Heterojunction Patents (Class 438/47)
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Patent number: 8729579Abstract: An illuminating device includes at least first and second nitride-based semiconductor light-emitting elements each having a semiconductor chip with an active layer region. The active layer region is at an angle of 1° or more with an m plane, and an angle formed by a normal line of a principal surface in the active layer region and a normal line of the m plane is 1° or more and 5° or less. The first and second nitride-based semiconductor light-emitting elements have thicknesses of d1 and d2, respectively, and emit the polarized light having wavelengths ?1 and ?2, respectively, where the inequalities of ?1<?2 and d1<d2 are satisfied.Type: GrantFiled: March 28, 2012Date of Patent: May 20, 2014Assignee: Panasonic CorporationInventors: Toshiya Yokogawa, Akira Inoue, Masaki Fujikane, Mitsuaki Oya, Atsushi Yamada, Tadashi Yano
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Patent number: 8729575Abstract: The semiconductor light emitting device according to an embodiment includes an N-type nitride semiconductor layer, a nitride semiconductor active layer disposed on the N-type nitride semiconductor layer, and a P-type nitride semiconductor layer disposed on the active layer. The P-type nitride semiconductor layer includes an aluminum gallium nitride layer. The indium concentration in the aluminum gallium nitride layer is between 1E18 atoms/cm3 and 1E20 atoms/cm3 inclusive. The carbon concentration is equal to or less than 6E17 atoms/cm3. Where the magnesium concentration is denoted by X and the acceptor concentration is denoted by Y, Y>{(?5.35e19)2?(X?2.70e19)2}1/2?4.63e19 holds.Type: GrantFiled: August 23, 2011Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Jongil Hwang, Hung Hung, Yasushi Hattori, Rei Hashimoto, Shinji Saito, Masaki Tohyama, Shinya Nunoue
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Patent number: 8729563Abstract: Solid state lighting (SSL) devices and methods are disclosed. A particular method includes forming an SSL formation structure having a CTE, selecting a first material of an interlayer structure to have a first material CTE greater than the substrate CTE, and selecting a second material based at least in part on the second material having a CTE less than the first material CTE. The intelayer structure is formed over the SSL formation structure e.g., with a first layer of the first material over the SSL formation structure, a portion of the second material over the first material, and a second layer of the first material over the second material. The CTE difference between the first and second materials can counteract a force placed on the formation structure by the first material. Particular formation structures can have an off-cut angle with a non-zero value of up to about 4.5 degrees.Type: GrantFiled: September 14, 2012Date of Patent: May 20, 2014Assignee: Micron Technology, Inc.Inventor: Ji-Soo Park
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Publication number: 20140134774Abstract: A method for making a light emitting diode chip includes following steps: providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof; forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer partly covering the protrusions to expose a part of each of the protrusions; etching the un-doped GaN layer to expose a top end of each of the protrusions; and forming an n-type GaN layer, an active layer, and a p-type GaN layer sequentially on the top ends of the protrusions and the un-doped GaN layer.Type: ApplicationFiled: August 30, 2013Publication date: May 15, 2014Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.Inventors: CHING-HSUEH CHIU, YA-WEN LIN, PO-MIN TU, SHIH-CHENG HUANG
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Publication number: 20140134775Abstract: A method for forming a light emitting device comprises forming a buffer layer having a plurality of layers comprising a substrate, an aluminum gallium nitride layer adjacent to the substrate, and a gallium nitride layer adjacent to the aluminum gallium nitride layer. During the formation of each of the plurality of layers, one or more process parameters are selected such that an individual layer of the plurality of layers is strained.Type: ApplicationFiled: January 17, 2014Publication date: May 15, 2014Applicant: TOSHIBA TECHNO CENTER INC.Inventors: Long YANG, Will FENWICK
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Publication number: 20140131726Abstract: There are provided a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting device includes a base layer configured of a group III nitride semiconductor, a polarity modifying layer formed on a group III element polar surface of the base layer, and a light emitting laminate having a multilayer structure of the group III nitride semiconductor formed on the polarity modifying layer, an upper surface of at least one layer in the multilayer structure being formed of an N polar surface.Type: ApplicationFiled: August 23, 2013Publication date: May 15, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Don LEE, Jong Uk SEO, Sang Heon HAN
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Publication number: 20140131730Abstract: A method of fabricating a heterostructure device, including (a) obtaining a first layer or substrate; (b) growing a second layer on the first layer or substrate; and (c) forming the second layer that is at least partially relaxed wherein (1) the first layer and the second layer have the same lattice structure but different lattice constants, (2) the first layer and the second layer form a heterojunction, and (3) the heterojunction forms an active area of a device or serves as a pseudo-substrate for the device.Type: ApplicationFiled: November 6, 2013Publication date: May 15, 2014Inventors: Stacia Keller, Carl J. Neufeld, Umesh K. Mishra, Steven P. DenBaars
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Publication number: 20140127848Abstract: Provided are a nitride semiconductor light-emitting device comprising a polycrystalline or amorphous substrate made of AlN; a plurality of dielectric patterns formed on the AlN substrate and having a stripe or lattice structure; a lateral epitaxially overgrown-nitride semiconductor layer formed on the AlN substrate having the dielectric patterns by Lateral Epitaxial Overgrowth; a first conductive nitride semiconductor layer formed on the nitride semiconductor layer; an active layer formed on the first conductive nitride semiconductor layer; and a second conductive nitride semiconductor layer formed on the active layer; and a process for producing the same.Type: ApplicationFiled: January 10, 2014Publication date: May 8, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong Hyun CHO, Masayoshi KOIKE, Yuji IMAI, Min Ho KIM, Bang Won OH, Hun Joo HAHM
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Patent number: 8716049Abstract: Techniques for crack-free growth of GaN, and related, films on larger-size substrates via spatially confined epitaxy are described.Type: GrantFiled: February 11, 2011Date of Patent: May 6, 2014Assignee: Applied Materials, Inc.Inventors: Jie Su, Olga Kryliouk
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Patent number: 8716044Abstract: A p-type cladding layer (3) of p-type semiconductor is formed over a substrate. An active layer (5) including a p-type semiconductor region is disposed over the p-type cladding layer. A buffer layer (10) of non-doped semiconductor is disposed over the active layer. A ridge-shaped n-type cladding layer (11) of n-type semiconductor is disposed over a partial surface of the buffer layer. The buffer layer on both sides of the ridge-shaped n-type cladding layer is thinner than the buffer layer just under the ridge-shaped n-type cladding layer.Type: GrantFiled: September 16, 2013Date of Patent: May 6, 2014Assignee: Fujitsu LimitedInventors: Tsuyoshi Yamamoto, Hisao Sudo
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Patent number: 8709846Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (GaN) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (InGaN) material directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN, and P-type GaN materials has a non-planar surface.Type: GrantFiled: June 26, 2013Date of Patent: April 29, 2014Assignee: Micron Technology, Inc.Inventors: Niraj Rana, Zaiyuan Ren
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Publication number: 20140110665Abstract: The embodiments of the present invention relate to a light emitting diode and manufacturing method thereof. The electroluminescent layer of the light-emitting diode is formed of graphene/compound semiconductor quantum dot composites.Type: ApplicationFiled: October 22, 2013Publication date: April 24, 2014Applicant: BOE Technology Group Co., Ltd.Inventors: Feng Zhang, Tianming Dai, Qi Yao
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Publication number: 20140105236Abstract: A semiconductor laser device includes an n-type clad layer, a first p-type clad layer and a ridge stripe. The device also includes an active layer interposed between the n-type clad layer and the first p-type clad layer, and a current-blocking layer formed on side surfaces of the ridge stripe. The ridge stripe of the device includes a second p-type clad layer formed into a ridge stripe shape on the opposite surface of the first p-type clad layer from the n-type clad layer. The ridge stripe is formed such that a first ridge width as the width of a surface of the second p-type clad layer exists on the same side as the first p-type clad layer and a second ridge width as the width of a surface of the second p-type clad layer exists on the opposite side from the first p-type clad layer.Type: ApplicationFiled: December 16, 2013Publication date: April 17, 2014Applicant: ROHM CO., LTD.Inventors: Yoshito NISHIOKA, Yoichi MUGINO, Tsuguki NOMA
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Patent number: 8697481Abstract: Multijunction solar cells having at least four subcells are disclosed, in which at least one of the subcells comprises a base layer formed of an alloy of one or more elements from group III on the periodic table, nitrogen, arsenic, and at least one element selected from the group consisting of Sb and Bi, and each of the subcells is substantially lattice matched. Methods of manufacturing solar cells and photovoltaic systems comprising at least one of the multijunction solar cells are also disclosed.Type: GrantFiled: December 7, 2012Date of Patent: April 15, 2014Assignee: Solar Junction CorporationInventors: Rebecca Elizabeth Jones-Albertus, Pranob Misra, Michael J. Sheldon, Homan B. Yuen, Ting Liu, Daniel Derkacs, Vijit Sabnis, Micahel West Wiemer, Ferran Suarez
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Patent number: 8697466Abstract: A method of manufacturing a nitride semiconductor device includes the step of forming a second nitride semiconductor layer having an inclined facet by metal-organic chemical vapor deposition, in which a molar flow ratio of a group V element gas to a group III element gas that are supplied to a growth chamber of a metal-organic chemical vapor deposition growth apparatus is set at 240 or less.Type: GrantFiled: September 13, 2012Date of Patent: April 15, 2014Assignee: Sharp Kabushiki KaishaInventor: Satoshi Komada
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Patent number: 8698197Abstract: The present invention is directed to a position sensing detector made of a photodiode having a semi insulating substrate layer; a buffered layer that is formed directly atop the semi-insulating substrate layer, an absorption layer that is formed directly atop the buffered layer substrate layer, a cap layer that is formed directly atop the absorption layer, a plurality of cathode electrodes electrically coupled to the buffered layer or directly to the cap layer, and at least one anode electrode electrically coupled to a p-type region in the cap layer. The position sensing detector has a photo-response non-uniformity of less than 2% and a position detection error of less than 10 ?m across the active area.Type: GrantFiled: February 13, 2013Date of Patent: April 15, 2014Assignee: OSI Optoelectronics, Inc.Inventors: Peter Steven Bui, Narayan Dass Taneja
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Publication number: 20140097456Abstract: A method for producing a light-emitting device includes the steps of: forming a layer containing In on a substrate in a reactor in which a Mg-containing raw material has been used; and forming an active layer including a nitride semiconductor on the layer containing In.Type: ApplicationFiled: October 8, 2013Publication date: April 10, 2014Applicant: CANON KABUSHIKI KAISHAInventor: Takeshi Kawashima
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Patent number: 8686451Abstract: An optoelectronic component (100) comprises a first semiconductor layer stack (101), which has an active layer (110) designed for the emission of radiation and a main area (111). A separating layer (103) is arranged on said main area, said separating layer forming a semitransparent mirror. The optoelectronic component comprises a second semiconductor layer stack (102), which is arranged at the separating layer and which has a further active layer (120) designed for the emission of radiation.Type: GrantFiled: January 19, 2009Date of Patent: April 1, 2014Assignee: OSRAM Opto Semiconductor GmbHInventors: Nikolaus Gmeinwieser, Berthold Hahn
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Patent number: 8686450Abstract: The present invention relates to a method of manufacturing a vertically-structured GaN-based light emitting diode. The method of manufacturing a vertically-structured GaN-based light emitting diode includes forming a GaN layer on a substrate; patterning the compound layer in a predetermined shape; forming an n-type GaN layer on the patterned compound layer through the epitaxial lateral over-growth process and sequentially forming an active layer and a p-type GaN layer on the n-type GaN layer; forming a structure supporting layer on the p-type GaN layer; sequentially removing the substrate and the GaN layer formed on the substrate after forming the structure supporting layer; removing the patterned compound layer exposed after removing the GaN layer so as to form an n-type GaN layer patterned in a concave shape; and forming an n-type electrode on the n-type GaN layer patterned in a concave shape.Type: GrantFiled: August 23, 2007Date of Patent: April 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jae Hoon Lee, Hee Seok Choi, Jeong Tak Oh, Su Yeol Lee
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Patent number: 8684749Abstract: A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits light when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device.Type: GrantFiled: August 5, 2013Date of Patent: April 1, 2014Assignee: Toshiba Techno Center Inc.Inventors: Steven Lester, Jeff Ramer, Jun Wu, Ling Zhang
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Patent number: 8685767Abstract: A double-metallic deposition process is used whereby adjacent layers of different metals are deposited on a substrate. The surface plasmon frequency of a base layer of a first metal is tuned by the surface plasmon frequency of a second layer of a second metal formed thereon. The amount of tuning is dependent upon the thickness of the metallic layers, and thus tuning can be achieved by varying the thicknesses of one or both of the metallic layers. In a preferred embodiment directed to enhanced LED technology in the green spectrum regime, a double-metallic Au/Ag layer comprising a base layer of gold (Au) followed by a second layer of silver (Ag) formed thereon is deposited on top of InGaN/GaN quantum wells (QWs) on a sapphire/GaN substrate.Type: GrantFiled: December 8, 2010Date of Patent: April 1, 2014Assignee: Lehigh UniversityInventors: Nelson Tansu, Hongping Zhao, Jing Zhang, Guangyu Liu
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Patent number: 8686397Abstract: A light emitting diode structure of (Al,Ga,In)N thin films grown on a gallium nitride (GaN) semipolar substrate by metal organic chemical vapor deposition (MOCVD) that exhibits reduced droop. The device structure includes a quantum well (QW) active region of two or more periods, n-type superlattice layers (n-SLs) located below the QW active region, and p-type superlattice layers (p-SLs) above the QW active region. The present invention also encompasses a method of fabricating such a device.Type: GrantFiled: June 11, 2012Date of Patent: April 1, 2014Assignee: The Regents of the University of CaliforniaInventors: Shuji Nakamura, Steven P. DenBaars, Shinichi Tanaka, Daniel F. Feezell, Yuji Zhao, Chih-Chien Pan
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Publication number: 20140084241Abstract: The invention provides a Group III nitride semiconductor light-emitting device in which the strain in the light-emitting layer is relaxed, thereby attaining high light emission efficiency, and a method for producing the device. The light-emitting device of the present invention has a substrate, a low-temperature buffer layer, an n-type contact layer, a first ESD layer, a second ESD layer, an n-side superlattice layer, a light-emitting layer, a p-side superlattice layer, a p-type contact layer, an n-type electrode N1, a p-type electrode P1, and a passivation film F1. The second ESD layer has pits X having a mean pit diameter D. The mean pit diameter D is 500 ? to 3,000 ?. An InGaN layer included in the n-side superlattice layer has a thickness Y satisfying the following condition: ?0.029×D+82.8?Y??0.029×D+102.8.Type: ApplicationFiled: August 12, 2013Publication date: March 27, 2014Applicant: TOYODA GOSEI CO., LTD.Inventors: Koji Okuno, Atsushi Miyazaki
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Publication number: 20140087508Abstract: The present invention provides a method for producing a Group III nitride semiconductor light-emitting device wherein a p-cladding layer has a uniform Mg concentration. A p-cladding layer having a superlattice structure in which AlGaN and InGaN are alternately and repeatedly deposited is formed in two stages of the former process and the latter process where the supply amount of the Mg dopant gas is different. The supply amount of the Mg dopant gas in the latter process is half or less than that in the former process. The thickness of a first p-cladding layer formed in the former process is 60% or less than that of the p-cladding layer, and 160 ? or less.Type: ApplicationFiled: August 15, 2013Publication date: March 27, 2014Applicant: TOYODA GOSEI CO., LTD.Inventors: Atsushi Miyazaki, Koji Okuno
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Publication number: 20140084240Abstract: A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.Type: ApplicationFiled: September 24, 2012Publication date: March 27, 2014Inventors: Hsin-Hua Hu, Andreas Bibl, John A. Higginson
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Publication number: 20140084276Abstract: Provided are a method and an apparatus for manufacturing an organic EL device which enable deposition of a vaporized material from an evaporation source onto a substrate in a desired pattern, while eliminating the need for a conventional strip-shaped shadow mask. A shielding portion 51 is configured to be switchable between a shield position where the shielding portion 51 is arranged between an evaporation source 4 and a substrate 81 so as to shield the substrate 81 and a shield release position where the shielding portion 51 is withdrawn from between the evaporation source 4 and the substrate 81 so as to release the shielding of the substrate 81. The shielding portion 51 is switched between the shield position and the shield release position while rotating together with a roller 3.Type: ApplicationFiled: December 10, 2012Publication date: March 27, 2014Applicant: NITTO DENKO CORPORATIONInventors: Ryohei Kakiuchi, Satoru Yamamoto, Kanako Hida
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Publication number: 20140084266Abstract: An electro-optic device includes a first electrode, an active layer formed over and electrically connected with the first electrode, a buffer layer formed over and electrically connected with the active layer, and a second electrode formed directly on the buffer layer. The second electrode includes a plurality of nanowires interconnected into a network of nanowires. The buffer layer provides a physical barrier between the active layer and the plurality of nanowires to prevent damage to the active layer while the second electrode is formed.Type: ApplicationFiled: March 15, 2013Publication date: March 27, 2014Applicant: The Regents of the University of CaliforniaInventor: The Regents of the University of California
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Patent number: 8679868Abstract: An improved bifacial solar cell is disclosed. In some embodiments, the front side includes an n-type field surface field, while the back side includes a p-type emitter. In other embodiments, the p-type emitter is on the front side. To maximize the diffusion of majority carriers and lower the series resistance between the contact and the substrate, the regions beneath the metal contacts are more heavily doped. Thus, regions of higher dopant concentration are created in at least one of the FSF or the emitter. These regions are created through the use of selective implants, which can be performed on one or two sides of the bifacial solar cell to improve efficiency.Type: GrantFiled: October 1, 2013Date of Patent: March 25, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Atul Gupta, Nicholas P. T. Bateman
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Patent number: 8680507Abstract: A DBR/gallium nitride/aluminum nitride base grown on a silicon substrate includes a Distributed Bragg Reflector (DBR) positioned on the silicon substrate. The DBR is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the DBR, an inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.Type: GrantFiled: January 16, 2013Date of Patent: March 25, 2014Assignee: Translucent, Inc.Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
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Patent number: 8680586Abstract: A semiconductor light emitting device including: a substrate made of GaAs; and a semiconductor layer formed on the substrate, in which part of the substrate on a side opposite to the semiconductor layer is removed by etching so that the semiconductor light emitting device has a thickness of not more than 60 ?m.Type: GrantFiled: January 4, 2008Date of Patent: March 25, 2014Assignee: ROHM Co., Ltd.Inventors: Tadahiro Hosomi, Kentaro Mineshita
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Patent number: 8680509Abstract: A nitride semiconductor device is provided, in which a superlattice strain buffer layer using AlGaN layers having a low Al content or GaN layers is formed with good flatness, and a nitride semiconductor layer with good flatness and crystallinity is formed on the superlattice strain buffer layer. A nitride semiconductor device includes a substrate; an AlN strain buffer layer made of AlN formed on the substrate; a superlattice strain buffer layer formed on the AlN strain buffer layer; and a nitride semiconductor layer formed on the superlattice strain buffer layer, and is characterized in that the superlattice strain buffer layer has a superlattice structure formed by alternately stacking first layers made of AlxGa1-xN (0?x?0.25), which further contain p-type impurity, and second layers made of AlN.Type: GrantFiled: August 23, 2010Date of Patent: March 25, 2014Assignee: Dowa Electronics Materials Co., Ltd.Inventors: Yoshikazu Ooshika, Tetsuya Matsuura
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Publication number: 20140077159Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a p-type layer, and a light emitting unit provided between the n-type layer and the p-type layer and including barrier layers and well layers. At least one of the barrier layers includes first and second portion layers. The first portion layer is disposed on a side of the n-type layer. The second portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the first portion layer. At least one of the well layers includes third and fourth portion layers. The third portion layer is disposed on a side of the n-type layer. The fourth portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the third portion layer.Type: ApplicationFiled: November 27, 2013Publication date: March 20, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshiki HIKOSAKA, Koichi Tachibana, Hajime Nago, Shinya Nunoue
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Publication number: 20140077158Abstract: A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.Type: ApplicationFiled: November 23, 2013Publication date: March 20, 2014Applicant: Sharp Laboratories of America, Inc.Inventors: Mark Albert Crowder, Changqing Zhan, Paul J. Schuele
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Publication number: 20140077219Abstract: A group-III nitride compound semiconductor light emitting element includes a substrate that has a main face on which an concave and convex portion is formed, a group-III nitride compound semiconductor layer that is formed on the main face of the substrate, and a clearance that is formed between the substrate and the group-III nitride compound semiconductor layer at a first region of the semiconductor light emitting element. In the first region, a portion of the group-III nitride compound semiconductor layer and a portion of the clearance are disposed in a concave of the concave and convex portion on a section through two adjacent top portions of the concave and convex portion and a bottom portion located between the adjacent top portions.Type: ApplicationFiled: September 16, 2013Publication date: March 20, 2014Applicant: Toyoda Gosei Co., Ltd.Inventors: Masao KAMIYA, Koichi Goshonoo, Shingo Totani, Takashi Kawai, Takahiro Mori, Koji Hirata
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Publication number: 20140077154Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).Type: ApplicationFiled: March 14, 2013Publication date: March 20, 2014Inventors: Maxim S Shatalov, Remigijus Gaska, Jinwei Yang, Michael Shur, Alexander Dobrinsky
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Publication number: 20140077153Abstract: The present disclosure involves a light-emitting device. The light-emitting device includes an n-doped gallium nitride (n-GaN) layer located over a substrate. A multiple quantum well (MQW) layer is located over the n-GaN layer. An electron-blocking layer is located over the MQW layer. A p-doped gallium nitride (p-GaN) layer is located over the electron-blocking layer. The light-emitting device includes a hole injection layer. In some embodiments, the hole injection layer includes a p-doped indium gallium nitride (p-InGaN) layer that is located in one of the three following locations: between the MQW layer and the electron-blocking layer; between the electron-blocking layer and the p-GaN layer; and inside the p-GaN layer.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: TSMC Solid State Lighting Ltd.Inventors: Zhen-Yu Li, Tzu-Te Yang, Hon-Way Lin, Chung-Pao Lin, Kuan-Chun Chen, Ching-Yu Chen, You-Da Lin, Hao-Chung Kuo
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Publication number: 20140070246Abstract: The invention relates to a light-emitting semiconductor component, comprising—a first semiconductor body (1), which comprises an active zone (11) in which during the operation of the light-emitting semiconductor component electromagnetic radiation is generated, at least some of which leaves the first semiconductor body (1) through a radiation exit surface (1a), and—a second semiconductor body (2), which is suitable for converting the electromagnetic radiation into converted electromagnetic radiation having a shorter wavelength, wherein—the first semiconductor body (1) and the second semiconductor body (2) are produced separately from each other,—the second semiconductor body (2) is electrically inactive, and—the second semiconductor body (2) is in direct contact with the radiation exit surface (1a) and is attached there to the first semiconductor body (1) without connecting means.Type: ApplicationFiled: March 7, 2012Publication date: March 13, 2014Applicant: OSRAM OPTO SEMICONDUCTORS GMBHInventors: Matthias Sabathil, Andreas Plößl, Hans-Jürgen Lugauer, Alexander Linkov, Patrick Rode
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Publication number: 20140073077Abstract: A method for epitaxial growth of a light emitting diode, includes following steps: providing a substrate; forming a buffer layer on the substrate; forming a first epitaxial layer on the buffer layer in a first temperature; forming a second epitaxial layer on the first epitaxial layer in a second temperature lower than the first temperature, thereby forming a first rough surface on the second epitaxial layer; etching the second epitaxial layer and the first epitaxial layer until a second rough surface is formed on the first epitaxial layer; forming a mask layer on the rough surface of the first epitaxial layer; partly etching the mask layer to form a plurality of protrusions with the first epitaxial layer exposed thereamong; and forming an N-type epitaxial layer, an active layer and a P-type epitaxial layer on the first epitaxial layer in sequence.Type: ApplicationFiled: August 5, 2013Publication date: March 13, 2014Applicant: Advanced Optoelectronic Technology, Inc.Inventors: YA-WEN LIN, SHIH-CHENG HUANG, PO-MIN TU
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Patent number: 8669129Abstract: One object of the present invention is to provide a method for producing a group III nitride semiconductor light-emitting device which has excellent productivity and produce a group III nitride semiconductor light-emitting device and a lamp, a method for producing a group III nitride semiconductor light-emitting device, in which a buffer layer (12) made of a group III nitride is laminated on a substrate (11), an n-type semiconductor layer (14) comprising a base layer (14a), a light-emitting layer (15), and a p-type semiconductor layer (16) are laminated on the buffer layer (12) in this order, comprising: a pretreatment step in which the substrate (11) is treated with plasma; a buffer layer formation step in which the buffer layer (12) having a composition represented by AlxGa1-xN (0?x<1) is formed on the pretreated substrate (11) by activating with plasma and reacting at least a metal gallium raw material and a gas containing a group V element; and a base layer formation step in which the base layer (14a)Type: GrantFiled: June 3, 2009Date of Patent: March 11, 2014Assignee: Toyoda Gosei Co., Ltd.Inventors: Hisayuki Miki, Yasunori Yokoyama, Takehiko Okabe, Kenzo Hanawa
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Patent number: 8664086Abstract: A method for manufacturing a semiconductor thin film device includes: forming a buffer layer on an Si (111) substrate and a single crystal semiconductor layer on the buffer layer; forming an island including the semiconductor layer, buffer layer, and a portion of the substrate; forming a coating layer on the island; etching the substrate along its Si (111) plane to release the island from the substrate, the coating layer serving as a mask; and bonding the released island to another substrate, a released surface of the released island contacting the another substrate. A semiconductor device includes a single crystal semiconductor layer other than Si, which has a semiconductor device formed on a front surface of an Si (111) layer lying in a (111) plane. The layer is bonded to another substrate with a back surface contacting the another substrate or a bonding layer formed on the another substrate.Type: GrantFiled: April 27, 2010Date of Patent: March 4, 2014Assignee: Oki Data CorporationInventor: Mitsuhiko Ogihara
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Patent number: 8664026Abstract: A method for fabricating a semiconductor lighting chip includes steps of providing a substrate with an epitaxial layer thereon. The epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer successively grown on the substrate. The epitaxial layer has dislocation defects traversing the first semiconductor layer, the active layer and the second semiconductor layer. The epitaxial layer is then subjected to an etching process which remove parts of the second semiconductor layer and the active layer along the dislocation defects to form recesses recessing from the second semiconductor layer to the active layer. Thereafter a first electrode and a second electrode are formed on the first semiconductor layer and the second semiconductor layer, respectively.Type: GrantFiled: August 17, 2011Date of Patent: March 4, 2014Assignee: Advanced Optoelectronic Technology, Inc.Inventors: Po-Min Tu, Shih-Cheng Huang
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VERTICAL LIGHT-EMITTING DEVICES HAVING PATTERNED EMITTING UNIT AND METHODS OF MANUFACTURING THE SAME
Publication number: 20140057381Abstract: Example embodiments are directed to a light-emitting device including a patterned emitting unit and a method of manufacturing the light-emitting device. The light-emitting device includes a first electrode on a top of a semiconductor layer, and a second electrode on a bottom of the semiconductor layer, wherein the semiconductor layer is a pattern array formed of a plurality of stacks. A space between the plurality of stacks is filled with an insulating layer, and the first electrode is on the insulating layer.Type: ApplicationFiled: October 30, 2013Publication date: February 27, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Hyung-su JEONG, Young-soo PARK, Su-hee CHAE, Bok-ki MIN, Jun-youn KIM, Hyun-gi HONG, Young-jo TAK, Jae-won LEE -
Publication number: 20140054599Abstract: A flexible semiconductor device and a method of manufacturing the flexible semiconductor device are provided. The flexible semiconductor device may include at least one vertical semiconductor element that is at least partly embedded in a flexible material layer. The flexible semiconductor device may further include a first electrode formed on a first surface of the flexible material layer and a second electrode formed on a second surface of the flexible material layer. A method of manufacturing a flexible semiconductor device may include separating a flexible material layer, in which the at least one vertical semiconductor element is embedded, from a substrate by weakening or degrading an adhesive force between an underlayer and a buffer layer by using a difference in coefficients of thermal expansion of the underlayer and the buffer layer.Type: ApplicationFiled: July 9, 2013Publication date: February 27, 2014Inventors: Jun-hee CHOI, Byoung-lyong CHOI, Tae-ho KIM
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Publication number: 20140054541Abstract: A method of manufacturing a quantum dot (QD) device includes: forming a first QD solution obtained by dispersing a plurality of QDs in a mixture of a solvent and an anti-solvent; and forming a first QD layer on a substrate structure by applying the first QD solution onto the substrate structure and naturally evaporating the first QD solution.Type: ApplicationFiled: April 8, 2013Publication date: February 27, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-young CHUNG, Kyung-sang CHO, Tae-ho KIM, Byoung-lyong CHOI
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Patent number: 8659005Abstract: A light emitting device comprising a staggered composition quantum well (QW) has a step-function-like profile in the QW, which provides higher radiative efficiency and optical gain by providing improved electron-hole wavefunction overlap. The staggered QW includes adjacent layers having distinctly different compositions. The staggered QW has adjacent layers Xn wherein X is a quantum well component and in one quantum well layer n is a material composition selected for emission at a first target light regime, and in at least one other quantum well layer n is a distinctly different composition for emission at a different target light regime. X may be an In-content layer and the multiple Xn-containing a step function In-content profile.Type: GrantFiled: December 24, 2007Date of Patent: February 25, 2014Assignee: Lehigh UniversityInventors: Nelson Tansu, Ronald A. Arif, Yik Khoon Ee, Hongping Zhao
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Patent number: 8658449Abstract: A method of manufacturing a semiconductor layer with which inactivation of impurity is able to be inhibited by a simple method, a semiconductor layer in which inactivation of impurity is inhibited, a method of manufacturing a laser diode with which inactivation of impurity is able to be inhibited by a simple method, and a laser diode including a semiconductor layer in which inactivation of impurity is inhibited are provided. In the method of manufacturing a semiconductor layer, after a semiconductor layer is formed by epitaxial growth with the use of AsH3, supply of AsH3 is stopped without separately supplying new gas when process temperature is 500 deg C. or more.Type: GrantFiled: March 31, 2010Date of Patent: February 25, 2014Assignee: Sony CorporationInventors: Naoki Jogan, Takahiro Arakida
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Publication number: 20140048792Abstract: The present invention provides an organic light emitting device comprising a first electrode, a second electrode, and one or more organic material layers disposed between the first electrode and the second electrode, and having an excellent life-span property by changing a dipole moment of a compound comprised in the organic material layers.Type: ApplicationFiled: October 5, 2012Publication date: February 20, 2014Inventors: Minseung Chun, Jungi Jang, Changhwan Shin, Seong So Kim, Hyungjin Lee, Sang Young Jeon, Chang Hwan Kim, Dong Sik Kim
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Publication number: 20140048818Abstract: A photoelectric conversion element of an embodiment is a photoelectric conversion element which performs photoelectric conversion by receiving illumination light having n light emission peaks having a peak energy Ap (eV) (where 1?p?n and 2?n) of 1.59?Ap?3.26 and a full width at half maximum Fp (eV) (where 1?p?n and 2?n), wherein the photoelectric conversion element includes m photoelectric conversion layers having a band gap energy Bq (eV) (where 1?q?m and 2?m?n), and the m photoelectric conversion layers each satisfy the relationship of Ap?Fp<Bq?Ap with respect to any one of the n light emission peaks.Type: ApplicationFiled: July 29, 2013Publication date: February 20, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Shinji SAITO, Rei HASHIMOTO, Mizunori EZAKI, Shinya NUNOUE, Hironori ASAI
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Patent number: 8653503Abstract: A high-power and high-efficiency light emitting device with emission wavelength (?peak) ranging from 280 nm to 360 nm is fabricated. The new device structure uses non-polar or semi-polar AlInN and AlInGaN alloys grown on a non-polar or semi-polar bulk GaN substrate.Type: GrantFiled: December 18, 2012Date of Patent: February 18, 2014Assignee: The Regents of the University of CaliforniaInventors: Roy B. Chung, Zhen Chen, James S. Speck, Steven P. DenBaars, Shuji Nakamura
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Patent number: 8653499Abstract: A light-emitting diode (LED) includes a first conductivity type semiconductor layer, a strain-relaxed layer over the first conductivity type semiconductor layer, an active layer over the strain-relaxed layer, and a second conductivity type semiconductor layer over the active layer. The strain-relaxed layer includes a strain-absorbed layer over the first conductivity type semiconductor layer and a surface-smoothing layer on the strain-absorbed layer filling the cavities. The strain-absorbed layer includes a plurality of cavities in a substantial hexagonal-pyramid form.Type: GrantFiled: June 6, 2011Date of Patent: February 18, 2014Assignee: Epistar CorporationInventor: Shih-Chang Lee