Abstract: One embodiment is a method of forming a circuit structure. The method comprises forming a first amorphous layer over a substrate; forming a first glue layer over and adjoining the first amorphous layer; forming a second amorphous layer over and adjoining the first glue layer; and forming a plurality of posts separated from each other by removing a first portion of the first amorphous layer and a first portion of the second amorphous layer. At least some of the plurality of posts each comprises a second portion of the first amorphous layer, a first portion of the first glue layer, and a second portion of the second amorphous layer.

Abstract: To realize a high productivity while maintaining excellent film deposition characteristics on a substrate even if a plurality of processing gases of different gas species are used.

Abstract: Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first electrode, where the semiconductive stack can have a thickness of about 700 angstroms (?) or less. Each of the at least one semiconductive material can have an associated band gap of about 4 electron volts (eV) or less and a second electrode can be formed on the semiconductive stack.

Abstract: It is an object to provide a homogeneous semiconductor film in which variation in the size of crystal grains is reduced. Alternatively, it is an object to provide a homogeneous semiconductor film and to achieve cost reduction. By introducing a glass substrate over which an amorphous semiconductor film is formed into a treatment atmosphere set at more than or equal to a temperature that is needed for crystallization, rapid heating due to heat conduction from the treatment atmosphere is performed so that the amorphous semiconductor film is crystallized. More specifically, for example, after the temperature of the treatment atmosphere is increased in advance to a temperature that is needed for crystallization, the substrate over which the semiconductor film is formed is put into the treatment atmosphere.

Abstract: A method for manufacturing is: forming an insulating film over a substrate; forming an amorphous semiconductor film over the insulating film; forming over the amorphous semiconductor film, a silicon nitride film in which a film thickness is equal to or more than 200 nm and equal to or less than 1000 nm, equal to or less than 10 atomic % of oxygen is included, and a relative proportion of nitrogen to silicon is equal to or more than 1.3 and equal to or less than 1.5; irradiating the amorphous semiconductor film with a continuous-wave laser light or a laser light with repetition rate of equal to or more than the wave length of 10 MHz transmitting the silicon nitride film to melt and later crystallize the amorphous semiconductor film to form a crystalline semiconductor film.

Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.

Abstract: Apparatus and method for plasma deposition of thin film photovoltaic materials at microwave frequencies. The apparatus avoids unintended deposition on windows or other microwave transmission elements that couple microwave energy to deposition species. The apparatus includes a microwave applicator with one or more conduits passing therethrough that carry deposition species. The applicator transfers microwave energy to the deposition species to activate or energize them to a reactive state. The conduits physically isolate deposition species that would react or otherwise combine to form a thin film material at the point of microwave power transfer and deliver the microwave-excited species to a deposition chamber. One or more supplemental material streams may be delivered directly to the deposition chamber without passing through the microwave applicator and may combine with deposition species exiting the one or more conduits to form a thin film material.

Abstract: Disclosed are atomic layer deposition method and a semiconductor device including the atomic layer, including the steps: placing a semiconductor substrate in an atomic layer deposition chamber; feeding a first precursor gas to the semiconductor substrate within the chamber to form a first discrete monolayer on the semiconductor substrate; feeding an inert purge gas to the semiconductor substrate within the chamber to remove the first precursor gas which has not formed the first discrete monolayer on the semiconductor substrate; feeding a second precursor gas to the chamber to react with the first precursor gas which has formed the first discrete monolayer, forming a discrete atomic size islands; and feeding an inert purge gas to the semiconductor substrate within the chamber to remove the second precursor gas which has not reacted with the first precursor gas and byproducts produced by the reaction between the first and the second precursor gases.

Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a semiconductor substrate, and an interconnection above the semiconductor substrate. The interconnection includes a co-catalyst layer, a catalyst layer on the co-catalyst layer, and a graphene layer on the catalyst layer. The co-catalyst layer includes a portion contacting the catalyst layer. The portion has a face-centered cubic structure with a (111) plane oriented parallel to a surface of the semiconductor substrate. The catalyst layer has a face-centered cubic structure with a (111) plane oriented parallel to the surface of the semiconductor substrate.

Abstract: A semiconductor memory device includes a transistor and a capacitor. The transistor includes: an insulating film in which a groove portion is provided; a pair of electrodes separated so that the groove portion is sandwiched therebetween; an oxide semiconductor film which is in contact with the pair of electrodes and side surfaces and a bottom surface of the groove portion and has a thickness value smaller than a depth value of the groove portion; a gate insulating film covering the oxide semiconductor film; and a gate electrode provided to overlap with the oxide semiconductor film with the gate insulating film positioned therebetween.

Abstract: A method of making a crystalline semiconductor structure provides a photonic device by employing low thermal budget annealing process. The method includes annealing a non-single crystal semiconductor film formed on a substrate to form a polycrystalline layer that includes a transition region adjacent to a surface of the film and a relatively thicker columnar region between the transition region and the substrate. The transition region includes small grains with random grain boundaries. The columnar region includes relatively larger columnar grains with substantially parallel grain boundaries that are substantially perpendicular to the substrate. The method further includes etching the surface to expose the columnar region having an irregular serrated surface.

Abstract: Provided is a photoelectric conversion device fabrication method that realizes both high productivity and high conversion efficiency by rapidly forming an n-layer having good coverage. The fabrication method for a photoelectric conversion device includes a step of forming a silicon photoelectric conversion layer on a substrate by a plasma CVD method. In the fabrication method for the photoelectric conversion device, the step of forming the photoelectric conversion layer includes a step of forming an i-layer formed of crystalline silicon and a step of forming, on the i-layer, an n-layer under a condition with a hydrogen dilution ratio of 0 to 10, inclusive.

Abstract: By an evacuation unit including first and second turbo molecular pumps connected in series, the ultimate pressure in a reaction chamber is reduced to ultra-high vacuum. By a knife-edge-type metal-seal flange, the amount of leakage in the reaction chamber is reduced. A microcrystalline semiconductor film and an amorphous semiconductor film are stacked in the same reaction chamber where the pressure is reduced to ultra-high vacuum. By forming the amorphous semiconductor film covering the surface of the microcrystalline semiconductor film, oxidation of the microcrystalline semiconductor film is prevented.

Abstract: The invention relates to a formulation which contains at least one silane and at least one carbon polymer in a solvent, and to the production of a silicon layer on a substrate which is coated with such a formulation.

Abstract: A fabricating method of a semiconductor stacking layer includes following steps. First, an amorphous silicon (?-Si) layer is formed on a substrate. Surface treatment is then performed on a surface of the ?-Si layer. After that, a doped microcrystalline silicon (?c-Si) layer is formed on the treated surface of the ?-Si layer, wherein interface defects existing between the ?-Si layer and the doped ?c-Si layer occupy an area in a cross-sectional region having a width of 1.5 micrometers and a thickness of 40 nanometers, and a ratio of the occupied area in the cross-sectional region is equal to or less than 10%. The method of fabricating the semiconductor stacking layer can be applied to a fabrication process of a semiconductor device to effectively reduce the interface defects of the semiconductor stacking layer.

Abstract: The present invention relates to a process for producing a doped silicon layer on a substrate, comprising the steps of (a) providing a liquid silane formulation and a substrate, (b) applying the liquid silane formulation to the substrate, (c) introducing electromagnetic and/or thermal energy to obtain an at least partly polymorphic silicon layer, (d) providing a liquid formulation which comprises at least one aluminium-containing metal complex, (e) applying this formulation to the silicon layer obtained after step (c) and then (f) heating the coating obtained after step (e) by introducing electromagnetic and/or thermal energy, which decomposes the formulation obtained after step (d) at least to metal and hydrogen, and then (g) cooling the coating obtained after step (f) to obtain an Al-doped or Al- and metal-doped silicon layer, to doped silicon layers obtainable by the process and to the use thereof for production of light-sensitive elements and electronic components.

Abstract: A semiconductor structure may include a polycrystalline substrate comprising a metal, the polycrystalline substrate having substantially randomly oriented grains, as well as a buffer layer disposed thereover. The buffer layer may comprise a plurality of islands having an average island spacing therebetween. A polycrystalline semiconductor layer is disposed over the buffer layer.

Abstract: In a first aspect, a method of forming a memory cell is provided that includes (1) forming a metal-insulator-metal (MIM) stack, the MIM stack including (a) a first conductive carbon layer; (b) a low-hydrogen, silicon-containing carbon layer above the first conductive carbon layer; and (c) a second conductive carbon layer above the low-hydrogen, silicon-containing carbon layer; and (2) forming a steering element coupled to the MIM stack. Numerous other aspects are provided.

Abstract: Embodiments of the present invention generally relate to methods of forming epitaxial layers and devices having epitaxial layers. The methods generally include forming a first epitaxial layer including phosphorus and carbon on a substrate, and then forming a second epitaxial layer including phosphorus and carbon on the first epitaxial layer. The second epitaxial layer has a lower phosphorus concentration than the first epitaxial layer, which allows for selective etching of the second epitaxial layer and undesired amorphous silicon or polysilicon deposited during the depositions. The substrate is then exposed to an etchant to remove the second epitaxial layer and undesired amorphous silicon or polysilicon. The carbon present in the first and second epitaxial layers reduces phosphorus diffusion, which allows for higher phosphorus doping concentrations. The increased phosphorus concentrations reduce the resistivity of the final device.

Abstract: A batch processing method for forming a structure including an amorphous carbon film includes performing a preliminary treatment of removing water from a surface of the underlying layer by heating the inside of the reaction chamber at a preliminary treatment temperature of 800 to 950° C. and supplying a preliminary treatment gas selected from the group consisting of nitrogen gas and ammonia gas into the reaction chamber while exhausting gas from inside the reaction chamber; and, then performing main CVD of forming an amorphous carbon film on the underlying layer by heating the inside of the reaction chamber at a main process temperature and supplying a hydrocarbon gas into the reaction chamber while exhausting gas from inside the reaction chamber.

Abstract: An organometal material gas is supplied into a low electron temperature and high density plasma excited by microwaves to form a thin film of a compound on a substrate as a film forming object. In this case, the temperature of a supply system for the organometal material gas is controlled by taking advantage of the relationship between the vapor pressure and temperature of the organometal material gas.

Abstract: Exact alignment of a recrystallized region, which is to be formed in an amorphous or polycrystalline film, is facilitated. An alignment mark is formed, which is usable in a step of forming an electronic device, such as a thin-film transistor, in the recrystallized region. In addition, in a step of obtaining a large-grain-sized crystal-phase semiconductor from a semiconductor film, a mark structure that is usable as an alignment mark in a subsequent step is formed on the semiconductor film in the same exposure step. Thus, the invention includes a light intensity modulation structure that modulates light and forms a light intensity distribution for crystallization, and a mark forming structure that modulates light and forms a light intensity distribution including a pattern with a predetermined shape, and also forms a mark indicative of a predetermined position on a crystallized region.

Abstract: A phase change memory may transition between two crystalline states. In one embodiment, the phase change material is a chalcogenide which transitions between face centered cubic and hexagonal states. Because these states are more stable, they are less prone to drift than the amorphous state conventionally utilized in phase change memories.

Abstract: A method for manufacturing a semiconductor device with high electric characteristics is provided. Part of a stacked semiconductor film in which an amorphous semiconductor film is provided on a crystalline semiconductor film is etched using a mixed gas including an HBr gas, a CF4 gas, and an oxygen gas, so that part of the crystalline semiconductor film provided in the stacked semiconductor film is exposed. Etching for forming a back channel portion of a thin film transistor is performed with the method for etching, whereby high electric characteristics can be provided for the thin film transistor.

Abstract: An amorphous oxide semiconductor contains at least one element selected from In, Ga, and Zn at an atomic ratio of InxGayZnz, wherein the density M of the amorphous oxide semiconductor is represented by the relational expression (1) below: M?0.94×(7.121x+5.941y+5.675z)/(x+y+z)??(1) where 0?x?1, 0?y?1, 0?z?1, and x+y+z?0.

Abstract: There is provided a method for producing an a-IGZO oxide thin film by sputtering, which can control the carrier density of the film to a given value with high reproducibility. The method is an amorphous In—Ga—Zn—O based oxide thin film production method including: providing a sintered oxide material consisting essentially of indium (In), gallium (Ga), zinc (Zn), and oxygen (O) as constituent elements, wherein the ratio [In]/([In]+[Ga]) of the number of indium atoms to the total number of indium and gallium atoms is from 20% to 80%, the ratio [Zn]/([In]+[Ga]+[Zn]) of the number of zinc atoms to the total number of indium, gallium and zinc atoms is from 10% to 50%, and the sintered oxide material has a specific resistance of 1.0×10?1 ?cm or less; and producing a film on a substrate by direct current sputtering at a sputtering power density of 2.5 to 5.5 W/cm2 using the sintered oxide material as a sputtering target.

Abstract: A resistive memory device includes a first conductive line on a substrate, a vertical selection diode comprising a nanowire or a nanotube and being arranged over the first conductive line, a resistive element including a resistive layer arranged over the vertical selection diode; and a second conductive line arranged over the resistive element.

Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Abstract: A method for manufacturing a nonvolatile storage device with a plurality of unit memory layers stacked therein is provided. Each of the unit memory layers includes: a first interconnect extending in a first direction; a second interconnect extending in a second direction; a recording unit sandwiched between the first and second interconnects and being capable of reversibly transitioning between a first state and a second state in response to a current supplied through the first and second interconnects; and a rectifying element sandwiched between the first interconnect and the recording unit and including at least one of p-type and n-type impurities. In the method, the first interconnect, the second interconnect, the recording unit, and a layer of an amorphous material including the at least one of p-type and n-type impurities used in the plurality of unit memory layers are formed at a temperature lower than a temperature at which the amorphous material is substantially crystallized.

Abstract: A method of forming an integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.

Abstract: An object is to provide a technique by which a semiconductor device including a high-performance and high-reliable transistor is manufactured. A protective conductive film which protects an oxide semiconductor layer when a wiring layer is formed from a conductive layer is formed between the oxide semiconductor layer and the conductive layer, and an etching process having two steps is performed. In a first etching step, an etching is performed under conditions that the protective conductive film is less etched than the conductive layer and the etching selectivity of the conductive layer to the protective conductive film is high. In a second etching step, etching is performed under conditions that the protective conductive film is more easily etched than the oxide semiconductor layer and the etching selectivity of the protective conductive film to the oxide semiconductor layer is high.

Abstract: Some embodiments include a method of providing a semiconductor device. The method can include: (a) providing a flexible substrate; (b) depositing at least one layer of material over the flexible substrate, wherein the deposition of the at least one layer of material over the flexible substrate occurs at a temperature of at least 180° C.; and (c) providing a diffusion barrier between a metal layer and an a-Si layer. Other embodiments are disclosed in this application.

Abstract: A method for forming a semiconductor film suitable for a practical photoelectric conversion device having favorable photoelectric conversion efficiency and adapted to volume production and increased substrate area, and a method for manufacturing a photoelectric conversion device including the semiconductor film are provided. The method for forming a semiconductor film manufactures the semiconductor film including amorphous structure by a plasma CVD method. The semiconductor film is an amorphous film of SiGe-based compound or a microcrystalline film of SiGe-based compound. The plasma CVD method controls bandgap in thickness direction of the semiconductor film by varying the ON or OFF time of electric power applied to generate a plasma and intermittently supplying the power. The ON time and OFF time of the power fall in a range where the duty ratio ON time/(ON time+OFF time)×100(%) is 10% or more and 50% or less.

Abstract: A method for etching is provided in which the etching selectivity of an amorphous semiconductor film to a crystalline semiconductor film is high. Part of a stacked semiconductor film in which an amorphous semiconductor film is provided on a crystalline semiconductor film is etched using a mixed gas of a Br-based gas, a F-based gas, and an oxygen gas, so that part of the crystalline semiconductor film provided in the stacked semiconductor film is exposed. Reduction in the film thickness of the exposed portion can be suppressed by performing the etching in such a manner. Moreover, when etching for forming a back channel portion of a thin film transistor is performed with the method for etching, favorable electric characteristics of the thin film transistor can be obtained. An insulating layer is preferably provided over the thin film transistor.

Abstract: An electronic device comprises a variable resistance memory element on a substrate. The variable resistance memory element comprises (i) an amorphous carbon layer comprising a hydrogen content of at least about 30 atomic percent, and a maximum leakage current of less than about 1×10?9 amps, and (ii) a pair of electrodes about the amorphous carbon layer. Methods of fabricating this and other devices are also described.

Abstract: Apparatus and method for plasma deposition of thin film photovoltaic materials at microwave frequencies. The apparatus inhibits deposition on windows or other microwave transmission elements that couple microwave energy to deposition species. The apparatus includes a microwave applicator with conduits passing therethrough that carry deposition species. The applicator transfers microwave energy to the deposition species to transform them to a reactive state conducive to formation of a thin film material. The conduits physically isolate deposition species that would react to form a thin film material at the point of microwave power transfer. The deposition species are separately energized and swept away from the point of power transfer to prevent thin film deposition. The invention allows for the ultrafast formation of silicon-containing amorphous semiconductors that exhibit high mobility, low porosity, little or no Staebler-Wronski degradation, and low defect concentration.

Abstract: Amorphous semiconductor films with enhanced charged carrier transport are disclosed. Also disclosed is a method for fabricating and treating the film to produce the enhanced transport. Also disclosed are semiconductor p-n junctions fabricated with the films which demonstrate the enhanced transport. The films are amorphous and include boron, carbon, and hydrogen.

Abstract: A method and apparatus for forming a thin film transistor is provided. A gate dielectric layer is formed, which may be a bilayer, the first layer deposited at a low rate and the second deposited at a high rate. In some embodiments, the first dielectric layer is a silicon rich silicon nitride layer. An active layer is formed, which may also be a bilayer, the first active layer deposited at a low rate and the second at a high rate. The thin film transistors described herein have superior mobility and stability under stress.

Abstract: A semiconductor device with an amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an aluminum oxide charge trapping layer on the a-Si p-i-n diode junction and a metal control gate overlying the aluminum oxide layer. A method is provided for making the a-Si MAS memory cell structure and can be repeated to integrate the structure three-dimensionally.

Abstract: A method of forming a two terminal device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a first side region, and a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms an opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element.

Abstract: Materials, devices, and methods for enhancing performance of electronic devices such as solar cells, fuels cells, LEDs, thermoelectric conversion devices, and other electronic devices are disclosed and described. A diamond-like carbon electronic device can include a conductive diamond-like carbon cathode having specified carbon, hydrogen and sp2 bonded carbon contents. In some cases, the sp2 bonded carbon content may be sufficient to provide the conductive diamond-like carbon material with a visible light transmissivity of greater than about 0.70. A charge carrier separation layer can be coupled adjacent and between the diamond-like carbon cathode and an anode. The conductive diamond-like carbon material of the present invention can be useful for any other application which can benefit from the use of conductive and transparent electrodes which are also chemically inert, radiation damage resistance, and are simple to manufacture.

Abstract: Germanium, tellurium, and/or antimony precursors are usefully employed to form germanium-, tellurium- and/or antimony-containing films, such as films of GeTe, GST, and thermoelectric germanium-containing films. Processes for using these precursors to form amorphous films are also described. Further described is the use of [{nBuC(iPrN)2}2Ge] or Ge butyl amidinate to form GeTe smooth amorphous films for phase change memory applications.

Abstract: According to one embodiment, a method of fabricating a semiconductor device is disclosed. The method can include forming an amorphous layer on a portion of a first silicon substrate having a first plane orientation, and irradiating with micro wave on the amorphous layer to transform from the amorphous layer into a crystalline layer having the first plane orientation.

Abstract: A method for obtaining a desired dopant profile of an emitter for a solar cell which includes depositing a first amorphous silicon layer having a first doping level over an upper surface of the crystalline silicon substrate, depositing a second amorphous silicon layer having a second doping level on the first amorphous silicon layer, and heating the crystalline silicon substrate and the first and second amorphous silicon layers to a temperature sufficient to cause solid phase epitaxial crystallization of the first and second amorphous silicon layers, such that the first and second amorphous silicon layers, after heating, have the same grain structure and crystal orientation as the underlying crystalline silicon substrate.

Abstract: On a translucent substrate, an insulating film having a refractive index n and an amorphous silicon film are deposited successively. By irradiating the amorphous silicon film with a laser beam having a beam shape of a band shape extending along a length direction with a wavelength ?, a plurality of times from a side of amorphous silicon film facing the insulating film, while an irradiation position of the laser beam is shifted each of the plurality of times in a width direction of the band shape by a distance smaller than a width dimension of the band shape, a polycrystalline silicon film is formed from the amorphous silicon film. Forming the polycrystalline silicon film forms crystal grain boundaries which extend in the width direction and are disposed at a mean spacing measured along the length direction and ranging from (?/n)×0.95 to (?/n)×1.

Abstract: In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of single crystal silicon carbide is prepared, an amorphous layer is formed on a portion of the semiconductor substrate where an electrode is to be formed, a metal layer is formed on the amorphous layer, and the electrode including the metal layer and a silicide layer is formed by irradiating the metal layer with a laser light in such a manner that a part of the metal layer reacts with the amorphous layer and forms the silicide layer.

Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a first gas mixture having a hydrogen containing gas to a silicon containing gas flow rate ratio greater than about 200:1 into the processing chamber, maintaining a first process pressure greater than about 6 Torr in the processing chamber to deposit a first microcrystalline silicon containing layer in presence of a plasma formed from the first gas mixture, supplying a second gas mixture into the processing chamber, and maintaining a second process pressure less than about 5 Torr in the processing chamber to deposit a second microcrystalline silicon containing layer in presence of a plasma formed from the second gas mixture.

Abstract: A semiconductor element of the electric circuit includes a semiconductor layer over a gate electrode. The semiconductor layer of the semiconductor element is formed of a layer including polycrystalline silicon which is obtained by crystallizing amorphous silicon by heat treatment or laser irradiation, over a substrate. The obtained layer including polycrystalline silicon is also used for a structure layer such as a movable electrode of a structure body. Therefore, the structure body and the electric circuit for controlling the structure body can be formed over one substrate. As a result, a micromachine can be miniaturized. Further, assembly and packaging are unnecessary, so that manufacturing cost can be reduced.

Abstract: Zinc sulfide (ZnS) single crystals and multi-grain ZnS crystals are suitable for many applications. The disclosed method produces ZnS single crystals or multi-grain ZnS crystals. More specifically, ZnS single crystals or multi-grain ZnS crystals of pure or substantially pure hexagonal wurtzite structure with sufficiently high purity and crystalline perfection to be used to fabricate components and devices including but not limited to optical components (useful in the infrared (IR) & visible spectrum range of 0.34-14 ?m), photoluminescence devices, cathode luminescence devices, electroluminescence devices, semiconductor devices, and IR laser gain mediums (in the wave length range of 1-5 ?m).

Abstract: An object is to provide a method for forming an oxide semiconductor film with little variation in electrical characteristics. Another object is to provide a method for manufacturing a semiconductor device including an oxide semiconductor film with little variation in electrical characteristics. To reduce the amount of light scattered by a substrate stage or the amount of the scattered light which travels to enter a light-transmitting oxide semiconductor layer when the light-transmitting oxide semiconductor layer is patterned, a layer having a function of preventing light transmission may be provided in a lower layer than a photoresist layer so that light does not reach the substrate stage. In addition, a semiconductor device may be manufactured using the oxide semiconductor layer formed by the above patterning method.