Providing Nondopant Ion (e.g., Proton, Etc.) Patents (Class 438/520)
  • Patent number: 10056488
    Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: August 21, 2018
    Assignee: Intel Corporation
    Inventors: Sameer Pradhan, Jeanne Luce
  • Patent number: 9722076
    Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions disposed in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.
    Type: Grant
    Filed: August 29, 2015
    Date of Patent: August 1, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURNING CO., LTD.
    Inventors: Chung-Ren Sun, Shiu-Ko Jangjian, Kun-Ei Chen, Chun-Che Lin
  • Patent number: 9117665
    Abstract: In accordance with an embodiment, a nonvolatile semiconductor memory device includes a substrate including a semiconductor layer including an active region, a first insulating film on the active region, a charge storage layer on the first insulating film, an element isolation insulating film defining the active region, a second insulating film, and a control electrode on the second insulating film. The top surface of the element isolation insulating film is placed at a height between the top surface and the bottom surface of the charge storage layer, thereby forming a step constituted of the charge storage layer and the element isolation insulating film. The second insulating film covers the step and the charge storage layer. The second insulating film includes a first silicon oxide film and a first silicon nitride film on the first silicon oxide film. Nitrogen concentration in the first silicon nitride film is non-uniform.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: August 25, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masayuki Tanaka
  • Patent number: 9029184
    Abstract: To provide a resource-saving photoelectric conversion device with excellent photoelectric conversion characteristics. Thin part of a single crystal semiconductor substrate, typically a single crystal silicon substrate, is detached to structure a photoelectric conversion device using a thin single crystal semiconductor layer, which is the detached thin part of the single crystal semiconductor substrate. The thin part of the single crystal semiconductor substrate is detached by a method in which a substrate is irradiated with ions accelerated by voltage, or a method in which a substrate is irradiated with a laser beam which makes multiphoton absorption occur. A so-called tandem-type photoelectric conversion device is obtained by stacking a unit cell including a non-single-crystal semiconductor layer over the detached thin part of the single crystal semiconductor substrate.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: May 12, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akihisa Shimomura
  • Patent number: 9020002
    Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of compound semiconductor material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. A silicon laser intermixed integrated device in accordance with one or more embodiments of the present invention comprises a silicon-on-insulator substrate, comprising at least one waveguide in a top surface, and a compound semiconductor substrate comprising a gain layer, the compound semiconductor substrate being subjected to a quantum well intermixing process, wherein the upper surface of the compound semiconductor substrate is bonded to the top surface of the silicon-on-insulator substrate.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: April 28, 2015
    Assignee: The Regents of the University of California
    Inventors: Matthew N. Sysak, John E. Bowers, Alexander W. Fang, Hyundai Park
  • Patent number: 8890291
    Abstract: A method of manufacturing a silicon wafer provides a silicon wafer which can reduce the precipitation of oxygen to prevent a wafer deformation from being generated and can prevent a slip extension due to boat scratches and transfer scratches serving as a reason for a decrease in wafer strength, even when the wafer is provided to a rapid temperature-rising-and-falling thermal treatment process.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: November 18, 2014
    Assignee: Sumco Corporation
    Inventors: Toshiaki Ono, Wataru Ito, Jun Fujise
  • Patent number: 8846482
    Abstract: A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: September 30, 2014
    Assignee: Avogy, Inc.
    Inventors: David P. Bour, Richard J. Brown, Isik C. Kizilyalli, Thomas R. Prunty, Linda Romano, Andrew P. Edwards, Hui Nie, Mahdan Raj
  • Patent number: 8772878
    Abstract: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: July 8, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Vassilios Papageorgiou, Belinda Hannon
  • Patent number: 8748253
    Abstract: An integrated circuit includes logic circuits of NMOS and PMOS transistors, and memory cells with NMOS and PMOS transistors. A common NSD implant mask exposes source and drain regions of a logic NMOS transistor and a memory NMOS transistor. The source and drain regions of the logic NMOS transistor and the memory NMOS transistor are concurrently implanted at a cryogenic temperature with an amorphizing species followed by arsenic. Phosphorus is concurrently implanted in the source and drain regions of the logic NMOS transistor and the memory NMOS transistor. The source and drain regions of the logic NMOS transistor are further implanted with phosphorus at a non-cryogenic temperature while the memory NMOS transistor is covered by a mask which blocks the phosphorus.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: June 10, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Shashank Sureshchandra Ekbote
  • Patent number: 8741720
    Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: June 3, 2014
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
  • Patent number: 8704229
    Abstract: Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: April 22, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Peter Javorka, Glyn Braithwaite
  • Patent number: 8703596
    Abstract: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in a first direction parallel to the surface of the silicon substrate, and stressor films formed on the silicon substrate between the channel region and the buried semiconductor regions in contact with the silicon substrate, for applying to the silicon substrate a second stress in a second direction which is opposite to the first direction.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 22, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8658522
    Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) preconditioning a process chamber with an aggressive plasma; (2) loading a substrate into the process chamber; and (3) performing plasma nitridation on the substrate within the process chamber. The process chamber is preconditioned using a plasma power that is at least 150% higher than a plasma power used during plasma nitridation of the substrate. Numerous other aspects are provided.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: February 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Tatsuya Sato, Patricia M. Liu, Fanos Christodoulou
  • Patent number: 8559478
    Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of compound semiconductor material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. A silicon laser intermixed integrated device in accordance with one or more embodiments of the present invention comprises a silicon-on-insulator substrate, comprising at least one waveguide in a top surface, and a compound semiconductor substrate comprising a gain layer, the compound semiconductor substrate being subjected to a quantum well intermixing process, wherein the upper surface of the compound semiconductor substrate is bonded to the top surface of the silicon-on-insulator substrate.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: October 15, 2013
    Assignee: The Regents of the University of California
    Inventors: Matthew N. Sysak, John E. Bowers, Alexander W. Fang, Hyundai Park
  • Patent number: 8546245
    Abstract: Provided is a method for manufacturing a low-cost bonded wafer (8) which allows bulk crystals of a wide bandgap semiconductor (1) to be transferred onto a handle substrate (3) as thinly as possible without breaking the substrate. More specifically, provided is a method for manufacturing a bonded wafer (8) by forming a wide bandgap semiconductor film (4) on a surface of a handle substrate (3), the method comprising a step of implanting ions from a surface (5) of a wide bandgap semiconductor substrate (1) having a bandgap of 2.8 eV or more to form an ion-implanted layer (2), a step of applying a surface activation treatment to at least one of the surface of the handle substrate (3) and the ion-implanted surface (5) of the wide bandgap semiconductor substrate (1), a step of bonding the surface (5) of the wide bandgap semiconductor substrate (1) and the surface of the handle substrate (3) to obtain bonded substrates (6), a step of applying a heat treatment to the bonded substrates (6) at a temperature of 150° C.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: October 1, 2013
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Shoji Akiyama
  • Patent number: 8502284
    Abstract: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in a first direction parallel to the surface of the silicon substrate, and stressor films formed on the silicon substrate between the channel region and the buried semiconductor regions in contact with the silicon substrate, for applying to the silicon substrate a second stress in a second direction which is opposite to the first direction.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: August 6, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8471307
    Abstract: An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si—Ge, carbon and boron. The first PSD layer is Si—Ge and includes carbon at a density between 5×1019 and 2×1020 atoms/cm3. The second PSD layer is Si—Ge and includes carbon at a density between 5×1019 atoms/cm3 and 2×1020 atoms/cm3 and boron at a density above 5×1019 atoms/cm3. The third PSD layer is silicon or Si—Ge, includes boron at a density above 5×1019 atoms/cm3 and is substantially free of carbon. After formation of the three layer epitaxial stack, the first PSD layer has a boron density less than 10 percent of the boron density in the second PSD layer. A process for forming an integrated circuit containing a PMOS transistor with a three layer PSD stack in PSD recesses.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: June 25, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Rajesh B. Khamankar, Haowen Bu, Douglas Tad Grider
  • Patent number: 8415231
    Abstract: A photovoltaic device uses a single crystal or polycrystalline semiconductor layer which is separated from a single crystal or polycrystalline semiconductor substrate as a photoelectric conversion layer and has a SOI structure in which the semiconductor layer is bonded to a substrate having an insulating surface or an insulating substrate. A single crystal semiconductor layer which is a separated surface layer part of a single crystal semiconductor substrate and is transferred is used as a photoelectric conversion layer and includes an impurity semiconductor layer to which hydrogen or halogen is added on a light incidence surface or on an opposite surface. The semiconductor layer is fixed to a substrate having an insulating surface or an insulating substrate.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: April 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai
  • Patent number: 8389385
    Abstract: Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: March 5, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, Gurtej S. Sandhu, John Smythe
  • Patent number: 8367532
    Abstract: A semiconductor device in one embodiment has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second connection region, of a field stop zone for spatially delimiting a space charge zone that can be formed in the semiconductor volume, and of an anode region adjoining the first connection region. The dopant concentration profile within the semiconductor volume is configured such that the integral of the ionized dopant charge over the semiconductor volume, proceeding from an interface of the anode region which faces the second connection region, in the direction of the second connection region, reaches a quantity of charge corresponding to the breakdown charge of the semiconductor device only near the interface of the field stop zone which faces the second connection region.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: February 5, 2013
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Hans-Joachim Schulze, Frank Hille, Holger Schulze, Manfred Pfaffenlehner, Carsten Schäffer, Franz-Josef Niedernostheide
  • Patent number: 8314019
    Abstract: A method of fabricating a power semiconductor component having a semiconductor body having at least two main surfaces includes applying a layer of a metallization on at least one of the main surfaces. The layer has a thickness of at least 15 ?m and serves as a heat sink. The method also includes producing a field stop zone in the semiconductor body by implantation of protons or helium through the layer.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: November 20, 2012
    Assignee: Infineon Technologies AG
    Inventors: Frank Hille, Hans-Joachim Schulze
  • Patent number: 8293619
    Abstract: A film of material may be formed by providing a semiconductor substrate having a surface region and a cleave region located at a predetermined depth beneath the surface region. During a process of cleaving the film from the substrate, shear in the cleave region is carefully controlled to achieve controlled propagation by either KII or energy propagation control. According to certain embodiments, an in-plane shear component (KII) is maintained near zero by adiabatic heating of silicon through exposure to E-beam radiation. According to other embodiments, a surface heating source in combination with an implanted layer serves to guide fracture propagation through the cleave sequence.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: October 23, 2012
    Assignee: Silicon Genesis Corporation
    Inventor: Francois J. Henley
  • Patent number: 8288257
    Abstract: Methods for implanting material into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, a method for implanting material into a substrate includes providing a substrate into a processing chamber, the substrate comprising a substrate surface having a material layer formed thereon, generating a first plasma of a non-dopant processing gas, exposing the material layer to the plasma of the non-dopant processing gas, generating a second plasma of a dopant processing gas including a reacting gas adapted to produce dopant ions, and implanting dopant ions from the plasma into the material layer. The method may further include a cleaning or etch process.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: October 16, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Matthew D. Scotney-Castle, Majeed A. Foad, Peter I. Porshnev
  • Patent number: 8236675
    Abstract: A method is proposed for the fabrication of the gate electrode of a semiconductor device such that the effects of gate depletion are minimized. The method is comprised of a dual deposition process wherein the first step is a very thin layer that is doped very heavily by ion implantation. The second deposition, with an associated ion implant for doping, completes the gate electrode. With the two-deposition process, it is possible to maximize the doping at the gate electrode/gate dielectric interface while minimizing risk of boron penetration of the gate dielectric. A further development of this method includes the patterning of both gate electrode layers with the advantage of utilizing the drain extension and source/drain implants as the gate doping implants and the option of offsetting the two patterns to create an asymmetric device.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: August 7, 2012
    Assignee: SemEquip, Inc.
    Inventors: Wade A. Krull, Dale C. Jacobson
  • Patent number: 8124509
    Abstract: The porosity of a diamond film may be increased and its dielectric constant lowered by exposing a film containing sp3 hybridization to ion implantation. The implantation produces a greater concentration of sp2 hybridizations. The sp2 hybridizations may then be selectively etched, for example, using atomic hydrogen plasma to increase the porosity of the film. A series of layers may be deposited and successively treated in the same fashion to build up a composite, porous diamond film.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: February 28, 2012
    Assignee: Intel Corporation
    Inventors: Kramadhati V. Ravi, Yuli Chakk
  • Patent number: 8101488
    Abstract: Embodiments of the present invention provide for a system for accelerating hydrogen ions. A hydrogen generator holding a supply of water is configured to generate a flow of hydrogen gas from the supply of water. An ion source structure is configured to generate a plurality of hydrogen ions from the flow of hydrogen gas. An accelerator tube is configured to accelerate the plurality of hydrogen ions. The supply of water has an isotopic ratio of deuterium that is smaller than the isotopic ratio of deuterium in Vienna Standard Mean Ocean Water.
    Type: Grant
    Filed: December 25, 2010
    Date of Patent: January 24, 2012
    Assignee: Twin Creeks Technologies, Inc.
    Inventors: Theodore H. Smick, Steven Richards, Geoffrey Ryding, Kenneth H Purser
  • Patent number: 8039375
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; implanting carbon into the semiconductor substrate; and implanting an n-type impurity into the semiconductor substrate to form a lightly doped source/drain (LDD) region, wherein the n-type impurity comprises more than one phosphorous atom. The n-type impurity may include phosphorous dimer or phosphorous tetramer.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: October 18, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Feng Nieh, Keh-Chiang Ku, Nai-Han Cheng, Chi-Chun Chen, Li-Te S. Lin
  • Patent number: 8039330
    Abstract: The invention is directed to a method for manufacturing a semiconductor. The method comprises steps of providing a substrate having a gate structure formed thereon and forming a source/drain extension region in the substrate adjacent to the gate structure. A spacer is formed on the sidewall of the gate structure and a source/drain region is formed in the substrate adjacent to the spacer but away from the gate structure. A bevel carbon implantation process is performed to implant a plurality carbon atoms into the substrate and a metal silicide layer is formed on the gate structure and the source/drain region.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: October 18, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Li-Shian Jeng, Kun-Hsien Lee, Wen-Han Hung, Tzyy-Ming Cheng
  • Patent number: 8003503
    Abstract: A method of forming a semiconductor device includes providing a dielectric film on a substrate, depositing a metal-containing gate electrode film over the dielectric film, and modifying a surface layer of the metal-containing gate electrode film by exposing the metal-containing gate electrode film to a process gas containing an oxygen-containing gas, a nitrogen-containing gas, or an oxygen- and nitrogen-containing gas, where a thickness of the modified surface layer is less than a thickness of the metal-containing gate electrode film. The method further includes, heat-treating the modified metal-containing gate electrode film to form a stressed metal-containing gate electrode film that exhibits stress over the substrate.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: August 23, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Robert D Clark
  • Patent number: 7982289
    Abstract: A wafer includes a wafer frontside and a region adjacent to the device surface, wherein the region includes vacancy-oxygen complexes and the wafer frontside includes a predetermined surface structure to form thereon a device with a desired property.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: July 19, 2011
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Hans-Joerg Timme, Helmut Strack
  • Patent number: 7981707
    Abstract: The method of the invention consists of implanting ions into the surface of multilayer optical waveguides, in the highly doped layer, in a defined pattern so as to modify the refractive index of this layer.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: July 19, 2011
    Assignee: Thales
    Inventors: Hideaki Page, Carlo Sirtori, Alfredo De Rossi
  • Patent number: 7943468
    Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: May 17, 2011
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
  • Patent number: 7927975
    Abstract: Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: April 19, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, Gurtej S. Sandhu, John Smythe
  • Patent number: 7923359
    Abstract: There is a process for reducing the sheet resistance of phosphorus-implanted poly-silicon. In an example embodiment, there is an MOS transistor structure. The structure has a gate region, drain region and a source region. A method for reducing the sheet resistance of the gate region comprises depositing intrinsic amorphous silicon at a predetermined temperature onto the gate region. An amorphizing species is implanted into the intrinsic amorphous silicon. Phosphorus species are then implanted into the gate region of the MOS transistor structure. A feature of this embodiment includes using Ar+ as the amorphizing species.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: April 12, 2011
    Assignee: NXP B.V.
    Inventors: Wolfgang Euen, Stephan Gross
  • Patent number: 7902050
    Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) preconditioning a process chamber with an aggressive plasma; (2) loading a substrate into the process chamber; and (3) performing plasma nitridation on the substrate within the process chamber. The process chamber is preconditioned using a plasma power that is at least 150% higher than a plasma power used during plasma nitridation of the substrate. Numerous other aspects are provided.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: March 8, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Tatsuya Sato, Patricia M. Liu, Fanos Christodoulou
  • Patent number: 7879667
    Abstract: A technique is presented which provides for a selective pre-amorphization of source/drain regions of a transistor while preventing pre-amorphization of a gate electrode of the transistor. Illustrative embodiments include the formation of a pre-amorphization implant blocking material over the gate electrode. Further illustrative embodiments include inducing a strain in a channel region by use of various stressors.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: February 1, 2011
    Assignee: Globalfoundries Inc.
    Inventors: Anthony Mowry, Markus Lenski, Andy Wei, Roman Boschke
  • Patent number: 7838401
    Abstract: A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so as to be offset from the front edge of a source/drain extension in direction away from the gate electrode and to surround as profile the associated source/drain impurity diffusion region.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: November 23, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Ohta, Kenichi Okabe
  • Patent number: 7795120
    Abstract: A 13C diamond is doped by proton induced transmutation. P-type doping is achieved by the 13C(p,??)10B reaction. N-type doping is achieved by the 13C(p,?)14N reaction. The transmutation reaction that occurs is determined by selection of proton beam energy. Stacks of junctions each calculated to be in the order of 10 nm thick have been achieved.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: September 14, 2010
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Jack L. Price, Noel A. Guardala, Michael G. Pravica
  • Patent number: 7767583
    Abstract: Embodiments of this method improve the results of a chemical mechanical polishing (CMP) process. A surface is implanted with a species, such as, for example, Si, Ge, As, B, P, H, He, Ne, Ar, Kr, Xe, and C. The implant of this species will at least affect dishing, erosion, and polishing rates of the CMP process. The species may be selected in one embodiment to either accelerate or decelerate the CMP process. The dose of the species may be varied over the surface in one particular embodiment.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: August 3, 2010
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Deepak Ramappa, Thirumal Thanigaivelan
  • Patent number: 7754590
    Abstract: Some embodiments of the invention relate to manufacturing a semiconductor device with an implantation layer on a semiconductor substrate including a method of manufacturing such an implantation layer, wherein said implantation layer is formed in an implantation step at a predetermined depth of penetration, determined from a top surface of said semiconductor substrate, using a particle beam, by increasing its path distance to a main implantation peak and correspondingly increasing the energy level of said particle beam for producing an undamaged implantation layer having a thickness that is increased significantly compared with the thickness of an implantation layer that would be produced at said predetermined depth of penetration using a particle beam with non-increased path distance and energy level.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: July 13, 2010
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Holger Schulze, Andreas Kyek
  • Patent number: 7674668
    Abstract: After a gate electrode is formed on a main surface of a semiconductor substrate, low concentration layers are formed on the main surface of the semiconductor substrate by implanting impurities therein, with using the gate electrode as a mask. Thereafter, first sidewalls and second sidewalls are formed on the both side surfaces of the gate electrode. Subsequently, nitrogen or the like is ion-implanted into the semiconductor substrate, with using the first sidewalls, the second sidewalls and the gate electrode as a mask, thereby forming a crystallization-control region (CCR) on the main surface of the semiconductor substrate. Then, after the second sidewalls are removed, high concentration layers for a source and a drain are formed on the main surface of the semiconductor substrate.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: March 9, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Norio Ishitsuka, Nobuyoshi Hattori, Tomio Iwasaki
  • Patent number: 7662680
    Abstract: A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities and carbide precipitates in the substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, annealing the substrate such that at least a part of the crystallographic defects are eliminated using the micro-cavities and the carbide precipitates, and wherein the semiconductor element is formed using the doping atoms.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: February 16, 2010
    Assignee: Infineon Technologies AG
    Inventor: Luis-Felipe Giles
  • Patent number: 7645676
    Abstract: Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: January 12, 2010
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Robert J. Gauthier, David Vaclav Horak, Charles William Koburger, III, Jack Allan Mandelman, William Robert Tonti
  • Patent number: 7598162
    Abstract: It is an object to provide a method of manufacturing a semiconductor device capable of forming a MOS transistor of high performance, comprising the steps of forming a gate electrode on a semiconductor substrate via a gate-insulating film (step S1), introducing a impurity into the semiconductor substrate using the gate electrode as a mask (step S7), introducing a diffusion-controlling substance into the semiconductor substrate to control the diffusion of the impurity (step S8), forming a side wall-insulating film on each side surface of the gate electrode (step S9), deeply introducing impurity into the semiconductor substrate using the gate electrode and the side wall-insulating film as masks (step S10), activating the impurity by the annealing treatment using a rapid thermal annealing method (step S11), and further activating the impurity by the millisecond annealing treatment (step S12).
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: October 6, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tomonari Yamamoto, Tomohiro Kubo
  • Patent number: 7544549
    Abstract: Upon manufacture of a semiconductor device provided with a source region and a drain region formed by activating, through anneal, an n-type first dopant ion-implanted in a p-type device forming area provided in a semiconductor layer formed on an insulator, and a body region, (a) ion implantation of Ar in a boundary region between the source and drain regions to be formed, which corresponds to a region lying in a predeterminate area for forming the body region, and (b) high-temperature anneal for partly recovering crystal defects produced by the ion implantation of the Ar at a temperature higher than the anneal for activation of the first dopant are carried out prior to the ion-implantation of the first dopant.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: June 9, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yasuhiro Domae
  • Patent number: 7494906
    Abstract: A dislocation region is formed by implanting a light inert species, such as hydrogen, to a specified depth and with a high concentration, and by heat treating the inert species to create “nano” bubbles, which enable a certain mechanical decoupling to underlying device regions, thereby allowing a more efficient creation of strain that is induced by an external stress-generating source. In this way, strain may be created in a channel region of a field effect transistor by, for instance, a stress layer or sidewall spacers formed in the vicinity of the channel region.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: February 24, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thorsten Kammler, Martin Gerhardt, Frank Wirbeleit
  • Patent number: 7494852
    Abstract: A method of forming a surface Ge-containing channel which can be used to fabricate a Ge-based field effect transistor (FET) which can be applied to semiconductor-on-insulator substrates (SOIs) is provided. The disclosed method uses Ge-containing ion beams, such as cluster ion beams, to create a strained Ge-containing rich region at or near a surface of a SOI substrate. The Ge-containing rich region can be present continuously across the entire surface of the semiconductor substrate, or it can be present as a discrete region at a predetermined surface portion of the semiconductor substrate.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: February 24, 2009
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Bruce B. Doris, Devendra K. Sadana
  • Patent number: 7479431
    Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: January 20, 2009
    Assignee: Intel Corporation
    Inventors: Michael L. Hattendorf, Jack Hwang, Anand Murthy, Andrew N. Westmeyer
  • Patent number: 7465633
    Abstract: Methods of forming capacitor-free DRAM cells include forming a field effect transistor by forming a first semiconductor wafer having a channel region protrusion extending therefrom and surrounding the channel region protrusion by an electrical isolation region. A portion of a backside of the first semiconductor wafer is then removed to define a semiconductor layer having a primary surface extending opposite the channel region protrusion and the electrical isolation region. A gate electrode is formed on the primary surface. The gate electrode extends opposite the channel region protrusion. The source and drain regions are formed in the semiconductor layer, on opposite sides of the gate electrode.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: December 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-whan Song, Chang-kyun Kim
  • Patent number: 7422936
    Abstract: Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate. The spacer layer is then etched to form a sidewall spacer. An interlayer dielectric is applied over the gate structure with the sidewall spacer. The interlayer dielectric has a second polish rate higher than the first polish rate. A hard mask may also be applied over the gate structure and implanted so that the hard mask may be more readily removed.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Chris E. Barns, Matt Prince, Mark L. Doczy, Justin K. Brask, Jack Kavalieros