Abstract: A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode.

Abstract: Disclosed is a method for manufacturing a semiconductor device comprising implanting ions of an impurity element into a semiconductor region, implanting, into the semiconductor region, ions of a predetermined element which is a group IV element or an element having the same conductivity type as the impurity element and larger in mass number than the impurity element, and irradiating a region into which the impurity element and the predetermined element are implanted with light to anneal the region, the light having an emission intensity distribution, a maximum point of the distribution existing in a wavelength region of not more than 600 nm.

Abstract: Silicon carbide semiconductor devices and methods of fabricating silicon carbide semiconductor devices are provided by successively etching a mask layer to provide windows for formation of a source region or a first conductivity type, a buried silicon carbide region of a second conductivity type opposite to the first conductivity type and a second conductivity type well region in a first conductivity type silicon carbide layer. The source region and the buried silicon carbide region are formed utilizing a first window of the mask layer. Then, the well region is formed utilizing a second window of the mask layer, the second window being provided by a subsequent etch of the mask layer having the first window.

Abstract: Disclosed herein are various methods of determining characteristics of doped regions on device wafers, and a system for accomplishing same. In one illustrative embodiment, the method includes providing a device substrate comprising a plurality of masked areas, a plurality of unmasked areas, and at least one doped region formed in the substrate, determining a ratio between the unmasked areas and the masked areas for the device substrate, illuminating an area of the device substrate comprising the masked areas, the unmasked areas, and at least one doped region, and measuring an induced surface photovoltage of the device substrate while accounting for the ratio of the unmasked areas and the masked areas of the device substrate.

Abstract: A method for forming a plurality of MOSFETs wherein each one of the MOSFET has a unique predetermined threshold voltage. A doped well or tub is formed for each MOSFET. A patterned mask is then used to form a material line proximate each semiconductor well, wherein the width of the line is dependent upon the desired threshold voltage for the MOSFET. A tilted ion implantation is performed at an acute angle with respect to the substrate surface such that the ion beam passes through the material line. Thicker lines have a lower transmission coefficient for the ion beam and thus the intensity of the ion beam reaching the adjacent semiconductor well is reduced. By appropriate selection of the line width the dopant density in the well, and thus the final MOSFET threshold voltage, is controllable.

Abstract: A semiconductor device and its manufacturing method in which the trade-off relationship between channel resistance and JFET resistance is improved. The same mask is used to form a source region and a base region by ion implantation. In a vertical MOSFET including SiC, a source region and a base region are formed by ion implantation using the same tapered mask to give the base region a tapered shape. The taper angle of the tapered mask is set to 30° to 60° when the material of the tapered mask has the same range as SiC in ion implantation, and to 20° to 45° when the material of the tapered mask is SiO2.

Abstract: The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating film pattern.

Abstract: A method is provided for manufacturing a semiconductor device that can reduce the number of steps in manufacturing a triple-well that includes multiple ion implantation steps and heat treatment steps.

Abstract: The present invention provides a method for forming a contact plug in a semiconductor device capable of preventing an increase of contact resistance caused by a decrease in dopant concentration and suppressing diffusions of dopants implanted into the contact. The dopants are doped in a manner to allow the conductive layer to have different doping distributions with respect to a thickness. Particularly, the dopants are doped until reaching a target deposition thickness by gradually increasing a concentration of the dopants from a first concentration to a second concentration for an interval from an initial deposition of the conductive layer to the target deposition thickness, and the second concentration is consistently maintained throughout for an interval from the target deposition thickness to a complete deposition thickness.

Abstract: A process for fabricating power semiconductor devices involving preparation of a silicon wafer by epitaxial formation of an intrinsic silicon layer on a silicon substrate and high energy implantation to form channel and drift regions in the intrinsic epitaxial silicon.

Abstract: A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.

Abstract: A method of manufacturing a gallium nitride (GaN)-based semiconductor light emitting device includes forming a contact resistance improved layer on a p-type GaN-based semiconductor layer with at least one metal selected from the group of Au, Mg, Mn, Mo, Pd, Pt, Sn, Ti and Zn, heat-treating the p-type GaN-based semiconductor layer so that elements in the contact resistance improved layer diffuse into the p-type GaN-based semiconductor layer and that Ga elements in the p-type GaN-based semiconductor layer dissolve into the contact resistance improved layer, and removing the contact resistance improved layer remaining on the p-type GaN-based semiconductor layer.

Abstract: A process is described whereby a wafer is manufactured, a die from the wafer, and an electronic assembly including the die. A thin diamond layer is formed on a sacrificial wafer, and an integrated circuit is then formed on the thin diamond layer. The sacrificial wafer is then removed to expose the thin diamond layer. The resulting combination wafer is subsequently diced into individual dies. Each die has an exposed diamond layer forming the majority of the die and serving to conduct heat from the integrated circuit to a backside of the die, from where the heat can convect or be conducted away from the die.

Abstract: A method of monitoring and adjusting the position of a wafer with respect to an ion beam including setting the position of a wafer holder so that a wafer to be held therein is positioned at a tilt angle of 45 degrees and a twist angle of 45 degrees with respect to the path of an ion beam; positioning a n-type wafer without screen oxide in the wafer holder; implanting boron species into a region of the wafer at 160 KeV and a dose level of 5.0×1013 atoms/cm2; periodically measuring the sheet resistivity of a implanted wafer and readjusting the wafer tilt angle when the sheet resistivity is greater than 30 ohms/square.

Abstract: Provided is a semiconductor device having a semiconductor resistance element, which is capable of suppressing a variation in characteristics of the semiconductor resistance element due to an acceptor concentration difficult to be controlled, thereby stably improving the yield of a semiconductor integrated circuit using the semiconductor device. The device includes an n-type semiconductor resistance region formed in the surface of a compound semiconductor substrate, and a p-type buried region formed between the n-type semiconductor resistance region and a substrate region 21S of the compound semiconductor substrate. An acceptor of the p-type buried region is set to be higher than an acceptor concentration in the substrate region and lower than a doner concentration in the n-type semiconductor resistance region, whereby the effect of the acceptor concentration in the substrate on the semiconductor resistance region can be avoided.

Abstract: LDMOS transistor devices and fabrication methods are provided, in which additional dopants are provided to region of a substrate near a thick dielectric between the channel and the drain to reduce device resistance without significantly impacting breakdown voltage. The extra dopants are added by implantation prior to formation of the thick dielectric, such as before oxidizing silicon in a LOCOS process or following trench formation and before filling the trench in an STI process.

Abstract: In a silicon-on-insulator (SOI) wafer and a method of manufacturing the same, the SOI wafer includes a first semiconductor wafer including an isolation insulating film formed to define an active region; a well region and a buried layer formed in the active region of the first semiconductor wafer; and a second semiconductor wafer bonded with the first semiconductor wafer, wherein an SOI insulating film, which contacts a lower portion of the isolation insulating film and electrically insulates a lower portion of the active region, is formed.

Abstract: A high-voltage device with improved punch through voltage. A semiconductor silicon substrate has a high-voltage device region on which a gate structure is patterned. A lightly doped region is formed in the substrate and lateral to the gate structure. A spacer is formed on the sidewall of the gate structure. A heavily doped region is formed in the lightly doped region and lateral to the spacer. A lateral distance is kept between the spacer and the heavily doped region.

Abstract: A heterogeneous device comprises a substrate and a plurality of heterogeneous circuit devices defined in the substrate. In embodiments, a plurality of heterogeneous circuit devices are integrated by successively masking and ion implanting the substrate. The heterogeneous device may further comprise at least one microelectromechanical system-based element and/or at least one photodiode. In embodiments, the heterogeneous circuit devices comprise at least one CMOS transistor and at least one DMOS transistor. In embodiments, the substrate comprises a layer of silicon or a layer of p-type silicon. In other embodiments, the substrate comprises a silicon-on-insulator wafer comprising a single-crystal-silicon layer or a single-crystal-P-silicon layer, a substrate and an insulator layer therebetween.

Abstract: Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using an FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The floor of the trench is formed so as to be as smooth and planar as possible, thereby preventing undesirable exposure of the underlying active regions through any unknown or undesired cavity caused by scratches or pits or a deeper than desired sidewall.

Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed on the semiconductor substrate, and a hard mask layer formed on the gate. A first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate equal to half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer and the hard mask layer as masks.

Abstract: A method of fabricating an integrated circuit in and on a semiconductor substrate with deep implantations by applying a scattered ion capturing layer in the resist mask opening to capture any implanted ions scattered in the resist and deflected out of the resist into the mask opening to prevent these ions from reaching the semiconductor substrate and affecting the concentration of ions at the edge of the mask and thus the performance of the integrated circuit.

Abstract: An integrated circuit located between isolation trenches at the surface of a semiconductor chip comprising a first well of a first conductivity type having a first resistivity. This first well has a shallow buried region of higher resistivity than the first resistivity, extending between the isolation trenches and created by a compensating doping process. The circuit further comprises a second well of the opposite conductivity type extending to the surface between the isolation trenches, having a contact region and forming a junction with the shallow buried region of the first well, substantially parallel to the surface. Finally, the circuit has a MOS transistor located in the second well, spaced from the contact region, and having source, gate and drain regions at the surface. This space is predetermined to create a small voltage drop in I/O transistors for conditioning signals and power to a pad, or large voltage drops in ESD circuits for protecting the active circuitry connected to a pad.

Abstract: A trench structure that is substantially filled with high-conductivity material such as refractory metal particularly suitable for fast switching trench MOSFET applications. The trench is first lined by a dielectric material such as silicon dioxide. A layer of polysilicon is then formed on the dielectric material and provides buffering for stress relief. The trench is then filled substantially with refractory metal such as tungsten.

Abstract: Multiple dopant implantations are performed on a FinFET device to thereby distribute the dopant in a substantially uniform manner along a vertical depth of the FinFET in the source/drain junction. Each of the multiple implantations may be performed at different tilt angles.

Abstract: A double diffused field effect transistor and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of the substrate so that the substrate has a nonuniform doping profile. An epitaxial layer of the first conductivity type is formed over the substrate and one or more body regions of a second conductivity type are formed within the epitaxial layer. A plurality of source regions of the first conductivity type are then formed within the body regions. Finally, a gate region is formed, which is adjacent to the body regions.

Abstract: The present invention provides a method for forming a transistor junction in a semiconductor wafer by implanting a dopant material (116) into the semiconductor wafer, implanting a halo material (110) into the semiconductor wafer (102), selecting a fluorine dose and energy to tailor one or more characteristics of the transistor, implanting fluorine into the semiconductor wafer at the selected dose and energy, activating the dopant material using a thermal process and annealing the semiconductor wafer to remove residual fluorine. The one or more characteristics of the transistor may include halo segregation, halo diffusion, the sharpness of the halo profile, dopant activation, dopant profile sharpness, drive current, bottom wall capacitance or near edge capacitance.

Abstract: A method for producing a crystalline layer of SiC having at least a region thereof doped with boron atoms comprises a step a) of ion implantation of boron into a layer (1) of crystalline SiC and a step b) of heating the SiC-layer for annealing it for making the boron implanted therein electrically active. The method further comprises a step c) of implanting carbon atoms in said layer (1) for forming carbon interstitials in excess with respect to carbon vacancies present in the SiC-layer before carrying out step b).

Abstract: A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a region of a surface portion of the semiconductor substrate located below the gate electrode. Source/drain regions each composed of a second-conductivity-type impurity layer are formed in regions of the surface portion of the semiconductor substrate located on both sides of the gate electrode. Second-conductivity-type extension regions are formed between the channel region and respective upper portion of the source/drain regions in contact relation with the source/drain regions. First-conductivity-type pocket regions are formed between the channel region and respective lower portion of the source/drain regions in contact relation with the source/drain regions and in spaced relation to the gate insulating film.

Abstract: Doping of the P type base region in a MOSFET or an IGBT with a combination of boron and one or more of indium, aluminum and gallium, provides a structure having a lower P type doping level in the channel portion of the structure than in the remainder of the structure without requiring counter doping of the channel. The doping level of the emitter region of an MCT is kept high everywhere except in the channel in order to provide a fast turn-off time for the MCT.

Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.

Abstract: A method for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves dual halo implants annealed at different temperatures to improve the threshold voltage roll-off characteristics of MOSFETs of approximately 50 nm or less. The method includes a deep source/drain implant and anneal, followed by an angled deep halo implant and a second anneal at a lower temperature. An amorphization implant is then made, followed by a second angled halo implant, formation of source/drain extensions and a third anneal at a temperature less than the second anneal.

Abstract: The present invention discloses an electro-optical device support on a substrate. The electro-optical device includes a sacrificial layer disposed on the substrate having a chamber-wall region surrounding and defining an optical chamber. The electro-optical device further includes a membrane layer disposed on top of the sacrificial layer having a chamber-removal opening surrounding and defining an electric tunable membrane for transmitting an optical signal therethrough. The electrically tunable membrane disposed on top of the optical chamber surrounded by the chamber wall regions. The chamber-wall region is doped with ion-dopants for maintaining the chamber-wall region for removal-resistance under a chamber-forming process performed through the chamber-removal opening. In a preferred embodiment, the chamber-wall region is a doped silicon dioxide region with carbon or nitrogen. In another preferred embodiment, the chamber-wall region is a nitrogen ion-doped SiNxOy region.

Abstract: A method of fabricating lightly doped drains (LDD) of different resistance values starts by providing a semiconductor wafer, the semiconductor wafer having a first active area and a second active area positioned on the substrate. Secondly, a first gate and a second gate are formed on the first active area and the second active area, respectively. A first ion implantation process is then performed to implant dopants of a first electric type on a surface of portions of the substrate within the second active area, followed by performing a second ion implantation process to implant dopants of a second electric type on a surface of portions of the substrate within the first active area and second active area. Finally, the dopants of each electric type are activated to form a first LDD and a second LDD adjacent to the first gate and the second gate, respectively, the first LDD and the second LDD being of different resistance values.

Abstract: The invention provides a technology for reducing the direct contact resistance and for reducing the junction leak while maintaining the punch through margin. A semiconductor integrated circuit device is provided which comprises: a substrate; a transistor formed on the substrate, which comprises a source, a drain and a gate which controls a current flowing from said source to said drain; and a contact plug being electrically connected to at least one of the source and drain and made of a conductive material including a dopant. The contact plug is formed of at least a first layer and a second layer. The first layer contacts with one of the source and drain and is made of said material including the dopant of a first concentration. The second layer is formed of a layer of said material including the dopant of a second concentration, which is lower than the second concentration.

Abstract: Two different regions of a semiconductor substrate are implanted with dopants/ions. The implantation may occur though a sacrificial oxide layer disposed over the substrate. Following implantation in one or both regions, the substrate may be annealed and the sacrificial oxide layer removed. An oxide layer is then grown over the implanted regions of the substrate. For some embodiments, the substrate may be implanted with arsenic and/or with phosphorus. Further, the anneal may be performed for approximately 30 to 120 minutes at a temperature between approximately 900° C. and 950° C.

Abstract: In a method of manufacturing a solid-state image pickup device having a virtual gate structure, in a process of forming a profile of a sensor portion, when ion implantation to form a p+ type layer at a substrate surface side is carried out while the ion implantation direction is tilted with respect to the substrate surface, the ion implantation is divisively carried out at plural times and from multiple ion implantation directions so that the total dose amount is matched, whereby impurities can be implanted into any area of the sensor portion and thus no impurities-unformed area occurs.

Abstract: In this bypass-function added solar cell, a plurality of island-like p+ regions, which is third regions, are formed at a boundary between a p-type region and an n-type region layer constituting a substrate so that the p+ regions project into the region and the region and are separated away from the surface of the substrate. Therefore, in this solar cell, unlike prior art counterparts, the insulating film for isolating the p+ regions and the n electrodes constituting the np+ diode from one another is no longer necessary, thus allowing a reduction in manufacturing cost. As a result, a bypass-function added solar cell with a bypass-diode function added thereto can be provided with low cost and by simple process.

Abstract: An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high VT net dopant adjacent to the source region and a relatively low VT net dopant in the remainder of the channel region. One way to achieve this arrangement with disposable gate processing is to add disposable sidewalls inside the gate opening (after removing the disposable gate), patterning to selectively remove the source or gate side sidewalls, implant the source and drain regions and remove the remaining sidewall and the proceed. According to a second embodiment, wherein the channel implant can be symmetrical, a relatively low net VT implant is provided in the central region of the channel and a relatively high net VT implant is provided in the channel regions adjacent to the source and drain regions.

Abstract: A method of fabricating the semiconductor device for preventing polysilicon line from being damaged during removal of a photoresist layer. The method begins by forming polysilicon lines on a core device region and an electrostatic discharge protection device region of a substrate. A plurality of offset spacers is formed on sidewalls of the polysilicon lines. After the offset spacers are formed, a photoresist layer is formed over the substrate to cover the core device region, while exposing the electrostatic discharge protection device region. With the photoresist layer serving as a mask, a punch-through ion implantation is performed on the electrostatic discharge protection device region before the photoresist layer is removed. Next, a plurality of lightly doped source/drain regions is formed in the core device region. A spacer is further formed on the edge of the offset spacer, followed by forming source/drain regions in the core device region and the electrostatic discharge protection device.

Abstract: Since there are some cases where a CF film used as an interlayer dielectric film of a semiconductor device has a leak current which is too high to obtain required characteristics, it is required to decrease the leak current of the CF film. Ar gas is used as a plasma producing gas, and a compound gas of C and F, e.g., C4F8 gas, a hydrocarbon gas, e.g., C2H4 gas, and a boron containing gas, e.g., BF3 gas are used as thin film deposition gases. These gases are activated as plasma to deposit a CF film on a semiconductor wafer 10 using active species thereof. By adding the boron containing gas, boron is added to unreacted C and F and unbonded hands thereof which exist in the CF film, so that the number of the unbonded hands decreases. Therefore, it is difficult to form a current flowing path, so that the leak current decreases.

Abstract: A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures. To form photodiodes ions are implanted in two steps overlapping a source/drain region. A deeper implant provides a low charge carrier density region and a shallow implant provides a high charge carrier density region near the surface. A blanket transparent insulating layer is deposited.

Abstract: A method for suppressing silicidation retardation effects caused by high dopant concentrations, in particular high Arsenic concentrations, at the surface of a semiconductor substrate. The method includes implanting a preamorphization substance into the substrate to define the boundary of the source/drain, then implanting the dopant at high energy to establish a dopant concentration peak that is distanced from the surface of the substrate. The dopant is activated by rapid thermal annealing, with the relatively deep dopant concentration peak facilitating subsequent improved formation of silicide on the surface of the substrate.

Abstract: A semiconductor device having at least one layer of a group III-V semiconductor material epitaxially deposited on a group III-V nucleation layer adjacent to a germanium substrate. By introducing electrical contacts on one or more layers of the semiconductor device, various optoelectronic and microelectronic circuits may be formed on the semiconductor device having similar quality to conventional group III-V substrates at a substantial cost savings. Alternatively, an active germanium device layer having electrical contacts may be introduced to a portion of the germanium substrate to form an optoelectronic integrated circuit or a dual optoelectronic and microelectronic device on a germanium substrate depending on whether the electrical contacts are coupled with electrical contacts on the germanium substrate and epitaxial layers, thereby increase the functionality of the semiconductor devices.

Abstract: For fabricating a field effect transistor within an active device area of a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate. A layer of gate electrode material is deposited on the layer of gate dielectric material, and the gate electrode material is a semiconductor material. At least one of an N-type dopant or a P-type dopant or a neutral dopant is implanted into the layer of gate electrode material such that the at least one of an N-type dopant or a P-type dopant or a neutral dopant has a dopant concentration in the layer of gate electrode material. A layer of photo-resist material, a layer of BARC (bottom anti-reflective coating) material, and the layer of gate electrode material are patterned to form a gate structure of the field effect transistor. The gate structure is comprised of the remaining gate electrode material, and the BARC (bottom anti-reflective coating) material remains on the gate structure.

Abstract: The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.

Abstract: Silicon carbide devices and methods of fabricating silicon carbide devices are provided by forming a first p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate. At least one first region of n-type silicon carbide is formed extending through the first p-type silicon carbide epitaxial layer and to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer. At least one second region of n-type silicon carbide is also formed adjacent and spaced apart from the first region of n-type silicon carbide. A gate dielectric is formed over the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide. A gate contact is formed on the gate dielectric. A first contact is also formed so as to contact a portion of the p-type epitaxial layer and the second region of n-type silicon carbide. A second contact is also formed on the substrate.

Abstract: A layer comprising cobalt (Co) is formed on a p+ layer by vapor deposition, and a layer comprising gold (Au) is formed thereon. The two layers are alloyed by a heat treatment to form a light-transmitting electrode. The light-transmitting electrode therefore has reduced contact resistance and improved light transmission properties, and gives a light-emitting pattern which is stable over a long time. Furthermore, since cobalt (Co) is an element having a large work function, satisfactory ohmic properties are obtained.

Abstract: A method of forming a triple well structure. A first photoresist layer is formed on a substrate having a first conductive type. A first ion implantation process is performed to form a first well, which has the first conductive type but a dopant concentration of the first well is higher than a dopant concentration of the substrate. The first photoresist layer is baked. A second ion implantation process is performed through the baked first photoresist layer to form a first doped region under the first well. The first doped region has a second conductive type. After removing the first photoresist layer, a second photoresist layer is formed on the substrate. A third ion implantation process is performed to form a second doped region in the substrate around the first well and to form a second well in the substrate. The second doped region and the second well have the second conductive type. The second doped region and the first doped region together surround the first well.