Including Multiple Implantation Steps Patents (Class 438/519)
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Patent number: 8198659Abstract: A semiconductor device and a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device may include forming a gate electrode over a semiconductor substrate, a second conductive type ion implantation region at opposite sides of a gate electrode, a second conductive type ion implantation region as a first conductive type second ion implantation region by implanting a first conductive type impurity over opposite sides of said gate electrode, and/or forming a first conductive type first ion implantation region that substantially surrounds a first conductive type second ion implantation region. A method of manufacturing a semiconductor device may form an N type MOSFET and/or a P type MOSFET using a single photolithography process for each N+ source/drain photolithography process and/or P+ source/drain photolithography process.Type: GrantFiled: November 18, 2009Date of Patent: June 12, 2012Assignee: Dongbu HiTek Co., Ltd.Inventor: Kyung-Wook Kwon
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Patent number: 8187957Abstract: A field-effect transistor that increases the operation speeds of complementary field-effect transistors. Each of an nMOSFET and a pMODFET has a Ge channel and source and drain regions formed of an NiGe layer. The height of Schottky barriers formed at a junction between a channel region and the source region of the nMOSFET and at a junction between the channel region and the drain region of the nMOSFET is changed by very thin high-concentration segregation layers formed by making As atoms, Sb atoms, S atoms or the like segregate at the time of forming the NiGe layer. As a result, Schottky barrier height suitable for the nMOSFET and the pMODFET can be obtained, this being capable of realizing high-speed CMOSFETS.Type: GrantFiled: November 1, 2010Date of Patent: May 29, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Keiji Ikeda
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Patent number: 8178932Abstract: A semiconductor device includes a first transistor having a threshold voltage (Vth) adjusted to a first Vth by a first dopant having a first peak of concentration at a first depth; and a second transistor having the same channel-type as that of the first transistor and having a Vth adjusted to a second Vth by a second dopant having a second peak of concentration at a second depth equal to the first depth and higher concentration than the first dopant; wherein the first dopant and the second dopant are dopants comprising the same constituent element.Type: GrantFiled: January 26, 2011Date of Patent: May 15, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Yoshihiro Takao
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Patent number: 8163636Abstract: Method of preparing p-type doped ZnO or p-type doped ZnMgO, in which the following successive steps are carried out: a) implantation of O+ oxygen ions in an n-type doped ZnO or an n-type doped ZnMgO; b) first annealing at a temperature less than or equal to 1200° C. under oxygen for a time greater than or equal to 5 minutes; c) implantation of at least one ion of an element chosen among the elements of group I or the elements of group V of the periodic table; d) second annealing. The p-type doped ZnO or ZnMgO obtained by this method may be used in an optoelectronic device such as a light emitting diode.Type: GrantFiled: March 24, 2009Date of Patent: April 24, 2012Assignee: Commissariat a l'Energie AtomiqueInventor: Céline Chevalier
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Patent number: 8097518Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line(30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.Type: GrantFiled: October 6, 2010Date of Patent: January 17, 2012Assignee: Spansion LLCInventor: Masatomi Okanishi
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Patent number: 8012843Abstract: An improved method of performing pocket or halo implants is disclosed. The amount of damage and defects created by the halo implant degrades the performance of the semiconductor device, by increasing leakage current, decreasing the noise margin and increasing the minimum gate voltage. The halo or packet implant is performed at cold temperature, which decreases the damage caused to the crystalline structure and improves the amorphization of the crystal. The use of cold temperature also allows the use of lighter elements for the halo implant, such as boron or phosphorus.Type: GrantFiled: August 5, 2010Date of Patent: September 6, 2011Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Christopher R. Hatem, Benjamin Colombeau, Thirumal Thanigaivelan, Kyu-Ha Shim, Dennis Rodier
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Patent number: 7994040Abstract: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer.Type: GrantFiled: April 13, 2007Date of Patent: August 9, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Min-Hwa Chi, Wen-Chuan Chiang, Mu-Chi Chiang, Chang-Ku Chen
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Patent number: 7972948Abstract: A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity.Type: GrantFiled: September 13, 2010Date of Patent: July 5, 2011Assignee: Spansion LLCInventors: Weidong Qian, Mark T. Ramsbey, Tazrien Kamal
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Publication number: 20110045663Abstract: A field-effect transistor that increases the operation speeds of complementary field-effect transistors. Each of an nMOSFET and a pMODFET has a Ge channel and source and drain regions formed of an NiGe layer. The height of Schottky barriers formed at a junction between a channel region and the source region of the nMOSFET and at a junction between the channel region and the drain region of the nMOSFET is changed by very thin high-concentration segregation layers formed by making As atoms, Sb atoms, S atoms or the like segregate at the time of forming the NiGe layer. As a result, Schottky barrier height suitable for the nMOSFET and the pMODFET can be obtained, this being capable of realizing high-speed CMOSFETS.Type: ApplicationFiled: November 1, 2010Publication date: February 24, 2011Applicant: FUJITSU SEMICONDUCTORInventor: Keiji IKEDA
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Patent number: 7883999Abstract: A method for infusing material below the surface of a substrate is described. The method comprises modifying a surface condition of a surface on a substrate to produce a modified surface layer, and thereafter, infusing material into the modified surface in the substrate by exposing the substrate to a gas cluster ion beam (GCIB) comprising the material.Type: GrantFiled: January 25, 2008Date of Patent: February 8, 2011Assignee: TEL Epion Inc.Inventors: Yan Shao, Thomas G. Tetreault, John J. Hautala
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Publication number: 20100291762Abstract: A method of manufacturing a silicon carbide semiconductor device is provided that includes a step of forming in a surface of a silicon carbide wafer of first conductivity type a first region of second conductivity type having a predetermined space thereinside by ion-implanting aluminum as a first impurity and boron as a second impurity; a step of forming a JTE region in the surface of the silicon carbide wafer from the first region by diffusing the boron ion-implanted in the first region toward its neighboring zones by an activation annealing treatment; a step of forming a first electrode on the surface of the silicon carbide wafer at the space inside the first region and at an inner part of the first region; and a step of forming a second electrode on the opposite surface of the silicon carbide wafer. Thereby, a JTE region can be formed that has a wide range of impurity concentration and a desired breakdown voltage without increasing the number of steps of the manufacturing process.Type: ApplicationFiled: November 30, 2009Publication date: November 18, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Yoichiro TARUI
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Patent number: 7811915Abstract: A method for forming a semiconductor device includes forming a first dielectric layer over a first portion of a substrate, forming a charge storage layer over the first dielectric layer and etching a trench in the charge storage layer and the first dielectric layer, where the trench extends to the substrate. The method also includes implanting n-type impurities into the substrate to form an n-type region having a first depth and a first width and implanting p-type impurities into the substrate after implanting the n-type impurities, the p-type impurities forming a p-type region having a second depth and a second width. The method further includes forming a second dielectric layer over the charge storage layer and forming a control gate over the second dielectric layer.Type: GrantFiled: March 14, 2008Date of Patent: October 12, 2010Assignee: Spansion LLCInventors: Weidong Qian, Mark T. Ramsbey, Tazrien Kamal
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Patent number: 7767583Abstract: Embodiments of this method improve the results of a chemical mechanical polishing (CMP) process. A surface is implanted with a species, such as, for example, Si, Ge, As, B, P, H, He, Ne, Ar, Kr, Xe, and C. The implant of this species will at least affect dishing, erosion, and polishing rates of the CMP process. The species may be selected in one embodiment to either accelerate or decelerate the CMP process. The dose of the species may be varied over the surface in one particular embodiment.Type: GrantFiled: December 10, 2008Date of Patent: August 3, 2010Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Deepak Ramappa, Thirumal Thanigaivelan
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Patent number: 7759260Abstract: A method of fabricating a semiconductor structure. The method includes forming a first feature of a first active device and a second feature of a second active device, introducing a first amount of nitrogen into the first feature of the first active device, and introducing a second amount of nitrogen into the second feature of the second active device, the second amount of nitrogen being different from the first amount of nitrogen.Type: GrantFiled: August 16, 2006Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Jay S Burnham, John J Ellis-Monaghan, James S Nakos, James J Quinlivan
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Patent number: 7759148Abstract: A method for manufacturing a semiconductor optical device includes forming a BDR (Band Discontinuity Reduction) layer of a first conductivity type doped with an impurity, depositing a contact layer of the first conductivity type in contact with the BDR layer after forming the the BDR layer, the contact layer being doped with the same impurity as the BDR layer and used to form an electrode, and heat treating after forming the contact layer.Type: GrantFiled: August 13, 2007Date of Patent: July 20, 2010Assignee: Mitsubishi Electric CorporationInventors: Yoshihiko Hanamaki, Kenichi Ono
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Patent number: 7749798Abstract: An image sensing circuit and method is disclosed, wherein a photodiode is formed in a substrate through a series of angled implants. The photodiode is formed by a first, second and third implant, wherein at least one of the implants are angled so as to allow the resulting photodiode to extend out beneath an adjoining gate. Under an alternate embodiment, a fourth implant is added, under an increased implant angle, in the region of the second implant. The resulting photodiode structure substantially reduces or eliminates transfer gate subthreshold leakage.Type: GrantFiled: March 31, 2005Date of Patent: July 6, 2010Assignee: Aptina Imaging CorporationInventors: Howard E. Rhodes, Richard A. Mauritzson, Inna Patrick
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Patent number: 7745276Abstract: A method for manufacturing a SiC semiconductor device includes: preparing a SiC substrate having a (11-20)-orientation surface; forming a drift layer on the substrate; forming a base region in the drift layer; forming a first conductivity type region in the base region; forming a channel region on the base region to couple between the drift layer and the first conductivity type region; forming a gate insulating film on the channel region; forming a gate electrode on the gate insulating film; forming a first electrode to electrically connect to the first conductivity type region; and forming a second electrode on a backside of the substrate. The device controls current between the first and second electrodes by controlling the channel region. The forming the base region includes epitaxially forming a lower part of the base region on the drift layer.Type: GrantFiled: February 5, 2008Date of Patent: June 29, 2010Assignee: Denso CorporationInventors: Eiichi Okuno, Hiroki Nakamura, Naohiro Suzuki
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Patent number: 7700450Abstract: A method for forming a MOS transistor includes providing a substrate having at least a gate structure formed thereon, performing a pre-amorphization (PAI) process to form amorphized regions in the substrate, sequentially performing a co-implantation process, a first ion implantation process, and a first rapid thermal annealing (RTA) process to form lightly doped drains (LDDs), forming spacers on sidewalls of the gate structure, and forming a source/drain.Type: GrantFiled: October 25, 2006Date of Patent: April 20, 2010Assignee: United Microelectronics Corp.Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Shyh-Fann Ting, Wen-Han Hung, Li-Shian Jeng, Tzyy-Ming Cheng
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Patent number: 7696073Abstract: The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first dopant and a second dopant are co-doped into the ZnTe system compound semiconductor single crystal so that the number of atoms of the second dopant becomes smaller than the number of atoms of the first dopant, the first dopant being for controlling a conductivity type of the ZnTe system compound semiconductor to a first conductivity type, and the second dopant being for controlling the conductivity type to a second conductivity type different from the first conductivity type. By the present invention, a desired carrier concentration can be achieved with a doping amount smaller than in earlier technology, and crystallinity of the obtained crystal can be improved.Type: GrantFiled: November 26, 2007Date of Patent: April 13, 2010Assignee: Nippon Mining & Metals Co., Ltd.Inventors: Tetsuya Yamamoto, Atsutoshi Arakawa, Kenji Sato, Toshiaki Asahi
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Patent number: 7682955Abstract: The invention provides a method for forming a deep well region of a power device, including: providing a substrate with a first sacrificial layer thereon; forming a first patterned mask layer on the first sacrificial layer exposing a first open region; performing a first doping process to the first open region to form a first sub-doped region; removing the first patterned mask layer and the first sacrificial layer; forming an epitaxial layer on the substrate; forming a second sacrificial layer on the epitaxial layer; forming a second patterned mask layer on the second sacrificial layer exposing a second open region; performing a second doping process to the second open region to form a second sub-doped region; removing the second patterned mask layer; performing an annealing process to make the first and the second sub-doped regions form a deep well region; and removing the second sacrificial layer.Type: GrantFiled: November 25, 2008Date of Patent: March 23, 2010Assignee: Vanguard International Semiconductor CorporationInventors: Shanghui L. Tu, Hung-Shern Tsai, Jui-Chun Chang
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Patent number: 7671425Abstract: In a semiconductor device, pining regions 105 are disposed along the junction portion of a drain region 102 and a channel forming region 106 locally in a channel width direction. With this structure, because the spread of a depletion layer from a drain side is restrained by the pining regions 105, a short-channel effect can be restrained effectively. Also, because a passage through which carriers move is ensured, high mobility can be maintained.Type: GrantFiled: September 23, 2003Date of Patent: March 2, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akiharu Miyanaga, Nobuo Kubo
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Publication number: 20100048004Abstract: A production method for a semiconductor device includes the steps of: (a) providing a semiconductor substrate having a semiconductor layer 2 of a first conductivity type formed on a surface thereof; (b) forming a first mask 30 so as to cover a predetermined region of the semiconductor layer 2; (c) forming a well region 6 of a second conductivity type by implanting impurity ions of the second conductivity type into the semiconductor layer 2 having the first mask 30 formed thereon; (d) reducing the thickness t1 of the first mask 30 by removing a portion of the first mask 30; (e) forming a second mask 34 covering a portion of the well region 6 by using photolithography; and (f) forming a source region 8 of the first conductivity type by implanting impurity ions of the first conductivity type into the semiconductor layer 2 having the first mask 30? with the reduced thickness and the second mask 34 formed thereon.Type: ApplicationFiled: August 31, 2007Publication date: February 25, 2010Inventors: Koichi Hashimoto, Shin Hashimoto, Kyoko Egashira
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Patent number: 7655526Abstract: Disclosed is a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the steps of forming a gate electrode on a semiconductor substrate, forming a drift area in the semiconductor substrate by implanting a dopant using the gate electrode as a mask, forming a sidewall spacer at sides of the gate electrode, and forming a source/drain area in the semiconductor substrate by implanting a dopant using the gate electrode and the sidewall spacer as a mask.Type: GrantFiled: December 12, 2006Date of Patent: February 2, 2010Assignee: Dongbu Electronics Co., Ltd.Inventor: Choul Joo Ko
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Publication number: 20090246948Abstract: Method of preparing p-type doped ZnO or p-type doped ZnMgO, in which the following successive steps are carried out: a) implantation of O+ oxygen ions in an n-type doped ZnO or an n-type doped ZnMgO; b) first annealing at a temperature less than or equal to 1200° C. under oxygen for a time greater than or equal to 5 minutes; c) implantation of at least one ion of an element chosen among the elements of group I or the elements of group V of the periodic table; d) second annealing. The p-type doped ZnO or ZnMgO obtained by this method may be used in an optoelectronic device such as a light emitting diode.Type: ApplicationFiled: March 24, 2009Publication date: October 1, 2009Inventor: Celine Chevalier
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Patent number: 7585739Abstract: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.Type: GrantFiled: November 21, 2007Date of Patent: September 8, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Takashi Saiki, Hiroyuki Ohta, Hiroyuki Kanata
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Patent number: 7572716Abstract: A method is disclosed for doping a target area of a semiconductor substrate, such as a source or drain region of a transistor, with an electronically active dopant (such as an N-type dopant used to create active areas in NMOS devices, or a P-type dopant used to create active areas in PMOS devices) having a well-controlled placement profile and strong activation. The method comprises placing a carbon-containing diffusion suppressant in the target area at approximately 50% of the concentration of the dopant, and activating the dopant by an approximately 1,040 degree Celsius thermal anneal. In many cases, a thermal anneal at such a high temperature induces excessive diffusion of the dopant out of the target area, but this relative concentration of carbon produces a heretofore unexpected reduction in dopant diffusion during such a high-temperature thermal anneal.Type: GrantFiled: April 25, 2007Date of Patent: August 11, 2009Assignee: Texas Instruments IncorporatedInventors: Haowen Bu, Shashank S. Ekbote, Borna Obradovic, Srinivasan Chakravarthi
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Patent number: 7557021Abstract: The present invention provides, in one embodiment, a method for fabricating a microelectronic device. The method comprises implanting a dopant into a gate electrode located on a substrate. The gate electrode has a melting point below a melting point of the substrate. The method also comprises melting the gate electrode to allow the dopant to diffuse throughout the gate electrode. The method further comprises re-solidifying the gate electrode to increase dopant-occupied substitutional sites within the gate electrode.Type: GrantFiled: July 6, 2005Date of Patent: July 7, 2009Assignee: Texas Instruments IncorporatedInventor: Amitabh Jain
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Publication number: 20090117722Abstract: A method for fabricating a semiconductor structure includes forming a carbon masking layer on a semiconductor layer, forming a protective layer on the carbon masking layer. The method further includes forming an opening in the protective layer and the carbon masking layer and processing the semiconductor layer through the opening to form a first processed region in the semiconductor layer. The method further includes enlarging the opening in the carbon masking layer and performing an additional processing step on the semiconductor layer through the enlarged opening to form a second processed region in the semiconductor layer.Type: ApplicationFiled: July 26, 2006Publication date: May 7, 2009Inventors: Jesse Berkley Tucker, Kevin Sean Matocha, Peter Wilson Waldrab, James Howard Schermerhorn, Matthew Morgan Edmonds
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Patent number: 7410860Abstract: Apparatus and Methods for the self-alignment of separated regions in a lateral MOSFET of an integrate circuit. In one embodiment, a method comprising, forming a relatively thin dielectric layer on a surface of a substrate. Forming a first region of relatively thick material having a predetermined lateral length on the surface of the substrate adjacent the relatively thin dielectric layer. Implanting dopants to form a top gate using a first edge of the first region as a mask to define a first edge of the top gate. Implanting dopants to form a drain contact using a second edge of the first region as a mask to define a first edge of the drain contact, wherein the distance between the top gate and drain contact is defined by the lateral length of the first region.Type: GrantFiled: September 29, 2005Date of Patent: August 12, 2008Assignee: Intersil Americas Inc.Inventor: James D. Beasom
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Patent number: 7396717Abstract: A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of C, Chd xHy+, and (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000.Type: GrantFiled: April 3, 2006Date of Patent: July 8, 2008Assignee: United Microelectronics Corp.Inventors: Hsiang-Ying Wang, Chin-Cheng Chien, Tsai-Fu Hsiao, Ming-Yen Chien, Chao-Chun Chen
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Patent number: 7390711Abstract: A MOS transistor including a gate insulation layer and a gate electrode layer on a channel region of a semiconductor substrate. A gate spacer layer is formed on a sidewall of the electrode layer and the insulation layer. The transistor includes a deep extended source/drain region, a first source/drain region that is deeper than the extended source/drain region, and a second source/drain region that is shallower than the extended source/drain region.Type: GrantFiled: December 15, 2005Date of Patent: June 24, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Dong-Il Byun
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Patent number: 7344964Abstract: An image sensor includes: a first impurity region of the first conductive type aligned with one side of the gate structure and extending to a first depth from a surface portion of the semiconductor layer; a first spacer formed on each sidewall of the gate structure; a second impurity region of the first conductive type, aligned with the first spacer and extending to a second depth that is larger than the first depth from the surface portion of the semiconductor layer; a second spacer formed on each sidewall of the first spacer; a third impurity region of the first conductive type aligned with the second spacer and extending to a third depth that is larger than the second depth from the surface portion of the semiconductor layer; and a fourth impurity region of a second conductive type beneath the third impurity region.Type: GrantFiled: July 28, 2005Date of Patent: March 18, 2008Assignee: Magnachip Semiconductor, Ltd.Inventors: Jae-Young Park, Youn-Sub Lim
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Patent number: 7338876Abstract: A method for forming a semiconductor memory device includes the steps of: implanting a dopant in a semiconductor substrate; heat treating the semiconductor substrate in an oxidizing ambient to diffuse the dopant for forming diffused regions in the semiconductor substrate; and forming memory cells each including a MOS transistor having the diffused regions as source/drain regions.Type: GrantFiled: January 24, 2005Date of Patent: March 4, 2008Assignee: Elpida Memory, Inc.Inventors: Kensuke Okonogi, Kiyonori Oyu
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Publication number: 20070269967Abstract: A method for manufacturing a semiconductor device is provided, which is capable of solving a junction leakage problem. According to the manufacturing method of the present invention, arsenic is implanted to reduce the series resistance after formation of a contact hole. A sidewall film is then formed on the side surface defining the contact hole. Silicon is etched by using the sidewall film as a mask to thereby remove the region containing many implantation damages around the projected range position of arsenic while leaving unetched the arsenic region directly below the sidewall film. The removal of the secondary defect region having many implantation damages is effective to prevent occurrence of junction leak current.Type: ApplicationFiled: May 21, 2007Publication date: November 22, 2007Applicant: Elpida Memory, Inc.Inventor: Hiroaki Taketani
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Patent number: 7276431Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.Type: GrantFiled: February 25, 2005Date of Patent: October 2, 2007Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Patent number: 7268065Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.Type: GrantFiled: June 18, 2004Date of Patent: September 11, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
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Patent number: 7253072Abstract: The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405) such that a predominant axes (430) of the substrate (410) is rotated about 30 degrees to about 60 degrees or about 120 degrees to about 150 degrees offset from a radial with respect to the implant platen (405), and further wherein the substrate (410) is not tilted. The method further includes implanting ions into the substrate (410), the rotated position of the predominant axes (430) reducing shadowing.Type: GrantFiled: December 7, 2004Date of Patent: August 7, 2007Assignee: Texas Instruments IncorporatedInventors: James D. Bernstein, Lance S. Robertson, Said Ghneim, Nandu Mahalingam, Benjamin Moser
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Publication number: 20070161218Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing second impurities of a second conductivity type to form a second impurity region, forming a first nickel silicide film on the first impurity region and forming a second nickel silicide film on the second impurity region, removing an oxide film formed on each of the first and second nickel silicide films by using a mixed gas having an NH3 gas and a gas containing a hydrogen element mixed therein, and forming a first conducting film on the first nickel silicide film and forming a second conducting film on the second nickel silicide film, with the oxide film removed.Type: ApplicationFiled: January 4, 2007Publication date: July 12, 2007Applicant: Renesas Technology Corp.Inventors: Kazuhito Ichinose, Akie Yutani
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Patent number: 7235469Abstract: A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is higher near an interface to the insulator and lower in a surface side opposite to the insulator, and a second gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is substantially uniform and an n-type dopant of a concentration of above 6×1020 atoms/cm3 is contained.Type: GrantFiled: November 29, 2004Date of Patent: June 26, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Yasunori Okayama, Kiyotaka Miyano, Kazunari Ishimaru
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Patent number: 7235470Abstract: A semiconductor device is provided, which aims to reduce the standby power thereof by reducing the leak between a body and a drain with restraining the effect on a threshold voltage, in order to actualize the highly reliable semiconductor device. When extension regions are formed, an n-type impurity less diffusive than phosphorus (P+), for example, arsenic (As+) is used as an impurity. In addition to ordinary ion implantation with high dose (high concentration) and low acceleration energy, As+ ions are implanted with low dose and high acceleration energy.Type: GrantFiled: March 23, 2004Date of Patent: June 26, 2007Assignee: Fujitsu LimitedInventor: Naoto Horiguchi
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Patent number: 7232744Abstract: The present invention provides a method for implanting a dopant in a substrate and a method for manufacturing a semiconductor device. The method for implanting a dopant, among other steps, including tilting a substrate (310) located on or over an implant platen (305) about an axis in a first direction with respect to an implant source (320) and implanting a portion of an implant dose within the substrate (310) tilted in the first direction. The method further includes tilting the substrate (310) having already been tilted in the first direction about the axis in a second opposite direction, and implanting at least a portion of the implant dose within the substrate (310) tilted in the second opposite direction.Type: GrantFiled: October 1, 2004Date of Patent: June 19, 2007Assignee: Texas Instruments IncorporatedInventors: Said Ghneim, James D. Bernstein, Lance S. Robertson, Jiejie Xu, Jeffrey Loewecke
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Patent number: 7205202Abstract: Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.Type: GrantFiled: April 21, 2005Date of Patent: April 17, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Marius K. Orlowski, Vance H. Adams
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Patent number: 7202133Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.Type: GrantFiled: January 21, 2004Date of Patent: April 10, 2007Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: King Jien Chui, Francis Benistant, Ganesh Shamkar Samudra, Kian Meng Tee, Yisuo Li, Kum Woh Vincent Leong, Kheng Chok Tee
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Patent number: 7176108Abstract: A method of detaching a thin film from a source substrate comprises the steps of implanting ions or gaseous species in the source substrate so as to form therein a buried zone weakened by the presence of defects; and splitting in the weakened zone leading to the detachment of the thin film from the source substrate. Two species are implanted of which one is adapted to form defects and the other is adapted to occupy those defects, the detachment being made at a temperature lower than that for which detachment could be obtained with solely the dose of the first species.Type: GrantFiled: November 6, 2003Date of Patent: February 13, 2007Inventors: Ian Cayrefourcq, Nadia Ben Mohamed, Christelle Lagahe-Blanchard, Nguyet-Phuong Nguyen
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Patent number: 7172933Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.Type: GrantFiled: June 10, 2004Date of Patent: February 6, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chun Huang, Bow-Wen Chan, Baw-Ching Perng, Lawrence Sheu, Hun-Jan Tao, Chih-Hsin Ko, Chun-Chieh Lin
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Patent number: 7138322Abstract: An n-type channel diffused layer and an n-type well diffused layer are formed in the top portion of a semiconductor substrate, and a gate insulating film and a gate electrode are formed on the semiconductor substrate. Using the gate electrode as a mask, boron and arsenic are implanted to form p-type extension implanted layers and n-type pocket impurity implanted layers. Fluorine is then implanted using the gate electrode as a mask to form fluorine implanted layers. The resultant semiconductor substrate is subjected to rapid thermal annealing, forming p-type high-density extension diffused layers and n-type pocket diffused layers. Sidewalls and p-type high-density source/drain diffused layers are then formed.Type: GrantFiled: February 11, 2004Date of Patent: November 21, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Taiji Noda
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Semiconductor device manufacture method capable of supressing gate impurity penetration into channel
Patent number: 7135393Abstract: A gate electrode is formed above an n-type well including an n-type threshold voltage adjustment region, ions of p-type impurity are implanted with a low acceleration energy to form extension regions in the n-type well on both sides of the gate electrode, side wall spacers are formed on the side walls of the gate electrode, ions of p-type impurity are implanted with a small dose causing substantially no abnormal tailing in the gate electrode and with a relatively high acceleration energy to form p-type source/drain regions deeper than the threshold adjustment region, ions of atoms are implanted into the semiconductor substrate to change the upper parts of the gate electrode and the source/drain regions to amorphous state, ions of p-type impurity are implanted with a large dose to form high-concentration parts in the source/drain regions, and the impurities introduced by the ion implantation are activated.Type: GrantFiled: May 2, 2005Date of Patent: November 14, 2006Assignee: Fujitsu LimitedInventor: Yukio Tagawa -
Patent number: 7129141Abstract: A method for manufacturing a DRAM device includes the step of implanting phosphor at a specified dosage and heat treating the implanted phosphor for diffusion thereof to form source/drain regions, and implanting fluorine into the source/drain regions and heat treating the implanted fluorine for diffusion thereof. The resultant DRAM memory cell has a larger data storage capability due to lower junction leakage current caused by vacancy type defects formed in the metallurgical junction between the source/drain regions and the channel region.Type: GrantFiled: December 30, 2004Date of Patent: October 31, 2006Assignee: Elpida Memory, Inc.Inventors: Kiyonori Oyu, Kensuke Okonogi
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Patent number: 7122417Abstract: Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is fabricated by forming gate spacers on both sidewalls of a gate pattern in a semiconductor substrate including first and second regions. Then, a first impurity region is formed in the semiconductor substrate at the first region, and the gate spacer exposed at the first region is removed. A second impurity region is formed in the semiconductor substrate at the first region. A third impurity region is formed at the semiconductor substrate in the second region, and the gate spacer exposed at the second region is removed. A fourth impurity region is formed in the semiconductor substrate at the second region. The first and third impurity regions are formed deeper than the second and fourth impurity regions.Type: GrantFiled: February 10, 2004Date of Patent: October 17, 2006Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-Soo Chang
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Patent number: 7118983Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.Type: GrantFiled: June 30, 2005Date of Patent: October 10, 2006Assignee: Renesas Technology Corp.Inventors: Shinichi Fukada, Naotaka Hashimoto, Masanori Kojima, Hiroshi Momiji, Hiromi Abe, Masayuki Suzuki