Abstract: The present invention disclose a salicide process with a self-preamorphization step to reduce the sheet resistance of the source/drain region. The salicide process, comprising the steps of performing a pre-amorphization step on the surface of the silicon and simultaneously forming a metal layer, further contains the substeps of applying a back bias to the bottom of the substrate, using ion metal plasma to transform the surface of the substrate into amorphous silicon, forming a metal layer on the surface of the substrate and then using a thermal process having two stages to transform the metal into the salicide.

Abstract: An ultra-short channel MOSFET with the self-aligned silicided contact and the extended ultra-shallow source/drain junction is formed. An extremely short gate region can be defined without being limited with the bottleneck of the existed lithography technology. A good quality gate insulator layer forming from the regrowth of an oxynitride film is provided. A self aligned metal silicide process is performed to form the contacts. A disposable spacer structure is used to remove metal residue and thus the possible path for leakage is eliminated. An ultra shallow region is formed employing the metal silicide as a diffusion source. An extented source/drain region is provided.

Abstract: A method for introduction of an impurity dopant into a semiconductor layer of SiC comprises the step of ion implantation of the dopant in the semiconductor layer at a low temperature. The ion implantation is carried out in such a way that a doped and amorphous near-surface layer is formed, and the implantation step is followed by a step of annealing the semiconductor layer at such a high temperature that the dopant diffuses into the non-implanted sub-layer of the semiconductor layer following the near-surface layer.

Abstract: A semiconductor device and process for manufacture thereof is disclosed in which a gate electrode with reduced overlap capacitance is formed by forming a gate electrode on a surface of a semiconductor and doping edge portions of the gate electrode with a first doping which effectively reduces the conductivity of the edge portions of the gate electrode. The conductivity of the gate electrode may be reduced at the edge portions by doping the edge portions with a dopant which inhibits the doping of the gate electrode or with a dopant which has a different conductivity type than the gate electrode dopant.

Abstract: A CMOS SRAM cell in which a patterned SIMOX layer forms a buried oxide beneath the PMOS devices, but not beneath the NMOS devices. Latchup is impossible, and well diffusions are not needed.

Abstract: An impurity diffusion surface layer is formed in a surface of a silicon substrate, and an aluminum electrode is arranged in direct contact with the impurity diffusion layer. The surface layer contains Ge as an impurity serving to change the lattice constant in a concentration of at least 1.times.10.sup.21 cm.sup.-3 under a thermal non-equilibrium state. The lattice constant of the surface layer is set higher than that of silicon containing the same concentration of germanium under a thermal equilibrium state. As a result, it is possible to decrease the Schittky barrier height at the contact between the surface layer and the electrode. The surface layer also contains an electrically active boron as an impurity serving to impart carriers in a concentration higher than the critical concentration of solid solution in silicon under a thermal equilibrium state. The presence of Ge permits the carrier mobility within the surface layer higher than that within silicon.

Abstract: Voltage breakdown resistant monocrystalline silicon carbide semiconductor devices are obtained by forming an amorphous silicon carbide termination region in a monocrystalline silicon carbide substrate, at a face thereof, adjacent and surrounding a silicon carbide device. The amorphous termination region is preferably formed by implanting electrically inactive ions, such as argon, into the substrate face at sufficient energy and dose to amorphize the substrate face. The device contact or contacts act as an implantation mask to provide a self-aligned termination region for the device. The terminated devices may exhibit voltage breakdown resistance which approaches the ideal value for silicon carbide.