Abstract: A semiconductor having an ˜5V operational range, including a drain side enhanced gate-overlapped LDD (GOLD) and a source side halo implant region and well implant. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and a very lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms the gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain. The structure enables the manufacture of a deep submicron (<0.3 ?m) power MOSFET using existing 0.13 ?m process flow without additional masks and processing steps.

Abstract: A non-uniform ion implantation apparatus comprises a wide ion beam generator configured to generate a plurality of wide ion beams to irradiate at least two regions on the entire area of a wafer, and a wafer rotating device configured to rotate the wafer in a predetermined direction while the wide ion beams generated by the wide ion beam generator are irradiated to the wafer. Among the wide ion beams, at least one wide ion beam has a different dose from that of at least one different wide ion beam. Since the wide ion beams are irradiated at different doses to the wafer, a smooth circular border is formed between the regions to which the impurity ions are implanted to different concentrations. Since the position of the wafer is suitably changed for the wide ion beams, it is possible to control disposition of the regions implanted with the impurity ions of different concentrations.

Abstract: A MOS transistor including a gate insulation layer and a gate electrode layer on a channel region of a semiconductor substrate. A gate spacer layer is formed on a sidewall of the electrode layer and the insulation layer. The transistor includes a deep extended source/drain region, a first source/drain region that is deeper than the extended source/drain region, and a second source/drain region that is shallower than the extended source/drain region.

Abstract: A method for doping impurities into a device layer is provided. The method includes providing a carbonized dopant layer over a device layer, wherein the carbonized dopant layer comprises one or more dopant impurities, and heat treating the carbonized dopant layer to thermally diffuse the dopant impurities into the device layer.

Abstract: A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a depth. A non-amorphizing implantation implants dopants of the same conductivity type into the semiconductor body. This ion implantation step implants dopants throughout the defect area. The dopants can then be activated by heating the semiconductor body for less than 10 ms, e.g., using a flash anneal or a laser anneal.

Abstract: A method of forming a channel in a semiconductor device including forming an opening in a masking layer to expose a portion of an underlying semiconductor layer through the opening is provided. The method further includes disposing a screening layer and implanting a first type of ions in the portion of the underlying semiconductor layer through the screening layer and through the opening in the masking layer. A second type of ions are implanted in the portion of the underlying semiconductor layer through the screening layer and through the opening in the masking layer at an oblique ion implantation angle wherein a lateral spread of second type ions is greater than a lateral spread of first type ions. Semiconductor devices fabricated in accordance to above said method is also provided.

Abstract: Provided is a technology of carrying out activation annealing of n type impurity ions implanted for the formation of a field stop layer (n+ type semiconductor region) and activation annealing of p type impurity ions implanted for the formation of a collector region (p+ type semiconductor region) in separate steps to adjust an activation ratio of the n type impurity ions in the field stop layer to 60% or greater and an activation ratio of the p type impurity ions in the collector region to from 1 to 15%. This makes it possible to form an IGBT having a high breakdown voltage and high-speed switching characteristics. Moreover, use of a film stack made of nickel silicide, titanium, nickel and gold films for a collector electrode makes it possible to provide an ohmic contact with the collector region.

Abstract: A heterogeneous device comprises a substrate and a plurality of heterogeneous circuit devices defined in the substrate. In embodiments, a plurality of heterogeneous circuit devices are integrated by successively masking and ion implanting the substrate. The heterogeneous device may further comprise at least one microelectromechanical system-based element and/or at least one photodiode. In embodiments, the heterogeneous circuit devices comprise at least one CMOS transistor and at least one DMOS transistor. In embodiments, the substrate comprises a layer of silicon or a layer of p-type silicon. In other embodiments, the substrate comprises a silicon-on-insulator wafer comprising a single-crystal-silicon layer or a single-crystal-P-silicon layer, a substrate and an insulator layer therebetween.

Abstract: An image sensor is provided incorporating a first conductive type semiconductor substrate including an active area defined by a device isolation layer; a second conductive type first ion implant area formed as multiple regions in the active area; a second conductive type second ion implant area connecting the multiple regions of the second conductive type first ion implant area; and a first conductive type ion implant area formed on the second conductive type second ion implant area. The multiple regions of the second conductive type first ion implant area can be formed deeply in the substrate. The second conductive type second ion implant can be formed in the substrate at an upper region of the first ion implant area, a middle region of the first ion implant area, or a lower region of the first ion implant area.

Abstract: In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.

Abstract: In a method of removing a photoresist pattern, a photoresist pattern may be formed on an object layer. Impurities may be implanted into the object layer by a first ion implantation process employing the first photoresist pattern as a first ion implantation mask. The photoresist pattern hardened by the first ion implantation process may be transformed into a first water-soluble photoresist pattern. The water-soluble photoresist pattern may be removed from the object layer.

Abstract: A method for manufacturing a semiconductor device includes the step of depositing a doped silicon layer doped with a first-conductivity-type dopant and a non-doped silicon layer to form a layered silicon film, implanting a first-conductivity-type dopant into a portion of the layered silicon film disposed in a first region, implanting a second-conductivity-type dopant into a portion of the layered silicon film disposed in a second region, and heat treating the layered silicon film to form a first-conductivity-type silicon film in the first region and a second-conductivity-type silicon film in the second region.

Abstract: The present invention pertains to a high-voltage MOS device. The high-voltage MOS device includes a substrate, a first well, a first field oxide layer enclosing a drain region, a second field oxide enclosing a source region, and a third field oxide layer encompassing the first and second field layers with a device isolation region in between. A channel region is situated between the first and second field oxide layers. A gate oxide layer is provided on the channel region. A gate is stacked on the gate oxide layer. A device isolation diffusion layer is provided in the device isolation region.

Abstract: Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning a resist layer overlying a semiconductor substrate to form resist structures about symmetrically located on opposite sides of active regions of the cell, implanting one or more dopant species using a first implant using the resist structures as an implant mask, rotating the semiconductor substrate relative to the first implant by about 180 degrees, and implanting one or more dopant species into the semiconductor substrate with a second implant using the resist structures as an implant mask. A method of performing a symmetric angle implant is also disclosed to provide reduced cross-diffusion within the cell, comprising patterning equally spaced resist structures on opposite sides of the active regions of the cell to equally shadow laterally opposed first and second angled implants.

Abstract: A semiconductor device having a recess gate is formed by first forming a recess below the upper surface of the substrate. A spacer is formed at each sidewall of the recess. An impurity doping area is formed in a source area. A first LDD area is formed in a drain area. A gate comprising a gate insulating layer and a gate conductive layer is then formed in the recess. A second LDD area is formed on the upper surface of the semiconductor substrate. A gate spacer is formed at each sidewall of the gate. Then a source/drain area having an asymmetrical structure is formed on each side of the gate.

Abstract: A method is provided for producing a solid-state imaging device in which a plurality of pixels are arranged two-dimensionally so as to form a photosensitive region, each of the pixels including a photodiode that photoelectrically converts incident light to store a signal charge and read-out elements for reading out the signal charge from the photodiode, and a vertical driving circuit for driving the plurality of pixels in the photosensitive region in a row direction, a horizontal driving circuit for driving the same in a column direction and an amplify circuit for amplifying an output signal are formed with MOS transistors. The method includes: forming an element isolation region with a STI (Shallow Trench Isolation) structure between the plurality of photodiodes and the plurality of MOS transistors; and forming a gate oxide film of the MOS transistors to have a thickness of 10 nm or less.

Abstract: A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electrode. After impurities are implanted, the mask member is removed. Source and drain regions are formed by implanting impurities into the surface layer of the semiconductor substrate on both sides of the gate electrode. It is possible to reduce variations of cross sectional shape of gate electrodes and set an impurity concentration of the gate electrode independently from an impurity concentration of the source and drain regions.

Abstract: A method for manufacturing a semiconductor device has the steps of: (a) implanting boron (B) ions into a semiconductor substrate; (b) implanting fluorine (F) or nitrogen (N) ions into the semiconductor device; (c) after the steps (a) and (b) are performed, executing first annealing with a heating time of 100 msec or shorter relative to a region of the semiconductor substrate into which ions were implanted; and (d) after the step (c) is performed, executing second annealing with a heating time longer than the heating time of the first annealing, relative to the region of the semiconductor substrate into which ions were implanted. The method for manufacturing a semiconductor device is provided which can dope boron (B) shallowly and at a high concentration.

Abstract: A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface; forming an island on the top surface of the substrate, a top surface of the island parallel to the top surface of the substrate, a sidewall of the island extending between the top surface of the island and the top surface of the substrate; forming a plurality of carbon nanotubes on the sidewall of the island; and performing an ion implantation, the ion implantation penetrating into the island and blocked from penetrating into the substrate in regions of the substrate masked by the island and the carbon nanotubes.

Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.

Abstract: Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.

Abstract: The present invention relates to a method for fabricating a semiconductor device with improved refresh time. The method includes the steps of: forming a plurality of gate lines on a substrate; forming a plurality of cell junctions by ion-implanting a first dopant with use of the gate lines as a mask; forming a buffer layer along a gate line profile; and forming a plurality of plug ion-implantation regions in the cell junctions by ion-implanting a second dopant into the substrate under the presence of the buffer layer to thereby from the plugs thereon.

Abstract: In a semiconductor device, a relatively deep germanium implant and activation thereof precedes deposition of the nickel for nickel silicide formation. The activation of the germanium causes the lattice constant in the region of the implant to be increased over the lattice constant of the background substrate, which is preferably silicon. The effect is that the lattice so altered avoids formation of nickel disilicide. The result is that the nickel silicide spiking is avoided.

Abstract: A semiconductor device (1) has a source (2) a gate (3) and a drain (4), a single deep-pocket ion implant (8) in a source-drain depletion region, and a single shallow-pocket ion implant (9) in the source-drain depletion region.

Abstract: A semiconductor device including at least one of: lightly doped drain regions over a semiconductor substrate; a gate insulating layer over a semiconductor substrate between lightly doped drain regions; and/or a gate formed at an upper side of a gate insulating layer. A lower width of a gate may be less than an interval between lightly doped drain regions. An upper width of a gate may be greater than an interval between lightly doped drain regions.

Abstract: Methods for stabilizing a threshold voltage in an NMOS transistor are disclosed. A disclosed method comprises: forming a gate electrode on an active region in a substrate of a first conductive type; implanting ions of a second conductive type into the active region to form LDD regions; forming spacers on the sidewalls of the gate electrode; implanting ions of the second conductive type into the active region to form second source/drain regions; implanting halo ions into the active region; activating ions in the source/drain regions by conducting a first thermal process; and moving the halo ions toward the surface of the channel under the gate electrode by conducting a second thermal process.

Abstract: A semiconductor device is provided, which aims to reduce the standby power thereof by reducing the leak between a body and a drain with restraining the effect on a threshold voltage, in order to actualize the highly reliable semiconductor device. When extension regions are formed, an n-type impurity less diffusive than phosphorus (P+), for example, arsenic (As+) is used as an impurity. In addition to ordinary ion implantation with high dose (high concentration) and low acceleration energy, As+ ions are implanted with low dose and high acceleration energy.

Abstract: The present invention provides a method for implanting a dopant in a substrate and a method for manufacturing a semiconductor device. The method for implanting a dopant, among other steps, including tilting a substrate (310) located on or over an implant platen (305) about an axis in a first direction with respect to an implant source (320) and implanting a portion of an implant dose within the substrate (310) tilted in the first direction. The method further includes tilting the substrate (310) having already been tilted in the first direction about the axis in a second opposite direction, and implanting at least a portion of the implant dose within the substrate (310) tilted in the second opposite direction.

Abstract: The present invention provides a semiconductor memory device with reduced soft error rate (SER) and a method for fabricating such a device. The semiconductor memory device includes a plurality of implants of impurity ions that provide for a reduced number of minority carriers having less mobility. A fabrication process for the semiconductor memory includes a “non-retrograde” implant of impurity ions that is effective to suppress the mobility and lifetime of minority carriers in the devices, and a “retrograde” implant of impurity ions that is effective to substantially increase the doping concentration at the well bottom to slow down or eliminate additional minority carriers.

Abstract: The process for manufacturing a through insulated interconnection is performed by forming, in a body of semiconductor material, a trench extending from the front (of the body for a thickness portion thereof; filling the trench with dielectric material; thinning the body starting from the rear until the trench, so as to form an insulated region surrounded by dielectric material; and forming a conductive region extending inside said insulated region between the front and the rear of the body and having a higher conductivity than the first body. The conductive region includes a metal region extending in an opening formed inside the insulated region or of a heavily doped semiconductor region, made prior to filling of the trench.

Abstract: A method for manufacturing a semiconductor device by a small number of processes and by a means with high usability of materials to have high-definition and a gate insulating with a high step coverage property is disclosed. According to the present invention, a method for manufacturing a semiconductor device comprises the steps of forming a plurality of first conductive layers over a substrate; forming a first insulating layer to fill the gaps of the plurality of the first conductive layers; forming a second insulating layer over the first insulating layer and the plurality of the first conductive layers; and forming a semiconductor region and a second conductive layer over the second insulating layer.

Abstract: MOS transistors having a low junction capacitance between their halo regions and their source/drain extension regions and methods for manufacturing the same are disclosed. A disclosed MOS transistor includes: a semiconductor substrate of a first conductivity type; a gate insulating layer pattern and a gate on an active region of the substrate; spacers on side walls of the gate; source/drain extension regions of a second conductivity type within the substrate on opposite sides of the gate, the source/drain extension regions having a graded junction structure; halo impurity regions of the first conductivity type within the substrate under opposite edges of the gate adjacent respective ones of the source/drain extension regions; and source/drain regions of the second conductivity type within the substrate on opposite sides of the spacer.

Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.

Abstract: Channel stop sections are formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate.

Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Abstract: A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a depth. A non-amorphizing implantation implants dopants of the same conductivity type into the semiconductor body. This ion implantation step implants dopants throughout the defect area. The dopants can then be activated by heating the semiconductor body for less than 10 ms, e.g., using a flash anneal or a laser anneal.

Abstract: P-type buried regions 104a and 104b are formed in an extended drain region 102 formed in a P-type semiconductor substrate 110. An N-type buried region 113 is formed between the P-type buried regions 104a and 104b. An N-type impurity concentration of the N-type buried region 113 along a G–G? plane is low in the vicinity of boundaries between the N-type buried region 113 and the P-type buried regions 104a and 104b and is increased from the boundaries to an inside of the N-type buried region 113.

Abstract: A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into the source region of the LDMOS transistor. A fixed thermal cycle associated with forming the gate oxide of the conventional CMOS transistor is not substantially affected by the implanting of the P-body into the source region of the LDMOS transistor.

Abstract: A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped region is limited to a predetermined value. When the ratio exceeds the predetermined value, a dummy doped region is added to prevent the device from being damaged during a plasma process.

Abstract: There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.

Abstract: The present invention provides a method for measuring an implantation depth of an impurity injected into a wafer by an ion implantation device, using a measurement device and monitoring whether the measured implantation depth of impurity falls within an allowable range, comprising the steps of using, as a measuring wafer, a wafer having an insulating film and an Si layer formed on the insulating film with a thickness of a 1000 ? unit or less; implanting the impurity in the measuring wafer from above the surface of the Si layer, corresponding to a main surface of the measuring wafer and heat-treating the measuring wafer; and measuring surface resistivity of the main surface of the heat-treated measuring wafer by the measurement device and detecting, as an implantation depth of the impurity from the main surface, a concentration peak depth from the main surface, which corresponds to the surface resistivity and at which a concentration of the impurity implanted in the measuring wafer reaches a peak.

Abstract: A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the cost and complexity associated with the fabrication of a semiconductor circuit that includes a depletion-mode transistor.

Abstract: A gate electrode is formed above an n-type well including an n-type threshold voltage adjustment region, ions of p-type impurity are implanted with a low acceleration energy to form extension regions in the n-type well on both sides of the gate electrode, side wall spacers are formed on the side walls of the gate electrode, ions of p-type impurity are implanted with a small dose causing substantially no abnormal tailing in the gate electrode and with a relatively high acceleration energy to form p-type source/drain regions deeper than the threshold adjustment region, ions of atoms are implanted into the semiconductor substrate to change the upper parts of the gate electrode and the source/drain regions to amorphous state, ions of p-type impurity are implanted with a large dose to form high-concentration parts in the source/drain regions, and the impurities introduced by the ion implantation are activated.

Abstract: A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an outer region. The gate patterns have different lengths in the central region, the intermediate region, and the outer region. Accordingly, the semiconductor wafer may have a substantially uniform threshold voltage throughout the semiconductor wafer.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode.

Abstract: A method inhibits metal silicide encroachment in channel regions in a transistor that uses metal silicide as an electrical contact to its terminals. A metal layer is deposited overlying the transistor. A first anneal that is a low temperature anneal forms metal silicide regions to source, gate and drain terminals of the transistor. The low temperature inhibits lateral encroachment. Unsilicided portions of the metal are removed and followed by an ion implant of an element, such as nitrogen, that diffuses into the metal silicide regions. A second anneal at a higher temperature than the first anneal is completed wherein the implanted nitrogen ions prevent lateral encroachment of metal silicide.

Abstract: A method of manufacturing semiconductor devices includes forming element isolation regions in a semiconductor substrate, a gate insulation film in an element region surrounded by the element isolation regions and an impurity doped metal silicide film on the gate insulation film; irradiating energy beams to heat the silicide film; forming a gate electrode film by patterning the silicide film; and forming source and drain regions by doping an impurity into said element region by using at least the gate electrode film as a mask.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.