Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate.

Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on a silicon substrate and forming a thin-film circuit layer on top of the dies and the silicon substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Abstract: A 16 megabit (224) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

Abstract: A method for installing protective components in integrated circuits constructed from standard cells includes reserving sufficient space in the standard cells for at least one protective component, wiring the standard cells and determining which standard cells require a protective component and inserting at least one protective component into the standard cells. A place marker can mark the space required for a protective component in the integrated circuit layout. The protective component can be a protective diode. Protective component connections can be provided in the standard cells. The standard cells can be gate arrays.

Abstract: A method of attaching semiconductor devices, the contact devices of which have preferably already been applied at wafer level, on a switching device and such a device includes having the electrical contacts remain free of solder by using flexible contact elements, and performing the mechanical attachment by additional attachment elements or compression stops used as attachment elements.

Abstract: Within a damascene method for forming a patterned conductor layer within an aperture defined by a patterned dielectric layer within a microelectronic fabrication, at least one of: (1) the patterned dielectric layer is thermally annealed at a temperature of from about 300 to about 450 degrees centigrade prior to forming within the aperture the patterned conductor layer; and (2) the aperture is etched with a plasma employing an etchant gas composition comprising hydrogen to form a laterally enlarged aperture prior to forming within the laterally enlarged aperture the patterned conductor layer. In accord with the method, the microelectronic fabrication is formed with decreased contact resistance and enhanced structural integrity.

Abstract: Components or solid-state chips having electrical contacts containing copper are laminated to Kapton dielectric film, and through vias are formed down to copper-containing material of the component. A fabrication method is described for making reliable connections to the copper-containing materials. The method includes precoating the copper-containing material with SPIE, together with at least argon plasma cleaning, and possibly fluorine plasma etching, of the vias and copper material exposed at the bottoms of the vias.

Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 &mgr;m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density interlayer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Abstract: The invention includes a method of fabricating a circuit in a manner to place certain structures within a predefined distance of one another. Electrical connections are formed between certain structures of silicon, by annealing a conductive material to cause silicon out-diffusing to form local interconnects. The silicon out-diffusion can be facilitated without a masking step thereby simplifying as well as speeding up the fabrication process. The invention also includes a local interconnect thus formed.

Abstract: A method for making low sheet resistance local metal interconnections and improved transistor performance is described. The method involves patterning a polysilicon layer and a silicon nitride (Si3N4) cap layer over device areas to form FET gate electrodes, and the patterned polysilicon extends over the field oxide regions to form portions of the local interconnections. After forming source/drain areas and sidewall spacers on the FET gate electrodes, a silicon oxide (SiO2) insulating layer is deposited and polished back to the Si3N4 cap. The Si3N4 is then selectively removed over the patterned polysilicon layer, leaving recesses in the SiO2 layer. After etching contact openings in the SiO2 layer to the substrate, a high electrically conducting metal layer, having a barrier layer, is deposited and patterned to complete the local interconnections.

Abstract: A method of production of a semiconductor module comprised of a semiconductor chip, external connection terminal pads for bonding with solder balls or other external connection terminals, wires electrically connecting the same, and a sealing resin layer sealing the semiconductor chip, external connection terminal pds, and wires, where surfaces of the external connection terminal pads are exposed at bottoms of recesses formed in the sealing resin layer, comprising sealing by a resin external connection terminal pads and soluble metal layers formed at surfaces of the metal substrate by electroplating to form a sealing resin layer at that one surface, then etching away the metal substrate and soluble metal layers to thereby form in the resin sealing layer recesses exposing the external connection terminal pads at their bottoms by a single etching process without requiring special etching stop control.

Abstract: The invention includes a method of fabricating a circuit in a manner to place certain structures within a predefined distance of one another. Electrical connections are formed between certain structures of silicon, by annealing a conductive material to cause silicon out-diffusing to form local interconnects. The silicon out-diffusion can be facilitated without a masking step thereby simplifying as well as speeding up the fabrication process. The invention also includes a local interconnect thus formed.

Abstract: A semiconductor device is designed by disposing a plurality of cells. The semiconductor device is equipped with a semiconductor substrate 1, transistors formed in the semiconductor substrate, a first wiring pattern 100 and a second wiring pattern 200 formed respectively in a first cell and a second cell disposed adjacent to each other in a X direction in a wiring layer disposed over the semiconductor substrate in layer, the first wiring pattern 100 and the second wiring pattern 200 having portions extending in parallel with each other in a Y direction perpendicular to the X direction, and an interlayer dielectric layer formed as a lower layer of the wiring layer, the interlayer dielectric layer having openings formed at locations corresponding to a position 11 or 12 of the first wiring pattern and a position 22 or 21 of the second wiring pattern, respectively.

Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

Abstract: Configurable electronic circuits comprise arrays of cross-points of one layer of metal/semiconductive nanoscale lines crossed by a second layer of metal/semiconductive nanoscale lines, with a configurable layer between the lines. Methods are provided for altering the thickness and/or resistance of the configurable layer by oxidation or reduction methods, employing a solid material as the configurable layer. Specifically a method is provided for configuring nanoscale devices in a crossbar array of configurable devices comprising arrays of cross-points of a first layer of nanoscale lines comprising a first metal or a first semiconductor material crossed by a second layer of nanoscale lines comprising a second metal or a second semiconductor material.

Abstract: There is disclosed a semiconductor device comprising a copper interconnect layer 7 where a copper film is buried in a concave in an insulating film 3 via a barrier metal film, wherein the copper interconnect layer 7 has a line/space ratio of 4.5 or less and an interconnect occupancy of 10 to 60%. It can effectively prevent dishing and erosion, as well as increase and dispersion in an interconnect resistance when forming damascene copper interconnects.

Abstract: Electrical connection between two faces of a substrate and manufacturing process.

Abstract: A 2-input NOR gate with NMOS transistors and PMOS transistors formed on different semiconductor layers, and a fabricating method for the same, are disclosed. The NMOS and PMOS transistors of the CMOS transistors are formed on different semiconductor layers unlike in the conventional technique, thereby improving the chip density. Further, the device isolating film forming process can be eliminated, and therefore, the fabrication process can be simplified, while the problems such as punch-through, latch-up and the like can be solved.

Abstract: Disclosed is a process of electrically coupling the gate electrodes of an N-type transistor and a P-type transistor without causing substantial cross diffusion of P-type dopants into the N-type gate electrode and N-type dopants into the P-type gate electrode. This is possible because some or all annealing and diffusion steps are performed while the N-type and P-type gate electrodes are physically isolated from one another. Also disclosed is a Silicide as Diffusion Source process in which dopant atoms implanted in silicide regions diffuses out of the silicide regions and into the substrate to form source and drain diffusions. During this diffusion step adjacent N-type and P-type gate electrodes remain unconnected to prevent cross diffusion. Then, these two electrodes are electrically connected by a local interconnect. The local interconnection is a conductive path formed at about the level of the polysilicon (i.e.

Abstract: A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.

Abstract: A camouflaged interconnection for interconnecting two spaced-apart regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first region forming a conducting channel between the two spaced-apart regions, the conducting channel being of the same common conductivity type and bridging a region between the two spaced-apart regions, and a second region of opposite conductivity to type, the second region being disposed between the two spaced-apart regions of common conductivity type and over lying the conducting channel to camouflage the conducting channel from reverse engineering.

Abstract: An integrated circuit is formed by a method having the steps of providing a circuit substrate with a first metallized region, providing a first insulation layer covered by a silicon layer, patterning the first insulation layer and silicon layer to form a first insulation region and first silicon region, then forming a second metallized layer on the silicon region, heating the material so that the second metal layer diffuses into the silicon layer to form a metal silicide region, which is subsequently covered by a second insulating layer having a contact with an interconnect to enable contacting an antifuse formed by the metal silicide region.

Abstract: An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material is disposed over the plated electrode and subjected to a conversion process so that ions from the plated material diffuse into the chalcogenide material.

Abstract: A method for concentric metal density power distribution is disclosed that reduces metal density and increases available area for routing clock and signal traces. A method of concentric metal density power distribution includes the steps of partitioning an area of standard cells in an integrated circuit chip into a plurality of power regions, forming a power boundary around each of the plurality of power regions, and forming a plurality of concentric straps in a metal layer of the integrated circuit chip wherein each of the plurality of concentric straps has a strap width that varies from a maximum strap width at a periphery of each of the plurality of power regions to a minimum strap width toward a center of each of the plurality of power regions.

Abstract: A method for making a novel structure having borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections on integrated circuits is achieved. An etch-stop layer and a planar insulating layer are formed over the devices on a substrate. Contact openings are etched in the insulating layer to the etch-stop layer and the etch-stop layer is removed over the N− contact areas. An N+ doped polysilicon layer is deposited, and second contact openings are etched in the polysilicon and insulating layers over N+ and P+ contacts on the substrate to the etch-stop layer. The etch-stop layer is selectively removed and a conducting barrier layer and a metal layer are deposited having a second etch-stop layer on the surface. The layers are patterned to form interconnecting lines and concurrently to form polysilicon landing plugs to the N− contacts, while forming metal landing plugs to the N+ and P+ contacts.

Abstract: Forming low contract resistance metal contacts on GaN films by treating a GaN surface using a chlorine gas Inductively Coupled Plasma (ICP) etch process before the metal contacts are formed. Beneficially, the GaN is n-type and doped with Si, while the metal contacts include alternating layers of Ti and Al. Additionally, the GaN film is dipped in a solution of HCl:H2O prior to metal contact formation.

Abstract: This invention increases the overlapped area between the diffusion area and the borderless contact by using optical proximity correction (OPC) method. The method includes performing an optical proximity correction on an outer corner of an active area mask to enlarge a portion of an outer corner of an active area on a substrate in a photolithography process, wherein the outer corner of the active area is used to make contact with a borderless contact. The enlarged portion of the outer corner of the active area increases the overlapped area between the borderless contact and the active area, and reduces borderless contact leakage.

Abstract: Embodiment of the present invention are directed to improving the reclamation rate of the waste water of wet benches in semiconductor fabrication. The invention does so by ascertaining the best reclamation switch time before a given rinse recipe runs. In accordance with an aspect of the invention, a method for improvement of water reclamation rate comprises choosing a rinse recipe for a wet bench. The wet bench is activated, and waste water quality of waste water produced for the rinse recipe from the wet bench is detected to generate water quality data for a plurality of reclamation switch time levels. The waste water is directed to a water reclamation system during a reclamation time period after each of the plurality of reclamation switch time levels. The water quality data of the waste water is analyzed for the plurality of reclamation switch time levels.

Abstract: A method and apparatus for clocking an integrated circuit. The apparatus includes an integrated circuit having a clock driver disposed in a first side of a semiconductor substrate, and a clock distribution network coupled to the clock driver and disposed in a second side of the semiconductor substrate to send a clock signal to clock an area of the integrated circuit.

Abstract: A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. A stud is provided on the front surface of the chip, and a layer with interconnection wiring is formed on a transparent plate. The wiring layer includes a conducting pad on a surface thereof opposite the plate. A second layer is formed on top of the wiring layer, with a via formed therein to expose the conducting pad. The stud and via are then aligned and connected; the front surface of the chip thus contacts the second layer and the stud makes electrical contact with the conducting pad. A chip support is then attached to the device. An interface between the wiring layer and the plate is exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density.

Abstract: A multichip semiconductor package, and method of making is provided that has a plurality of semiconductor chips fabricated in electrical isolation one from another integrally on a singular coextensive substrate useful for numerous and varied semiconductor chip applications. The semiconductor chips, instead of being singulated into a plurality of single-chip packages, are kept as integrally formed together and are thereafter electrically connected together so as to form a larger circuit. Encapsulated follows so as to form a single, multichip package. Common signals of the plurality of semiconductor chips are bussed together in electrical common across the substrate to a common electrode suitable for electrically providing the signal to another, external circuit, such as a PWB. The common bussing is achieved by conductive leads disposed across the substrate in pair sets having an extended portion that accommodates the common electrode in contact therewith.

Abstract: A method and apparatus for connecting wiring patterns of an integrated circuit device. A wiring pattern of a semiconductor integrated circuit includes a first line for conducting a first potential and a second line for conducting a second potential. The method detects a portion of a distal end of the first line that overlaps a distal end of the second line and generates an avoidance pattern by eliminating the overlapping portion from the first line.

Abstract: A method of forming a side access layer on a semiconductor chip, or especially a stack of semiconductor chips, is provided. A region of protective insulating material and one or more conductive pads are formed above a major surface of each chip substrate. Each conductive pad is located at least a certain height above the major surface of the substrate and at least a certain distance away from a side surface of the chip, with the region of protective material generally extending between each conductive pad and the major surface of the substrate. The insulating material thereby protects each conductive pad during subsequent etching of the side surface of each chip substrate. The edge of each conductive pad is then exposed, preferably by planarizing the side surface of the chip or stack. Also, a side interconnect layer may be formed on the side surface of the chip or stack to provide an electrical connection to each conductive pad.

Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections.

Abstract: The shape of chrome patterns on an optical pattern transfer tool are adjusted to get a desired shape on a wafer in the manufacture of semiconductor devices, wherein very small regions on a photoresist are defined and these regions are controlled with a high degree of accuracy. The optical pattern transfer tool has first and second planar surfaces lying in substantially parallel planes and a plurality of opaque regions overlying the first planar surface. First and second steps formed between and the first and second planar surfaces at first and second edges, respectively, define a width of the first planar surface. Each of the opaque regions are spaced from one another and offset from one another such that they are alternately aligned along a length of the first planar surface, such that one of the opaque regions is aligned with a portion of the first edge and the next one of the opaque regions along the length is aligned with a portion of the second edge.

Abstract: A function cell capable of shortening the term necessary for circuit designing, a semiconductor device including the function cell, and a semiconductor circuit designing method using the function cell are obtained. The semiconductor device includes first and second function cells that realize the same logic circuit function and have different electrical characteristics from each other. The first function cell includes a first externally connected interconnection. The second function cell includes a second externally connected interconnection. The external shape of the first function cell is almost the same as the external shape of the second function cell. The position of the first externally connected interconnection on the first function cell plane is almost the same as the position of the plane.

Abstract: A method of forming a dummy metal pattern for manufacturing an interconnect pattern. The invention forms a dummy metal pattern on a wafer having a fixed layout while fabricating an interconnect so as to make uniform the metal line pattern on the wafer. Thus, a loading effect can be avoided to benefit a subsequent process, device reliability can be enhanced, and yield can also be increased.

Abstract: A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.

Abstract: A method of forming a local interconnect is provided. A semiconductor is provided. An isolation structure, a transistor and a conductive layer are formed on the substrate. A dielectric layer with an opening is formed over the substrate. A part of the dielectric layer is removed by a photolithography and etching process to form a via opening to expose a part of the gate of the transistor or a part of the conductive layer. A conformal barrier layer is formed in the via opening and overflows the dielectric layer. A conductive plug is formed in the via opening. The barrier layer is patterned to form a local interconnect.

Abstract: Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration.

Abstract: A process of contacting sides of a plurality of chips having semiconductor elements formed in a substrate surface, directly to each other on the same {111} crystal plane.

Abstract: There is provided a semiconductor integrated circuit device having a macro cell structure including: a rectangular macro cell region formed on a semiconductor substrate; a first diffusion region having the minimum permissible width, formed apart at least by a minimum inter-diffusion distance from both left and right side ends in upper and lower sides of the macro cell region, and formed in the vicinity of both upper and lower ends of the macro cell region; and a second diffusion region in which a well contact is formed. The first diffusion region is electrically connected with the second diffusion region.

Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected,, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it.

Abstract: A multi-layer electronic device package includes first and second outer layers and at least one signal layer disposed between the outer layers. The signal layer includes signal traces and ground traces interleaved with the signal traces. A method of routing signal traces in an electronic device package includes the acts of disposing a plurality of signal traces in at least one substrate layer, and interleaving a plurality of ground traces with the signal traces.

Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate.

Abstract: A plug is formed of polysilicon, or other oxidizable conductor. Chemical-mechanical polishing is performed, with a polish stop layer defining the top of the dielectric layer. The upper portion of the polysilicon is oxidized to a controlled depth, then the oxidized portion is removed by an etch, followed by removal of the polish stop layer. The plug thus formed protrudes a controllable distance above the surrounding dielectric, providing good contact to subsequent conductive layers.

Abstract: A method of fabricating a semiconductor device on a semiconductor wafer of the type having a plurality of active layers that includes the steps forming a layout for at least one of the active layers where the layout contains a plurality of active region segments and a plurality of inactive regions. The layout is then modified by adding a plurality of dummy active segments in the inactive regions. The layout is further modified by removing a plurality of sub-regions from the active regions to form a plurality of sub-inactive regions. The semiconductor wafer is then processed using the modified layout to provide an environment during the processing of the active layer wherein the relative area of the active to the inactive regions is substantially equal across the wafer.

Abstract: In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.

Abstract: A method of routing power supply voltage electrodes and reference voltage electrodes which makes efficient use of chip area, maximizes decoupling capacitance, and reduces voltage drops due to electrode resistance is described. The two top wiring layers of an integrated circuit chip are used as power distribution layers to distribute the power supply voltage and reference voltage so that the power supply voltage bus electrode and reference voltage bus electrode are in separate wiring layers. The chip is partitioned into a number of sub-blocks with spaces between the sub-blocks. In a first wiring layer the power supply voltage bus electrode is routed so as to surround each of the sub-blocks. In a second wiring layer the reference voltage bus electrode is routed so as to surround each of the sub-blocks.

Abstract: An integrated circuit having a voltage source and a plurality of conductive power bus tiers extending across the integrated circuit. Each of the power bus tiers are electrically coupled in parallel to the voltage source. The integrated circuit includes a filter capacitor having a first plate and a second plate that are separated by a capacitor dielectric. The first plate forms a bus strap coupling to each of the plurality of power bus tiers.