Selectively Interconnecting (e.g., Customization, Wafer Scale Integration, Etc.) Patents (Class 438/598)
  • Patent number: 7749814
    Abstract: A semiconductor device is made by providing a sacrificial substrate, forming a first insulating layer over the sacrificial substrate, forming a first passivation layer over the first insulating layer, forming a second insulating layer over the first passivation layer, forming an integrated passive device over the second insulating layer, forming a wafer support structure over the integrated passive device, removing the sacrificial substrate to expose the first insulating layer after forming the wafer support structure, and forming an interconnect structure over the first insulating layer in electrical contact with the integrated passive device. The integrated passive device includes an inductor, capacitor, or resistor. The sacrificial substrate is removed by mechanical grinding and wet etching. The wafer support structure can be glass, ceramic, silicon, or molding compound.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: July 6, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Kang Chen, Qing Zhang, Jianmin Fang
  • Patent number: 7745239
    Abstract: An integrated circuit having a metal interconnect layer, and also having a conductive line and a boundary defined with a uniform distance from the conductive line that defines a “keep out” distance between the boundary and the conductive line. A set of first fill elements are uniformly arranged along the boundary outside of the “keep out” distance, and a set of second fill elements further from the conductive line than the first fill elements are arranged in a pattern that would be uniform, but for having some fill elements missing from the pattern.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: June 29, 2010
    Assignee: Tela Innovations, Inc.
    Inventors: O. Samuel Nakagawa, Andrew B. Kahng, Pakman Wong, Puneet Gupta
  • Publication number: 20100159688
    Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.
    Type: Application
    Filed: May 15, 2009
    Publication date: June 24, 2010
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Darrell Rinerson, Robin Cheung
  • Patent number: 7732226
    Abstract: Disclosed are methods of manufacturing a flash memory device. The method can include performing a first test on memory banks of chips on a wafer to record an availability of the banks; performing an inking process on each of the chips according to a number of available banks in the chip; performing a sawing process to divide the chips mounted on the wafer; packaging the divided chips according to the number of available banks in the chip; and performing a verification test on the packaged chips.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: June 8, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Yong Wook Shin
  • Patent number: 7727872
    Abstract: A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: June 1, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, William M. Hiatt, David R. Hembree
  • Patent number: 7704868
    Abstract: Methods of fabricating micro-electromechanical system devices from complementary metal oxide semiconductors (CMOS) are provided.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: April 27, 2010
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Huikai Xie, Khai D. T. Ngo
  • Patent number: 7692309
    Abstract: An application-specific integrated circuit (ASIC) is customized using two non-adjacent via layers. An array of logic cells, each including a plurality of logic devices, are arranged in a plurality of non-customized base layers. A first routing grid, which includes a first non-customized metal routing layer, a customized via layer, and a second non-customized metal routing layer, is disposed on top of the plurality of non-customized layers. A second routing grid, which includes a third non-customized metal routing layer, another customized via layer, and a fourth non-customized metal routing layer, is disposed above the first routing grid. A non-customized via layer is disposed above the first routing grid and beneath the second routing grid. The routing grids and the non-customized via layer collectively facilitate routing connections to and from the logic cells.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: April 6, 2010
    Assignee: ViASIC, Inc.
    Inventor: William D. Cox
  • Patent number: 7679198
    Abstract: Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: March 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Jacob Robert Anderson, William Jones
  • Publication number: 20100060559
    Abstract: A display device displays images with a plurality of signal lines and includes spare lines, each being arranged to be connectable to the signal lines so as to be used for recovery of the signal lines from disconnection. Each of the spare lines has constricted sections for cutting. With this arrangement, it is possible to easily and properly recover the signal lines from disconnection.
    Type: Application
    Filed: July 28, 2006
    Publication date: March 11, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Hidetoshi Nakagawa
  • Patent number: 7674712
    Abstract: A method of patterning a substrate by mechanically locating a first masking film over the substrate; removing one or more first opening portions in first locations in the first masking film to form one or more first masking portions in the first masking film. First materials are deposited over the substrate in the first locations to form first patterned areas before mechanically locating a second masking film over the substrate and first masking portions. One or more second opening portions are removed from second locations, different from the first locations, in both the second masking film and the first masking portions to form one or more second masking portions. Second materials are deposited over the substrate in the second locations to form second patterned areas.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: March 9, 2010
    Inventor: Ronald S. Cok
  • Patent number: 7671361
    Abstract: Provided are a semiconductor device including a fuse focus detector, a fabrication method thereof and a laser repair method. In a chip region, fuses may be formed at a first level. A fuse focus detector including first and second conductive layers may be formed in a scribe line region. The first conductive layer may be formed at the first level, while the second conductive layer may be formed at a different level. For a laser repair method, a target region may be divided into sub-regions. In one selected sub-region, the fuse focus detector may be laser scanned in a direction for a reflection light measurement providing information on a thickness of the fuse focus detector. Using the thickness information, a focus offset value of a fuse in the selected sub-region may be calculated. When the focus offset value is within an allowable range, fuse cutting may be performed.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: March 2, 2010
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Kwang-kyu Bang, Yong-won Lee, Kyeong-seon Shin, Hyen-wook Ju, Jeong-kyu Kim
  • Publication number: 20100044858
    Abstract: Product chips and die, methods for fabricating product chips, and methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification for a wafer used to fabricate the die and a product chip location for the die on the wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.
    Type: Application
    Filed: August 19, 2008
    Publication date: February 25, 2010
    Inventors: John M. Cohn, Mark J. Flemming, John C. Malinowski, Karl V. Swanke
  • Patent number: 7666776
    Abstract: The invention includes methods of forming pluralities of electrically conductive structures. The methods can include formation of a gradient-containing material across a substrate and in direct physical contact with conductive surfaces of nodes. The gradient-containing material can consist essentially of tantalum nitride at a lowermost portion in contact with the conductive surfaces, consist essentially of tantalum at an uppermost portion, and have a TaN/Ta gradient extending between the lowermost and uppermost portions. Alternatively, the gradient-containing material can have a Co/W gradient extending therethrough. Conductive structures can be formed over the gradient-containing material. The invention also includes constructions comprising electrically conductive lines over a material having a TaN/Ta gradient, or a W/Co gradient, extending therethrough.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: February 23, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Rita J. Klein, James E. Green
  • Patent number: 7659202
    Abstract: A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive, thinning a surface of the substrate.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: February 9, 2010
    Inventor: John Trezza
  • Patent number: 7657999
    Abstract: In a method of forming an electrical circuit assembly, a substrate is provided including a plurality of first segments that form an electrical circuit. The first segments have surfaces that rise above surfaces of other segments that form the electrical circuit. All of the segments are deposited on the substrate via one or more shadow mask vapor deposition processes in a vacuum. A photoresist caused to cover all of the segments is hardened and then abraded until surfaces of the first segments are exposed, but surfaces of the other segments are not exposed, and a surface of the abraded photoresist is at the same level as the exposed surfaces of the first segments. Second segments can be deposited on the exposed surfaces of the first segments via a shadow mask vapor deposition process in a vacuum to a level above the top surface of the abraded photoresist.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: February 9, 2010
    Assignee: Advantech Global, Ltd
    Inventor: Thomas Peter Brody
  • Patent number: 7655547
    Abstract: A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: February 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Edward C. Cooney, III, Robert M. Geffken, Anthony K. Stamper
  • Patent number: 7648899
    Abstract: Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a source layer of dopant-generating material (e.g., material generating B, Al, Ti, etc.) over an exposed copper line, converting the upper portion of the source layer to a passivated layer (e.g., nitride or oxide) while allowing an unmodified portion of a dopant-generating source layer to remain in contact with copper, and, subsequently, allowing the dopant from the unmodified portion of source layer to controllably diffuse into and/or react with copper, thereby forming a thin protective cap within copper line. The cap may contain a solid solution or an alloy of copper with the dopant.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: January 19, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Ananda Banerji, George Andrew Antonelli, Jennifer O'loughlin, Mandyam Sriram, Bart Van Schravendijk, Seshasayee Varadarajan
  • Publication number: 20100006904
    Abstract: A circuit can include a module having signal pads that are configurable to route signals between the circuit and at least one external device. The module can also have unused pads that are interleaved between the signal pads. A circuit can include a module having signal pads that are configurable to route varying signals between the circuit and at least one external device. The module can also have voltage pads that are configurable to route substantially constant voltages between at least one external device and the circuit. The signal pads can be interleaved between the voltage pads. A module with one or more of these features can achieve ideal performance in both wire bond and flip chip packages with the flexibility of setting a different input/output utilization percentage within the module.
    Type: Application
    Filed: July 13, 2008
    Publication date: January 14, 2010
    Applicant: Altera Corporation
    Inventors: Guu Lin, Yen-Fu Lin, Stephanie T. Tran, Pooyan Khoshkhoo
  • Publication number: 20100006912
    Abstract: A complementary metal-oxide-semiconductor (CMOS) static random-access-memory (SRAM) element comprising a planar metal-insulator-metal (MIM) capacitor is disclosed, and the planar MIM capacitor is electrically connected to the transistors in the CMOS memory element to reduce the effects of charged particle radiation on the CMOS memory element. Methods for immunizing a CMOS SRAM element to the effects of charged particle radiation are also disclosed, along with methods for manufacturing CMOS SRAM including planar MIM capacitors as integrated circuits.
    Type: Application
    Filed: February 10, 2009
    Publication date: January 14, 2010
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Bradley J. Larsen, Todd A. Randazzo, Cheisan Yue
  • Patent number: 7645693
    Abstract: A semiconductor device includes bit lines (14) provided in a semiconductor substrate (10), word lines (16) provided above the bit lines and running in a width direction of the bit lines (14), metal lines (22) provided above the word lines (16) and running in a length direction of the bit lines (14), and bit line contact regions (28) running in the length direction of the word lines (16) and located between word line regions (26) in which a plurality of word lines (16) are disposed. Each of the bit lines (14) is connected with every other metal line (22) in the bit line contact regions (28). It is thus possible to provide a semiconductor device and a fabrication method therefor in which an alignment margin can be ensured between a contact hole (18) and the bit line (14) to enable downsizing of a memory cell.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: January 12, 2010
    Assignee: Spansion LLC
    Inventor: Hiroshi Murai
  • Publication number: 20090321871
    Abstract: A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC.
    Type: Application
    Filed: June 26, 2008
    Publication date: December 31, 2009
    Inventors: Wu-Te Weng, Ji-Shyang Nieh
  • Publication number: 20090311858
    Abstract: A programmable via structure is provided as well as a method of fabricating the same. The inventive programmable via a semiconductor substrate. An oxide layer such as a thermal oxide is located on a surface of the semiconductor substrate. A patterned heating material is located on a surface of the oxide layer. The inventive structure also includes a patterned dielectric material having a least one via filled with a phase change material (PCM). The patterned dielectric material including the PCM filled via is located on a surface of the patterned heating material. A patterned diffusion barrier is located on an exposed surface of said at least one via filled with the phase change material. The inventive structure also includes contact vias that extend through the patterned dielectric material. The contact vias are filled with a conductive material which also extends onto the upper surface of the patterned dielectric material.
    Type: Application
    Filed: August 8, 2009
    Publication date: December 17, 2009
    Applicant: International Business Machines Corporation
    Inventors: Kuan-Neng Chen, Lia Krusin-Elbaum, Chung H. Lam, Albert M. Young
  • Patent number: 7632747
    Abstract: Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plurality of conductive sections on a first substrate in a first pattern. The method continues by forming a plurality of conductive sections on a second substrate in a second pattern. The method further includes constructing a plurality of conductive lines in a common third pattern on both the first substrate and the second substrate. The conductive lines can be formed on the first and second substrates either before or after forming the first pattern of conductive sections on the first substrate and/or forming the second pattern of conductive sections on the second substrate.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: December 15, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Mark S. Johnson
  • Patent number: 7629250
    Abstract: A method for forming at least one conductive element is disclosed. Particularly, a semiconductor substrate, including a plurality of semiconductor dice thereon, may be provided and a dielectric layer may be formed thereover. At least one depression may be laser ablated in the dielectric layer and an electrically conductive material may be deposited thereinto. Also, a method for assembling a semiconductor die having a plurality of bond pads and a dielectric layer formed thereover to a carrier substrate having a plurality of terminal pads is disclosed. At least one depression may be laser ablated into the dielectric layer and a conductive material may be deposited thereinto for electrical communication between the semiconductor die and the carrier substrate. The semiconductor die may be affixed to the carrier substrate and at least one of the dielectric layer and the conductive material may remain substantially solid during affixation therebetween. The methods may be implemented at the wafer level.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: December 8, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Peter A. Benson, Charles M. Watkins
  • Patent number: 7622375
    Abstract: Provided are a method of manufacturing an electrically conductive member having excellent properties and such electrically conductive member. A method of manufacturing an electrically conductive member having an electrically conductive film on a surface of a substrate, comprising the steps of: (i) forming a layer containing a colloid on a porous surface of a substrate having at least the porous surface by applying a colloidal solution and (ii) forming an electrically conductive layer by drying the layer containing the colloid.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: November 24, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroki Kisu, Keiichi Murai, Naotoshi Miyamachi
  • Patent number: 7615439
    Abstract: Forming a metal-insulator diode and carbon memory element in a single damascene process is disclosed. A trench having a bottom and a sidewall is formed in an insulator. A first diode electrode is formed in the trench during a single damascene process. A first insulating region comprising a first insulating material is formed in the trench during the single damascene process. A second insulating region comprising a second insulating material is formed in the trench during the single damascene process. A second diode electrode is formed in the trench during the single damascene process. The first insulating region and the second insulating region reside between the first diode electrode and the second diode electrode to form a metal-insulator-insulator-metal (MIIM) diode. A region of carbon is formed in the trench during the single damascene process. At least a portion of the carbon is electrically in series with the MIIM diode.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: November 10, 2009
    Assignee: SanDisk Corporation
    Inventors: April Dawn Schricker, Deepak C. Sekar, Andy Fu, Mark Clark
  • Patent number: 7611981
    Abstract: A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough from the top surface to the bottom surface and having a solder ball secured at the surface of each via. A plurality of pairs of traces is provided on the top surface, each trace of each pair of traces extending to a different one of the vias and extending to vias on a plurality of rows and columns, each of the traces of each pair being spaced from the other trace by a ball pitch, being maximized for identity in length and being maximized for parallelism and spacing. Each of the traces of a pair is preferably further maximized for identity in cross-sectional geometry. A differential signal pair is preferably applied to at least one of a pair of traces.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: November 3, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: William P. Stearns, Nozar Hassanzadeh
  • Patent number: 7595222
    Abstract: The semiconductor device includes a first semiconductor chip having first electrodes on a fringe region of a main surface thereof, and a second semiconductor chip smaller in area than the first semiconductor chip and having second electrodes on a main surface thereof. The first semiconductor chip and the second semiconductor chip are connected together by bonding a surface of the second semiconductor chip that is opposite to the main surface thereof to a region of the main surface of the first semiconductor chip other than the fringe region. The first electrodes are connected to the second electrodes by wirings formed over the main surface of the first semiconductor chip, a side surface of the second semiconductor chip and the main surface of the second semiconductor chip.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: September 29, 2009
    Assignee: Panasonic Corporation
    Inventors: Nozomi Shimoishizaka, Toshiyuki Fukuda
  • Publication number: 20090239369
    Abstract: Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 24, 2009
    Inventors: Jae-hak Kim, Jing Hui Li, Wu Ping Liu, Johnny Widodo
  • Publication number: 20090230542
    Abstract: A semiconductor device is made by providing a sacrificial substrate, forming a first insulating layer over the sacrificial substrate, forming a first passivation layer over the first insulating layer, forming a second insulating layer over the first passivation layer, forming an integrated passive device over the second insulating layer, forming a wafer support structure over the integrated passive device, removing the sacrificial substrate to expose the first insulating layer after forming the wafer support structure, and forming an interconnect structure over the first insulating layer in electrical contact with the integrated passive device. The integrated passive device includes an inductor, capacitor, or resistor. The sacrificial substrate is removed by mechanical grinding and wet etching. The wafer support structure can be glass, ceramic, silicon, or molding compound.
    Type: Application
    Filed: March 13, 2008
    Publication date: September 17, 2009
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, Kang Chen, Haijing Cao, Qing Zhang, Jianmin Fang
  • Patent number: 7582566
    Abstract: A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: September 1, 2009
    Assignee: LSI Logic Corporation
    Inventors: Derryl D. J. Allman, Hemanshu D. Bhatt, Charles E. May, Peter Austin Burke, Byung-Sung Kwak, Sey-Shing Sun, David T. Price, David Pritchard
  • Publication number: 20090212424
    Abstract: A routing structure of an RDL of a chip is provided. The routing structure comprises a power route, a plurality of first stripes, a ground route, and a plurality of second stripes. The power route is arranged in a first direction and comprises a plurality of first bumps and a plurality of first line segments. Each of the first line segments connects adjacent first bumps. The first stripes are arranged in a second direction and connected to the power route. The ground route is disposed at one side of the power route in a third direction, and comprises a plurality of second bumps and a plurality of second line segments. Each of the second line segments connects adjacent second bumps. The second stripes, are arranged in a forth direction and connected to the ground route. The first stripes and the second stripes are interleaved without intersecting one another.
    Type: Application
    Filed: September 10, 2008
    Publication date: August 27, 2009
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Xiaoshan Chen
  • Patent number: 7575999
    Abstract: A method for forming at least one conductive element is disclosed. Particularly, a semiconductor substrate, including a plurality of semiconductor dice thereon, may be provided and a dielectric layer may be formed thereover. At least one depression may be laser ablated in the dielectric layer and an electrically conductive material may be deposited thereinto. Also, a method for assembling a semiconductor die having a plurality of bond pads and a dielectric layer formed thereover to a carrier substrate having a plurality of terminal pads is disclosed. At least one depression may be laser ablated into the dielectric layer and a conductive material may be deposited thereinto for electrical communication between the semiconductor die and the carrier substrate. The semiconductor die may be affixed to the carrier substrate and at least one of the dielectric layer and the conductive material may remain substantially solid during affixation therebetween. The methods may be implemented at the wafer level.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: August 18, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Peter A. Benson, Charles M. Watkins
  • Patent number: 7560370
    Abstract: A method for forming a semiconductor device includes forming a bit line contact region with a line pattern and then performing a process to form a bit line so that a multi-layered bit line contact is expended, thereby preventing a short between bit line contact plugs and improving the process margin of semiconductor devices and the reliability of semiconductor devices.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: July 14, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seo Min Kim
  • Publication number: 20090166758
    Abstract: A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An electrical strap is formed and in contact with at least a portion of at least one sidewall of the gate stack of a first transistor to provide a continuous electrical flowpath over a gate electrode of the first transistor and the source or drain region of a second transistor.
    Type: Application
    Filed: September 30, 2008
    Publication date: July 2, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Lieyong YANG, Siau Ben CHIAH, Ming LEI, Hua XIAO, Xiongfei YU, Kelvin Tianpeng GUAN, Puay San CHIA, Chor Shu CHENG, Gary CHIA, Chee Kong LEONG, Sean LIAN, Kin San PEY, Chao Yong LI
  • Publication number: 20090142916
    Abstract: On aspect is a method to manufacture an integrated circuit including a reshaping process of the wafer edge region and an apparatus to perform the reshaping process.
    Type: Application
    Filed: November 29, 2007
    Publication date: June 4, 2009
    Applicant: Qimonda AG
    Inventors: Heike Prenz, Peter Thieme, Peter Lahnor
  • Publication number: 20090128188
    Abstract: A three dimensional semiconductor device, comprising: a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device; a plurality of pads having predetermined positions within the device; and a configuration memory circuit coupled to the programmable logic blocks having a plurality of fabricating methods without altering the predetermined positions of the pads and the circuit blocks.
    Type: Application
    Filed: November 19, 2007
    Publication date: May 21, 2009
    Inventor: Raminda Udaya Madurawe
  • Patent number: 7531439
    Abstract: Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained. A protective material region is then formed. A second metallization layer is subsequently applied, which is then also patterned. Afterward, the first metallization layer together with the protective material region is then patterned.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: May 12, 2009
    Assignee: Infineon Technologies AG
    Inventors: Johann Rieger, Stefan Lipp, Hans Peter Zeindl, Thomas Detzel, Hubert Maier
  • Patent number: 7524763
    Abstract: A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: April 28, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soon-Bum Kim, Ung-Kwang Kim, Keum-Hee Ma, Young-Hee Song, Sung-Min Sim, Se-Yong Oh, Kang-Wook Lee, Se-Young Jeong
  • Patent number: 7524753
    Abstract: A method of manufacturing a semiconductor device having a through electrode, includes forming through holes 36 in a substrate 31, forming a first metal layer 39 from one surface side of the substrate and pasting a protection film 40 on one surface of the substrate, forming through electrodes by filling the through holes with a second metal by means of an electroplating of the second metal 42 applied from other surface of the substrate while using the first metal layer as a power feeding layer, removing the protection film 40, and removing the first metal layer 39 located in areas other than peripheral portions of the through electrodes.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: April 28, 2009
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Mitsutoshi Higashi, Akinori Shiraishi, Hideaki Sakaguchi
  • Publication number: 20090104765
    Abstract: A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.
    Type: Application
    Filed: December 17, 2008
    Publication date: April 23, 2009
    Applicant: Matsushita Electric Industrial Co., Ltd. (PANASONIC CORPORATION)
    Inventors: Nobuyoshi TAKAHASHI, Fumihiko Noro, Kenji Sato
  • Patent number: 7521358
    Abstract: Back-End of Line (BEoL) interconnect structures, and methods for their manufacture, are provided. The structures are characterized by narrower conductive lines and reduced overall dielectric constant values. Conformal diffusion barrier layers, and selectively formed capping layers, are used to isolate the conductive lines and vias from surrounding dielectric layers in the interconnect structures. The methods of the invention employ techniques to narrow the openings in photoresist masks in order to define narrower vias. More narrow vias increase the amount of misalignment that can be tolerated between the vias and the conductive lines.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: April 21, 2009
    Assignee: LAM Research Corporation
    Inventors: Nicolas Bright, Dave Hemker, Fritz C. Redeker, Yezdi Dordi
  • Patent number: 7521276
    Abstract: A method of making chip assemblies includes providing an in-process assembly including a semiconductor wafer, a wafer compliant structure overlying a front surface of the wafer and cavities, and terminals carried on the compliant structure adjacent the cavities and electrically connected to the wafer, the cavities being substantially sealed. The method includes subdividing the in-process assembly to form individual chip assemblies, each including one or more chip regions of the wafer, a portion of the compliant structure and the terminals carried on the portion, and opening vents communicating with said cavities after said providing step.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: April 21, 2009
    Assignee: Tessera, Inc.
    Inventors: Michael J. Nystrom, Belgacem Haba, Giles Humpston
  • Patent number: 7517794
    Abstract: One embodiment of the present invention is a method for fabricating a nanoscale shift register. In a described embodiment, a nanoimprinting-resist layer applied above a silicon-on-insulator substrate is nanoimprinted to form troughs and trough segments. The silicon layer exposed at the bottom of the troughs and trough segments is then etched, and a conductive material is deposited into the troughs to form nanowires and into the trough segments to form nanowire segments. The exposed surfaces of nanowires are coated with a protective coating, and the conductive material of the nanowire segments is then removed to produce trough segments etched through the nanoimprinting resist and the silicon layer.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: April 14, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gregory S. Snider, Phillip J. Kuekes
  • Patent number: 7504287
    Abstract: A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is conformally deposited over the contact points, and a second material layer is deposited. A photoresist layer is applied and patterned to leave remaining portions. The remaining portions are trimmed to produce trimmed remaining portions which overlie eventual contact holes to the contact points. Using the trimmed remaining portions as an etch mask, exposed portions the second material layer are etched away to leave sacrificial plugs. The sacrificial plugs are etched away to form contact holes that reach portions the first material layers. Another etching step is performed to extend the contact holes to produce final contact holes that extend to the contact points.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: March 17, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sven Beyer, Kamatchi Subramanian
  • Patent number: 7498206
    Abstract: Irrespective of a specification of the controller, a plurality of TFTs are formed for the controller on a substrate in advance. Then, in accordance with a design of the controller, connection is achieved among sources, drains, and gates, which serve as three terminals in each of the plural TFTs, appropriately through a wiring formed on a layer different from the one where the plural TFTs are formed, so that the controller with a desired specification is formed. At this time, it is not required to use all the TFTs arranged on the substrate and some TFTs may remain unused depending on the specification of the controller.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: March 3, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mai Akiba
  • Patent number: 7494909
    Abstract: Provided are a chip, a chip stack, and a method of manufacturing the same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in a via hole exposing the bottom of the pad are stacked such that the pad and the metal layer of adjacent chips are bonded. This leads to a simplified manufacturing process, high chip performance and a small footprint for a chip stack.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: February 24, 2009
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chull Won Ju, Byoung Gue Min, Seong Il Kim, Jong Min Lee, Kyung Ho Lee, Young Il Kang
  • Patent number: 7491636
    Abstract: A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal in substantially mutually parallel arrangement, providing redundant current paths between the bond pad and a common cap in the form of a contact pad to which they are all joined. The flexibility of the interconnect may be varied by controlling the column dimensions, height, aspect ratio, number of columns, column material and by applying a supporting layer of dielectric material to a controlled depth about the base of the columns. A large number of interconnects may be formed on a wafer, partial wafer, single die, interposer, circuit board, or other substrate.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: February 17, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Warren M. Farnworth
  • Patent number: 7488674
    Abstract: When forming a silicon nitride film to protect and insulate a surface on which a silicon substrate has been ground or polishing, by use of a mixed gas containing SiH4, N2, and NH3 as a reaction gas, a film is formed by a single-frequency parallel-plate plasma CVD method. Thereby, even when the film forming temperature is made not more than an allowable temperature limit of an adhesive to adhere a support (for example, approximately 100° C. or less, which is an allowable temperature limit when the adhesive is an ultraviolet curing resin), a high-quality film without exfoliation in a CMP step of the following step and with less leakage can be formed. This high-quality film is, if being prescribed by a refractive index, a film whose refractive index with respect to a wavelength of 633 nm is approximately 1.8 through 1.9.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: February 10, 2009
    Assignee: Nec Electronics Corporation
    Inventor: Tatsuya Usami
  • Publication number: 20090020856
    Abstract: Semiconductor device structures and methods for shielding a bond pad from electrical noise generated by active circuitry of an integrated circuit carried on a substrate. The structure includes electrically characterized devices placed in a pre-determined arrangement under the bond pad. The pre-determined arrangement of the electrically characterized devices provides for a consistent high frequency environment under the bond pad, which simplifies modeling of the bond pad by a circuit designer.
    Type: Application
    Filed: July 17, 2007
    Publication date: January 22, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David S. Collins, Mete Erturk, Edward J. Gordon, Robert Groves, Robert M. Rassel