Abstract: Semiconductor device structures and methods for shielding a bond pad from electrical noise generated by active circuitry of an integrated circuit carried on a substrate. The structure includes electrically characterized devices placed in a pre-determined arrangement under the bond pad. The pre-determined arrangement of the electrically characterized devices provides for a consistent high frequency environment under the bond pad, which simplifies modeling of the bond pad by a circuit designer.

Abstract: A voltage regulator and a method of manufacturing the voltage regulator, which can provide a desired output voltage of the voltage regulator using a plurality of metal wires, arranged in regular patterns, and conductive metal wiring patterns, configured to activate the metal wires by selectively connecting them to each other when a voltage regulator having various output voltage patterns is produced through a single chip, thus reducing the costs of manufacturing the voltage regulator by simplifying the manufacturing process while reducing the size of the chip of the voltage regulator.

Abstract: A semiconductor device has a substrate having a plurality of neighboring trenches, and a contact area, one mesa stripe each being formed between two neighboring trenches. The contact area contacts mesa stripes and surrounds an opening region in which the contact area is not formed and which is formed such that the contact area contacts the same mesa stripes at two positions between which the opening region is arranged, and the opening region having a region of elongate extension which intersects the mesa stripes in a skewed or perpendicular manner.

Abstract: Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures.

Abstract: A compliant structure is provided on a semiconductor wafer. The compliant structure includes cavities. The compliant structure and the wafer seal the cavities during process steps used to form conductive elements on the compliant structure. After processing, vents are opened to connect the cavities to the exterior of the assembly. The vents may be formed by severing the wafer and compliant structure to form individual units, so that the severance planes intersect channels or other voids communicating with the cavities. Alternatively, the vents may be formed by forming holes in the compliant structure, or by opening bores extending through the wafer.

Abstract: A method is provided for fabricating current-carrying formation on substrates. The method includes providing a substrate including a layer of a voltage switchable dielectric material, forming a mask over the layer of the voltage switchable dielectric material, and forming an electrically conductive layer. The mask includes gaps and the electrically conductive layer is formed in the gaps. The voltage switchable dielectric material has a characteristic voltage and the electrically conductive layer is formed by applying a voltage in excess of the characteristic voltage to the substrate and depositing the electrically conductive material through an electrochemical process such as electroplating.

Abstract: Localized trenches or access holes are milled in a semiconductor substrate to define access points to structures of an integrated circuit intended for circuit editing. A conductor is deposited, such as with a focused ion beam tool, in the access holes and a localized heat is applied to the conductor for silicide formation, especially at the boundary between a semiconductor structure, such as diffusion regions, and the deposited conductor. Localized heat may be generated at the target location through precise laser application, current generation through the target location, or a combination thereof.

Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.

Abstract: Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.

Abstract: The present invention provides a semiconductor element mounting substrate 101 including: a base substrate 1 having a region 2 for mounting a semiconductor element 11, the region 2 being set on the major surface of the base substrate 1; a plurality of wiring patterns 3 formed on the base substrate 1 and connected to the semiconductor element 11; and a dummy pattern 8 formed like a frame in the region 2 for mounting the semiconductor element 11 and not connected to the wiring patterns 3.

Abstract: A ground line is exposed by removing a surface protecting film, which covers an uppermost metal wiring layer, and providing an opening portion at a portion of a top surface of a semiconductor chip, which portion is within a region contacted by a collet in a pick-up process and corresponds to an upper portion of, among plural metal wires provided at the uppermost metal wiring layer, the ground line which has ohmic connection to a semiconductor substrate. When the collet approaches the top surface of the semiconductor chip in the pick-up process, electrostatic discharge is occurred between the collet and the ground line via the opening portion, and neutralizing charges which have flowed into the ground line directly reach the semiconductor substrate. The semiconductor substrate thereby enters a state of electrostatic equilibrium with a mounting film.

Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first insulation layer. A conductive pattern, e.g., a damascene bit line, is disposed in the second insulation layer. A conductive plug extends through the second insulation layer to contact the contact pad and is self-aligned to the conductive pattern. An insulation film may separate the conductive pattern and the conductive plug. A glue layer may be disposed between the conductive pattern and the second insulation layer. The device may further include a third insulation layer on the second insulation layer and the conductive pattern, and the conductive plug may extend through the second and third insulation layers.

Abstract: A method of fabricating a micro-electromechanical system (MEMS) device from a complementary metal oxide semiconductor (CMOS) having a silicon layer and an oxide layer, the oxide layer being on the silicon layer and containing at least one metal layer. The method includes etching the silicon layer of the CMOS to form a trench through the silicon layer to expose a portion of the oxide layer. The method also includes depositing a silicon oxide layer on the silicon layer and on an exposed portion of the oxide layer within the trench. Additionally, the method includes etching the silicon oxide layer deposited on the exposed portion of the oxide layer to expose a portion of the metal within the oxide layer. The method further includes electrodepositing a conductor within the trench such that the conductor extends through the trench to the exposed portion of the metal and etching the silicon layer of the CMOS to remove portions of the silicon layer adjacent the conductor.

Abstract: A method of applying a sculptured copper seed layer on a semiconductor feature surface using ion deposition sputtering. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material.

Abstract: A method for manufacturing a semiconductor device includes forming a second storage node contact hole with a mask for storage node and securing an overlay margin between a storage node contact hole and a storage node with a hard mask layer that serves as a hard mask as well as an anti-reflection film to reduce contact resistance, prevent reduction of a line-width of a lower interlayer insulating film and eliminate processes for depositing the interlayer insulating film and a polysilicon layer and etching the polysilicon layer to reduce a production period and cost of products.

Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.

Abstract: A semiconductor device and fabricating method thereof are disclosed. Embodiments relate to forming metal lines having a prescribed pattern over a lower insulating interlayer, forming a silicon oxide layer over surfaces of the metal lines and a surface of the lower insulating interlayer exposed between the metal lines, and forming an upper insulating interlayer over the silicon oxide layer.

Abstract: A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact. A system for performing the method includes the semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components.

Abstract: After forming a resist film including a hygroscopic compound, pattern exposure is performed by selectively irradiating the resist film with exposing light while supplying water onto the resist film. After the pattern exposure, the resist film is developed so as to form a resist pattern.

Abstract: An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles.

Abstract: A method for producing at least one semiconductor component group, in particular a SiC semiconductor component group, includes the step of producing a number of semiconductor components on a substrate, particularly on a wafer. The individual semiconductor components are tested for detecting operative semiconductor components. At least one semiconductor component group is assembled, which is formed of a number of operative semiconductor components and which forms a coherent flat structure. The operative semiconductor components of the semiconductor component group are electrically connecting in parallel.

Abstract: There is provided a semiconductor chip using an electrical identification code and an optical identification code, both of the codes being formed in the same process to be always in one-to-one correspondence with each other. An optically readable wiring pattern associated with an electrically readable identification code is formed on a top layer of the semiconductor chip or a layer that is optically identifiable from the top layer, and used as an optical identification code. The semiconductor chip is thus provided such that the optically readable wiring pattern is part of wiring of memory elements that electrically store an identification code, and comprised of a combination of wiring forms set as 1 or 0 that is an output of each of the memory elements.

Abstract: An integrated circuit includes an etch stop layer over a substrate; a UV blocker layer on the etch stop layer, wherein the UV blocker layer has a high extinction coefficient; and a low-k dielectric layer on the UV blocker layer.

Abstract: A semiconductor device having copper interconnecting metallization (111) protected by a first (102) and a second (120) overcoat layer (homogeneous silicon dioxide), portions of the metallization exposed in a window (103) opened through the thicknesses of the first and second overcoat layers. A patterned conductive barrier layer (130) is positioned on the exposed portion of the copper metallization and on portions of the second overcoat layer surrounding the window. A bondable metal layer (150) is positioned on the barrier layer; the thickness of this bondable layer is suitable for wire bonding. A third overcoat layer (160) consist of a homogeneous silicon nitride compound is positioned on the second overcoat layer so that the ledge (162, more than 500 nm high) of the third overcoat layer overlays the edge (150b) of the bondable metal layer. The resulting contoured chip surface improves the adhesion to plastic device encapsulation.

Abstract: A standard cell is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In the empty region in the cell column searched for, a spacer cell or a filler cell is placed. At this time, using the spacer cell or filler cell, the well potential of the standard cells in the cell column is fixed.

Abstract: The present invention is a photodiode detector array for use in computerized tomography (CT) and non-CT applications. Specifically, the present invention is a high-density photodiode arrays, with low dark current, low capacitance, high signal to noise ratio, high speed, and low crosstalk that can be fabricated on relatively large substrate wafers. More specifically the photodiode array of the present invention is fabricated such that the PN-junctions are located on both the front side and back side surfaces of the array, and wherein the front side PN-junction is in electrical communication with the back side PN-junction. Still more specifically, the present invention is a photodiode array having PN-junctions that are electrically connected from the front to back surfaces and which can be operated in a fully depleted mode at low reverse bias.

Abstract: The invention includes a method of forming a metal-comprising mass for a semiconductor construction. A semiconductor substrate is provided, and a metallo-organic precursor is provided proximate the substrate. The precursor is exposed to a reducing atmosphere to release metal from the precursor, and subsequently the released metal is deposited over the semiconductor substrate. The invention also includes capacitor constructions, and methods of forming capacitor constructions.

Abstract: A chip and a method of fabricating the chip for low cost chip identification circuitry. In one embodiment, a method of manufacturing an integrated circuit includes formation of a multi-level metallization structure including a pad level comprising programming pads. A plurality of active devices are formed on a substrate, and multiple levels of metallization are formed over the active devices, connecting some of the active devices to form programmable circuitry. The programmable circuitry is connected to pairs of programming pads on the bond pad level. Programming pads in some of the pairs are selectively connected to one another by using conductive ink deposited with maskless inkjet printing techniques. The pads are then covered with a non-conductive protective layer.

Abstract: A method for forming interconnects onto attachment points of a wafer includes the steps of providing a mold with a plurality of cavities having a predetermined shape, depositing a release agent on surfaces of the cavities, filling the cavities with an interconnect material to form the interconnects, removing the release agent from the mold, and attaching the interconnects to the attachment points of the wafer. An adhesive layer can optionally be deposited in addition to the release layer. The adhesive layer can be used, for example, to bond the chip to a package.

Abstract: A semiconductor device and a fabrication method thereof are provided. An inductor device provided with an inductor cell and a second device having a RF device circuit unit are provided next to each other in the same plane and are electrically connected to each other through a connecting electrode.

Abstract: A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the conductive layer into a plurality of wire bond pads spaced apart; and forming a protective dielectric layer on the top surface of the substrate in spaces between adjacent wire bond pads, top surfaces of the dielectric layer in the spaces coplanar with coplanar top surfaces of the wire bond pads.

Abstract: An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles.

Abstract: Methods for forming a redistribution layer on microfeature workpieces, and microfeature workpieces having such a redistribution layer are disclosed herein. In one embodiment, a method includes constructing a dielectric structure on a microfeature workpiece having a substrate and a terminal carried by the substrate, and removing a section of the dielectric structure to form an opening. The opening has a first portion extending through the dielectric structure and exposing the terminal and a second portion extending to an intermediate depth in the dielectric structure. The second portion is spaced laterally apart from the terminal. The method further includes forming a conductive layer on the microfeature workpiece with the conductive layer in electrical contact with the terminal and disposed in the first and second portions of the opening.

Abstract: A process produces metallic interconnects and contact surfaces on electronic components using a copper-nickel-gold layer structure. The copper core of the interconnects and contact surfaces is deposited by electroplating by means of a first resist mask made from positive resist. The copper core of the interconnects and contact surfaces is surrounded by a nickel-gold layer by means of a second resist mask. The interconnects and contact surfaces are produced by means of two resist masks arranged one on top of the other, in such a way that the copper which forms the core of the interconnect is completely surrounded by the nickel-gold layer, which extends above the copper core, and an adjoining layer that extends beneath the copper core and comprises a diffusion barrier and seed layer.

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract: The invention provides a transfer technique by which the dimensional precision of a thin-film device is not deteriorated, even if the device is produced by transferring a fine structure or a thin-film circuit layer onto a substrate with an inferior shape-stability. The method includes: forming a fine structure or a thin-film circuit layer on a first substrate using a photolithographic patterning process; shifting the fine structure or the thin-film circuit layer from the first substrate onto a second substrate, or shifting the fine structure or the thin-film circuit layer from the first substrate onto the second substrate via a third substrate; and forming a thin-film pattern on the fine structure or the thin-film circuit layer shifted onto the second substrate by a non-photolithographic method.

Abstract: A phototransistor of a CMOS image sensor suitable for decreasing the size of layout, and a method for fabricating the phototransistor are disclosed, in which the phototransistor includes a first conductive type semiconductor substrate; an STI layer on the first conductive type semiconductor substrate, to define an active area and a device isolation area in the first conductive type semiconductor substrate; a second conductive type well in the first conductive type semiconductor substrate; a gate line on the first conductive type semiconductor substrate; an ohmic contact layer in the second conductive type well, wherein the ohmic contact layer is overlapped with the gate line in state of interposing the STI layer therebetween; and a contact to connect the gate line with the ohmic contact layer through the STI layer.

Abstract: Forming low contract resistance metal contacts on GaN films by treating a GaN surface using a chlorine gas Inductively Coupled Plasma (ICP) etch process before the metal contacts are formed. Beneficially, the GaN is n-type and doped with Si, while the metal contacts include alternating layers of Ti and Al. Additionally, the GaN film is dipped in a solution of HCl:H2O prior to metal contact formation.

Abstract: A method and apparatus are provided an interconnect cladding layer. In one embodiment, a first sacrificial layer is deposited over a substrate and patterned. In the vias created during the patterning operation, a conductive material is placed to create conductive interconnects. After planarizing the conductive material, the sacrificial layer is removed leaving the interconnect exposed. A cladding layer is then deposited over the conductive material.

Abstract: An integrated circuit device is provided including an integrated circuit substrate having a fuse region. A window layer is provided on the integrated circuit substrate that defines a fuse region. The window layer is positioned at an upper portion of the integrated circuit device and recessed beneath a surface of the integrated circuit device. A buffer pattern is provided between the integrated circuit substrate and the window layer and a fuse pattern is provided between the buffer pattern and the window layer. Methods of forming integrated circuit devices are also described.

Abstract: The invention, which relates to a method for fabricating metallic interconnects with copper-nickel-gold layer construction on electronic components, is based on the object of specifying a method by means of which it is possible to fabricate such metallic interconnects on different electronic components cost-effectively by means of the known and tried and tested methods which have a comprehensive corrosion protection. According to the invention, the object is achieved by virtue of the fact that the interconnects are embodied such that they are completely encapsulated by being deposited in a manner buried in a patterned dielectric layer in the lower region and being covered in the upper region by a nickel-gold layer adjoining the lower encapsulation without any gaps.

Abstract: A method of fabricating a chip-scale or wafer-level package having passivation layers on substantially all surfaces thereof to form a hermetically sealed package. The package may be formed by disposing a first passivation layer on the passive or backside surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.

Abstract: A camouflaged interconnection for interconnecting two spaced-apart regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first region forming a conducting channel between the two spaced-apart regions, the conducting channel being of the same common conductivity type and bridging a region between the two spaced-apart regions, and a second region of opposite conductivity to type, the second region being disposed between the two spaced-apart regions of common conductivity type and over lying the conducting channel to camouflage the conducting channel from reverse engineering.

Abstract: Methods for attaching two wafers are presented along with devices resulting from such methods. In one illustrative embodiment, a first wafer is provided having pillars for conducting an electric signal. The wafer also includes an electronic device such as an inductor or capacitor that may in some instances consume relatively large amounts of space. The first wafer is bonded to a second wafer so that a circuit on the second wafer may be electrically connected to the electronic device of the first wafer.

Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.

Abstract: A semiconductor device includes a substrate having first and second device regions separated from each other by a device isolation region, a first field effect transistor having a first polysilicon gate electrode and formed in the first device region, a second field effect transistor having a second polysilicon gate electrode and formed in the second device region, a polysilicon pattern extending over the device isolation region from the first polysilicon gate electrode to the second polysilicon gate electrode, and a silicide layer formed on a surface of the first polysilicon gate electrode, a surface of said the polysilicon gate electrode and a surface of the polysilicon pattern so as to extend on the polysilicon pattern from the first polysilicon gate electrode to the second polysilicon gate electrode, the silicide layer having a region of increased film thickness on the polysilicon pattern, wherein the silicide layer has a surface protruding upward in the region of increased film thickness.

Abstract: A method performed on a wafer having multiple chips, each including a doped semiconductor and substrate, involves etching an annulus trench partially into the substrate, metalizing the annulus trench with a metal, etching a via trench within the periphery of the annulus trench, making a length of the via trench electrically conductive, and thinning the substrate to expose the metal and the electrically conductive material.

Abstract: A memory structure has a plurality of row conductors intersecting a plurality of column conductors at a plurality of intersections. Each intersection includes an electrically linear resistive element in series with a voltage breakdown element.

Abstract: Multichip packages and methods for making same. The present invention generally allows for either the back of a flipchip, the back of a mother die, or both to be exposed in a multichip package. When the mother die is connected to the package contacts, the back of the flip chip is higher than the electrical connections. Accordingly, the back of the flip chip can be exposed. Furthermore, if a temporary tape substrate is used with a leadframe panel that does not have a die attach pad, the package can be even thinner. Once the temporary tape substrate is removed, both the back of the flipchip and the back of the mother die will be exposed from the encapsulant.

Abstract: A modifiable circuit structure and its method of formation are disclosed. The modifiable circuit structure electrically couples one portion of an interconnect with another portion of the interconnect through vias disposed in a dielectric layer. The combination of the modifiable circuit structure, the interconnect portions, and the vias provide a signal path between transistors in an integrated circuit. In one embodiment the modifiable circuit structure is a polysilicon feature formed over regions of a semiconductor substrate. In an alternative embodiment, the modifiable circuit structure is a diffusion region formed in region the semiconductor substrate.