Abstract: A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring.

Abstract: In one embodiment, a device includes a first conductive pad disposed over a substrate, and a etch stop layer disposed over a top surface of the first conductive pad. The device further includes a solder barrier disposed over the etch stop layer.

Abstract: A method includes applying solder to conductive pads of a semiconductor device, applying solder to conductive pads of a substrate, aligning the solder on the semiconductor device with the solder on the substrate such that portions of the solder on the semiconductor device contact corresponding portions of the solder on the substrate, heating the semiconductor device and the substrate to liquefy the solder, and exerting an oscillating force operative to oscillate the semiconductor device relative to the substrate at a frequency.

Abstract: In a method of manufacturing a ball grid array (BGA) semiconductor package, micro balls are mounted onto a respective plurality of through-holes formed in a substrate, and a semiconductor device is mounted on a die pad portion of the substrate. The semiconductor device and the micro balls are electrically connected with bonding wires. The semiconductor device, the die pad portion, the bonding wires, and parts of the micro balls are sealed together with an insulating resin to form an encapsulation member. The encapsulation member and the substrate are then cut into individual BGA semiconductor packages.

Abstract: Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.

Abstract: A mounting structure which reduces the mechanical stress added to a low-? material due to warping caused by the difference in thermal expansion coefficients between a chip and a chip support during mounting. This mounting structure includes: a low-? layer formed on top a semiconductor substrate; an electrode layer formed on the low-? layer; a protective layer formed the low-? layer and the electrode layer and having an opening reaching the electrode layer; a first solder layer filling the opening and formed on the electrode layer inside; a second solder layer formed on the first solder layer and having an elastic modulus smaller than the first solder layer; and a support layer connected to the second solder layer and supporting the semiconductor substrate. The protective layer has a greater elastic modulus and a smaller thermal expansion coefficient than an underfill layer formed between the protective layer and the support layer.

Abstract: A flip chip package manufacturing method is provided. A non-conductive film is pressed onto a wafer with multiple conductive bumps. The wafer is cut to multiple single chips. A carrier is provided, and a thermo-compression flip chip bonding process is executed to bond the non-conductive film onto the carrier. The carrier is transferred into a chamber with enclosed, pneumatic pressurized and heatingable characteristics to execute a de-void process to eliminate the bubbles and to execute a high-temperature soldering process to solder the single chip onto the carrier. The sequence of the de-void process and the high-temperature soldering process may exchange.

Abstract: Integrated circuits having electrically conductive traces are described. The electrically conductive traces may be formed of multiple electrically conductive layers. One or more of the multiple electrically conductive layers may have a cut formed therein to form a gap in that electrically conductive layer. One or more electrical conductive layers of the electrical conductive traces may bridge the gap.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

Abstract: A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads.

Abstract: A first substrate provided with a receiving area made from a first metallic material is supplied. A second substrate provided with an insertion area comprising a base surface and at least two bumps made from a second metallic material is arranged facing the first substrate. The bumps are salient from the base surface. A pressure is applied between the first substrate and the second substrate so as to make the bumps penetrate into the receiving area. The first metallic material reacts with the second metallic material so as to form a continuous layer of an intermetallic compound having a base formed by the first and second metallic materials along the interface between the bumps and the receiving area.

Abstract: A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias.

Abstract: A semiconductor device including a light sensing region disposed on a substrate is provided that includes a bond structure having one or more patterned layers underlying the pad element. The pad element may be coupled to the light sensing region and may be formed in a first metal layer disposed on the substrate. A second metal layer of the device has a first bond region, a region of the second metal layer that underlies the pad element. This first bond region of the second metal layer includes a pattern of a plurality of conductive lines interposed by dielectric. A via connects the pad element and the second metal layer.

Abstract: A method including forming a contact pad array on an integrated circuit substrate, the contact pad array including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads; and depositing solder on the accessible area of the contact pads. An apparatus including an integrated circuit substrate including a body having a nonplanar shape and a surface including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads.

Abstract: An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly. An active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the active layer and formed on the second surface of the insulating layer, and is also electrically connected to a printed circuit board. A method of fabricating an integrated circuit assembly includes coupling a handle wafer to the active layer of a semiconductor-on-insulator wafer, removing the substrate of the semiconductor-on-insulator, forming a bond pad connecting to the active layer on the exposed insulator surface, bonding the bond pad to a printed circuit board using a solder bump, and removing the handle wafer.

Abstract: The present disclosure relates to a method for forming a semiconductor device. The method includes forming a first aluminum pad layer on a metal layer, forming an adhesion layer on the first aluminum pad layer, etching the adhesion layer so as to form a patterned adhesion layer, and forming a second aluminum pad layer on the first aluminum pad layer and the patterned adhesion layer.

Abstract: A splash containment structure for semiconductor structures and associated methods of manufacture are provided. A method includes: forming wire bond pads in an integrated circuit chip and forming at least one passivation layer on the chip. The at least one passivation layer includes first areas having a first thickness and second areas having a second thickness. The second thickness is greater than the first thickness. The first areas having the first thickness extend over a majority of the chip. The second areas having the second thickness are adjacent the wire bond pads.

Abstract: A method uses a line pattern to form a semiconductor device including asymmetrical contact arrays. The method includes forming a plurality of parallel first conductive line layers extending in a first direction on a semiconductor substrate. In this method, the semiconductor substrate may have active regions forming an oblique angle with the first direction. The method may further include forming a first mask layer and a second mask layer and using the first mask layer and the second mask layer to form a trench comprising a line area and a contact area by etching the first conductive line layers using the first mask layer and the second mask layer. The method further includes forming a gap filling layer filling the line area of the trench and forming a spacer of sidewalls of the contact area and forming a second conductive line layer electrically connected to the active region.

Abstract: A semiconductor module is produced by providing a circuit carrier having a metallization, an electrically conductive wire and a bonding device. With the aid of the bonding device, a bonding connection is produced between the metallization and a first section of the wire. A separating location and a second section of the wire, the second section being spaced apart from the separating location, are defined on the wire. The wire is reshaped in the second section. Before or after reshaping, the wire is severed at the separating location, such that a terminal conductor of the semiconductor module is formed from a part of the wire. The terminal conductor is bonded to the metallization and having a free end at the separating location.

Abstract: The present invention provides a transfer substrate for transferring a metal wiring material to a transfer-receiving object, the transfer substrate comprising a substrate, at least one metal wiring material formed on the substrate and an underlying metal film formed between the substrate and the metal wiring material, wherein the metal wiring material is a molded article prepared by sintering, e.g., gold powder having a purity of 99.9% by weight or more and an average particle size of 0.01 ?m to 1.0 ?m and the underlying metal film is composed of a metal such as gold or an alloy. The transfer substrate is capable of transferring a metal wiring material to the transfer-receiving object even at a temperature for heating the transfer-receiving object of 80 to 300° C.

Abstract: Solder is simultaneously transferred from a mold to a plurality of 3D assembled modules to provide solder bumps on the modules. The mold includes cavities containing injected molten solder or preformed solder balls. A fixture including resilient pressure pads and vacuum lines extending through the pads applies pressure to the modules when they are positioned on the mold. Following reflow and solder transfer to the modules, the fixture is displaced with respect to the mold. The modules, being attached to the fixture by vacuum pressure through the pads, are displaced from the mold with the fixture.

Abstract: A method for manufacturing a chip package is provided. The method includes: forming an electrically insulating material over a chip side; selectively removing at least part of the electrically insulating material thereby forming a trench in the electrically insulating material, depositing electrically conductive material in the trench wherein the electrically conductive material is electrically connected to at least one contact pad formed over the chip side; forming an electrically conductive structure over the electrically insulating material, wherein at least part of the electrically conductive structure is in direct physical and electrical connection with the electrically conductive material; and depositing a joining structure over the electrically conductive structure.

Abstract: Semiconductor devices and methods for making semiconductor devices are disclosed herein. A semiconductor device configured in accordance with a particular embodiment includes a substrate having a source/drain region, an interconnect, and first and second electrodes extending between first and second sides of the substrate. The first electrode includes a first contact pad and a via extending through the substrate that connects the first contact pad with the interconnect. The second electrode includes a second contact pad and a conductive feature in the substrate that connects the second contact pad with the interconnect.

Abstract: A semiconductor device includes a substrate having external connection terminals, and a semiconductor chip mounted over a semiconductor-chip mounting portion of the substrate. The external connection terminals are formed by sequentially forming an electroless nickel plating layer, an electroless gold plating layer, and an electrolytic gold plating layer on a terminal portion formed on a surface of the substrate.

Abstract: Embodiments described herein generally relate to connections for integrated circuit (IC) dies. For example, in an embodiment an integrated circuit (IC) die is provided. The IC die includes a plurality of clusters of pads formed on a surface of the IC die, each cluster being associated with a respective circuit formed in the IC die. Each cluster includes a plurality of micropads each electrically coupled to the circuit associated with the cluster through a respective via and a sacrificial pad coupled to the circuit through the plurality of micropads, the sacrificial pad being larger than each of the micropads.

Abstract: Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non-attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.

Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.

Abstract: A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.

Abstract: A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.

Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) stress compensation layers that reduce stress on one or more underlying semiconductor devices, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices. A stressed element is located within a back-end-of-the-line stack at a position overlying the one or more semiconductor devices. A stressing layer is located over the stressed element induces a stress upon the stressed element. A stress compensation layer, located over the stressed element, provides a counter-stress to reduce the stress induced on the stressed element by the stressing layer. By reducing the stress induced on the stressed element, stress on the semiconductor substrate is reduced, improving uniformity of performance of the one or more semiconductor devices.

Abstract: A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.

Abstract: A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of die first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same.

Abstract: An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad. A first conductive material is deposited in the channel of the photoresist layer to form a column of conductive material. The remainder of the photoresist layer is removed. A masking layer is formed around the column of conductive material while exposing the interconnect pad within the column of conductive material. A second conductive material is deposited over the first conductive layer. The second conductive material extends above the column of conductive material. The masking layer is removed. The second conductive material is reflowed to form a column interconnect structure over the semiconductor device.

Abstract: A method of fabricating a semiconductor device includes forming a first insulation film over a semiconductor substrate, the semiconductor substrate including an outer region and an inner region located at an inner side of the outer region, forming a first wiring over the first insulation film in the inner region, forming a second insulation film over the first wiring and over the first insulation film, decreasing a film thickness of the second insulation film in the inner region with regard to a film thickness of the second insulation film in the outer region, and polishing the second insulation film after the decreasing of the film thickness of the second insulation film.

Abstract: A method to realize flux free indium bumping process includes several steps including substrate metallization, contact holes opening, underbump metallization (UBM) layer thickening, indium bump preparation and Ag layer coating. The method can be used in the occasion for some special application, e.g., the packaging of the photoelectric chip (with optical lens), MEMS and biological detection chip, where the usage of flux is prohibited.

Abstract: An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad.

Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die including a plurality of contact pads. An insulating layer is formed over the semiconductor wafer and contact pads. An under bump metallization (UBM) is formed over and electrically connected to the plurality of contact pads. A mask is disposed over the semiconductor wafer with a plurality of openings aligned over the plurality of contact pads. A conductive bump material is deposited within the plurality of openings in the mask and onto the UBM. The mask is removed. The conductive bump material is reflowed to form a plurality of bumps with a height less than a width. The plurality of semiconductor die is singulated. A singulated semiconductor die is mounted to a substrate with bumps oriented toward the substrate. Encapsulant is deposited over the substrate and around the singulated semiconductor die.

Abstract: A semiconductor chip (1) is flip-chip mounted on a circuit board (4) with an underfill resin (6) interposed between the semiconductor chip (1) and the circuit board (4) and a container covering the semiconductor chip (1) is bonded on the circuit board (4). At this point, the semiconductor chip (1) positioned with the underfill resin (6) interposed between the circuit board (4) and the semiconductor chip (1) is pressed and heated by a pressure-bonding tool (8); meanwhile, the surface of the underfill resin (6) protruding around the semiconductor chip (1) is pressed by the pressure-bonding tool (8) through a film (13) on which a surface unevenness is formed in a periodically repeating pattern, so that a surface unevenness (16a) is formed. The inner surface of the container covering the semiconductor chip (1) is bonded to the surface unevenness (16a) on the surface of the underfill resin.

Abstract: An electronic assembly includes a copper pillar attach substrate that has a dielectric layer and a solder resist layer overlying the dielectric layer. The solder resist layer has a plurality of solder resist openings. A plurality of parallel traces are formed on the dielectric layer. Each trace has a first end portion, a second end portion and an intermediate portion. The first and second end portions of each trace are covered by the solder resist layer and the intermediate portions are positioned in the solder resist openings. Each of the intermediate portions has at least one conductive coating layer on it and has a height measured from the dielectric layer to the top of the topmost conductive coating layer that is at least as great as the solder resist layer thickness.

Abstract: A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.

Abstract: Some implementations provide a semiconductor device that includes a substrate, several metal and dielectric layers coupled to the substrate, and a pad coupled to one of the several metal layers. The semiconductor device also includes a first metal layer coupled to the pad and an under bump metallization layer coupled to the first metal redistribution layer. The semiconductor device further includes a mold layer covering a first surface of the semiconductor device and at least a side portion of the semiconductor device. In some implementations, the mold layer is an epoxy layer. In some implementations, the first surface of the semiconductor device is the top side of the semiconductor device. In some implementations, the mold layer covers the at least side portion of the semiconductor device such that a side portion of at least one of the several metal layers and dielectric layers is covered with the mold layer.

Abstract: A microelectronic assembly includes a substrate having a first surface, a plurality of first conductive pads exposed thereon, and a plurality of first metal posts. Each metal post defines a base having an outer periphery and is connected to one of the conductive pads. Each metal post extends along a side wall from the base to ends remote from the conductive pad. The assembly further includes a dielectric material layer having a plurality of openings and extending along the first surface of the substrate. The first metal posts project through the openings such that the dielectric material layer contacts at least the outside peripheries thereof. Fusible metal masses contact the ends of some of first metal posts and extend along side walls towards the outer surface of the dielectric material layer. A microelectronic element is carried on the substrate and is electronically can be connected the conductive pads.

Abstract: A method is provided for fabricating an interconnection structure. The method includes providing a semiconductor substrate having certain semiconductor devices inside, a dielectric layer covering the semiconductor devices, and vias inside the dielectric layer connecting with connection pads of the semiconductor devices. The method also includes forming a first conductive layer on the semiconductor substrate, and forming a second conductive layer with smaller grain sizes by doping the first conductive layer. Further, the method includes forming an interconnection pad by patterning the second conductive layer, and forming a connection wire on the interconnection pad.

Abstract: A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer.

Abstract: A leadless package and method for manufacturing silicon based leadless QFN/SON compatible packages are described. In addition the package allows for hermetic sealing of devices while maintaining electrical and optical access. Micro-vias with feed-through metallization through a silicon structure facilitates a surface mount technology compatible silicon package with bottom SMT pads and top surface device integration. Sloped edges on the SMT side enable solder filleting for post solder inspection. Hermetic seal can be attained for example using anodic bonding of a glass lid or using metal soldering. Metal soldering enables the use of solder bumps to provide electrical connections for the package to the lid with integrated device functionality used for sealing. Hermetically sealed silicon packages eliminates the need for an extra packaging layer required in plastic packages and provides a standard interface for enclosing one or more discrete devices.

Abstract: A contact pad for an electronic device integrated in a semiconductor material chip is formed from a succession of protruding elements. Each protruding element extends transversally to a main surface of the chip and has a rounded terminal portion. Adjacent pairs protruding elements define an opening which is partially filled with a first conductive material to form a contact structure that is in electrical contact with an integrated electronic device formed in the chip. A layer of a second conductive material is deposited to cover said protruding elements and the contact structures so as to form the contact pad.

Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.

Abstract: A bond pad region is provided that reduces parasitic capacitance generated between bond pad metallization and underlying silicon by reducing the effective area of the bond pad, while maintaining flexibility of wire bond sites and ensuring mechanical integrity of the wire bonds. Embodiments provide, in a region that would be populated by a traditional bus bar bond pad, a small bus bar bond pad that is less than half the area of the region and populating at least a portion of the remaining area with metal tiles that are not electrically connected to the small bus bar bond pad or to each other. The metal tiles provide an attachment area for at least a portion of one or more wire bonds. Only those tiles involved in connection to a wire bond contribute to parasitic capacitance, along with the small bus bar pad.

Abstract: A method of making a bonding pad for a semiconductor device which includes forming a first region over a buffer layer, where the first region includes aluminum and having a first average grain size. The method further includes forming a second region over the first region, where the second region includes aluminum, and where the second region has a second average grain size different from the first average grain size. Additionally, the method includes forming a first passivation layer surrounding the first region and the second region. Furthermore, the method includes forming a second passivation layer partially covering the second region, where the first region and the second region extend along a top surface of the first passivation layer.

Abstract: Described is a method of forming a solder deposit on a substrate comprising the following steps i) provide a substrate that includes at least one inner contact area, ii) contact the entire substrate area including the at least one inner contact area with a solution suitable to provide a conductive layer on the substrate surface, iii) form a patterned resist layer, iv) electroplate a solder deposit layer containing a tin or tin alloy onto the inner contact area, v) remove the patterned resist layer, vi) form a solder resist layer having solder resist openings on the substrate surface.