Abstract: A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

Abstract: The present invention discloses a wafer level chip scale package device. The device includes: a chip including at least one bonding pad; a UBM layer disposed on the bonding pad; a pre-solder layer disposed on the UBM layer; and a bump melted and combined with the pre-solder layer.

Abstract: A semiconductor device with improved quality and reliability is provided. In a UBM formed over an electrode pad located over a semiconductor substrate, the edge (end) of an Au film as an upper layer is located inside or in the same position as the edge (end) of a TiW film as a lower layer, which can suppress the formation of a suspended part in the Au film. This arrangement can prevent the occurrence of electrical short circuit between the adjacent pads due to the suspended part and the adhesion of the suspended part as foreign matter to the semiconductor substrate, thus improving the quality and reliability of the semiconductor device (semiconductor chip).

Abstract: A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots, forming a plurality of bottom coverage layers at the opening slots, proceeding a heat procedure, forming a plurality of external coverage layers to make each of the external coverage layers connect with each of the bottom coverage layers, wherein said external coverage layer and said bottom coverage layer form a wrap layer and completely surround the copper bump, forming a plurality of connective layers on the external coverage layers, removing the photoresist layer, removing the second areas and enabling each of the first areas to form an under bump metallurgy layer.

Abstract: A semiconductor device includes a semiconductor element having a plurality of element electrodes formed thereon, a circuit board having board electrodes respectively corresponding to the element electrodes formed thereon and having the semiconductor element mounted thereon, and bumps each of which is provided on at least one of the element electrode and the board electrode, and connects together the element electrode and the board electrode corresponding to each other when the semiconductor element is mounted on the circuit board. Furthermore, at least one of a dielectric layer and a resistive layer is provided between at least one of the bumps and the element or board electrode on which the at least one of the bumps is provided, so that the element or board electrode, the dielectric layer or the resistive layer, and the bump form a parallel-plate capacitor or electrical resistance.

Abstract: A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.

Abstract: A semiconductor device includes: a foundation layer that is provided on a substrate and is electrically conductive; a nickel layer provided on the foundation layer; and a solder provided on the nickel layer, the nickel layer having a first region on a side of the foundation layer and a second region on a side of the solder, the second region being harder than the first region.

Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.

Abstract: A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer.

Abstract: A method of making a semiconductor device comprises providing a carrier, forming a first conductive layer extending above a surface of the carrier, providing a substrate, disposing the first conductive layer into a first surface of the substrate, removing the carrier, forming a second conductive layer extending above the first surface of the substrate to create a vertical offset between the first conductive layer and second conductive layer, and forming a plurality of first bumps over the first conductive layer and second conductive layer. The method further includes the steps of disposing a third conductive layer into a second surface of the substrate opposite the first surface of the substrate, forming a fourth conductive layer extending above the second surface of the substrate to create a vertical offset between the third conductive layer and fourth conductive layer, and forming a plurality of second bumps.

Abstract: A method of forming a device includes providing a wafer including a substrate; and forming an under-bump metallurgy (UBM) layer including a barrier layer overlying the substrate and a seed layer overlying the barrier layer. A metal bump is formed directly over a first portion of the UBM layer, wherein a second portion of the UBM layer is not covered by the metal bump. The second portion of the UBM layer includes a seed layer portion and a barrier layer portion. A first etch is performed to remove the seed layer portion, followed by a first rinse step performed on the wafer. A second etch is performed to remove the barrier layer portion, followed by a second rinse step performed on the wafer. At least a first switch time from the first etch to the first rinse step and a second switch time from the second etch to the second rinse step is less than about 1 second.

Abstract: A method for fabrication of bonding solder layers on metal bumps with improved coplanarity, applicable to the flip-chip bump bonding technique for semiconductor IC packaging. When metal bumps have different sizes, the bonding solders thereon may have different heights after high-temperature reflows. The present invention can improve the coplanarity of bonding solders, and mitigating or even eliminating the difficulties in downstream packaging and testing caused by the inconsistent height of bonding solders. To achieve this purpose, the present invention proposes a two-step fabrication method for controlling the surface areas of the metal bumps and the bonding solder layers thereon separately, and thereby improving the coplanarity of the bonding solders after high-temperature reflows. The two-step fabrication method includes: a first-step process for forming metal bumps on the semiconductor devices; and a second-step process for forming bonding solder layers of different sizes on the metal bumps.

Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes depositing a layer of a first metallic material on a semiconductor chip. The first layer has a first physical quantity. A layer of a second metallic material is deposited on the layer of the first metallic material. The second layer has a second physical quantity. The first and second layers are reflowed to form a solder structure with a desired ratio of the first metallic material to the second metallic material.

Abstract: A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Abstract: Embodiments of the present invention relate to circuit layouts that are compatible with printing electronic inks, printed circuits formed by printing an electronic ink or a combination of printing and conventional blanket deposition and photolithography, and methods of forming circuits by printing electronic inks onto structures having print-compatible shapes. The layouts include features having (i) a print-compatible shape and (ii) an orientation that is either orthogonal or parallel to the orientation of every other feature in the layout.

Abstract: A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus.

Abstract: A fine pitch solder bump structure with a built-in stress buffer that is utilized in electronic packages, and a method of producing the fine pitch solder bump structure with built-in stress buffer. Employed is a very thick final passivation layer that is constituted of a polyimide as a so-called “cushion” for a minimal thickness of UBM (BLM) pad and solder material, while concurrently completely separating the resultingly produced polyimide islands, so that the polyimide material provides most of the physical height for the “standoff” of a modified C4 (controlled collapse chip connection) structure.

Abstract: A semiconductor element mounted on an insulating resin layer formed on a wiring layer is sealed by a sealing resin. On the wiring layer, a protruding electrode protruding to the side of the semiconductor element and a protruding section are integrally formed with the wiring layer, respectively. The protruding electrode is electrically connected to an element electrode of the semiconductor element by penetrating the insulating resin layer. The protruding section is arranged to surround the semiconductor element along the four sides of the semiconductor element, and is embedded in the sealing resin up to a position above a section where the protruding electrode and the element electrode are bonded.

Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Abstract: The micro device includes a support substrate, and a movable structure configured to move with respect to the support substrate. At least one of the support substrate and the movable structure is provided with at least one protrusion protruding towards the other of the support substrate and the movable structure. Further, a base portion extending into the one of the support substrate and the movable structure is provided integrally with the at least one protrusion. With this configuration, the protrusion is securely held by the base portion, and the detachment of the protrusion can therefore be prevented even after repeated collisions between the support substrate and the movable structure via the protrusion.

Abstract: A system and method comprises depositing a dielectric layer on a substrate and depositing a metal layer on the dielectric layer. The system and method further includes depositing a high temperature diffusion barrier metal cap on the metal layer. The system and method further includes depositing a second dielectric layer on the high temperature diffusion barrier metal cap and the first dielectric layer, and etching a via into the second dielectric layer, such that the high temperature diffusion barrier metal cap is exposed. The system and method further includes depositing an under bump metallurgy in the via, and forming a C4 ball on the under bump metallurgy layer.

Abstract: A sacrificial material applied to a thin die prior to die attach provides stability to the thin die and inhibits warpage of the thin die as heat is applied to the die and substrate during die attach. The sacrificial material may be a material that sublimates at a temperature near the reflow temperature of interconnects on the thin die. A die attach process deposits the sacrificial material on the die, attaches the die to a substrate, and applies a first temperature to reflow the interconnects. At the first temperature, the sacrificial material maintains substantially the same thickness. A second temperature is applied to sublimate the sacrificial material leaving a clean surface for the later packaging processes. Examples of the sacrificial material include polypropylene carbonate and polyethylene carbonate.

Abstract: Generally, the subject matter disclosed herein relates to methods for forming modern sophisticated semiconductor devices, and more specifically, methods wherein substantially lead-free solder bumps may be formed above a contact layer of a semiconductor chip. One illustrative method disclosed herein includes forming a solder bump above a metallization layer of a semiconductor device, removing an oxide film from a surface of the solder bump, and, after removing the oxide film, performing a solder bump reflow process in a reducing ambient to reflow the solder bump.

Abstract: A semiconductor device has a semiconductor die having a first surface and a second surface wherein at least one bond pad is formed on the first surface. A passivation layer is formed on the first surface of the semiconductor device, wherein a central area of the at least one bond is exposed. A seed layer is formed on exposed portions of the bond pad and the passivation layer. A conductive pillar is formed on the seed layer. The conductive pillar has a base portion wherein the base portion has a diameter smaller than the seed layer and a stress relief portion extending from a lateral surface of a lower section of the base portion toward distal ends of the seed layer. A solder layer is formed on the conductive pillar.

Abstract: A method includes forming an under-bump metallurgy (UBM) layer overlying a substrate, and forming a mask overlying the UBM layer. The mask covers a first portion of the UBM layer, and a second portion of the UBM layer is exposed through an opening in the mask. A metal bump is formed in the opening and on the second portion of the UBM layer. The mask is then removed. A laser removal is performed to remove a part of the first portion of the UBM layer and to form an UBM.

Abstract: A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.

Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.

Abstract: A system and method for forming conductive connections is disclosed. An embodiment comprises forming conductive material on to contacts of a semiconductor substrate. The semiconductor substrate is then inverter such that the conductive material is beneath the semiconductor substrate, and the conductive material is reflowed to form a conductive bump. The reflow is performed using gravity in order to form a more uniform shape for the conductive bump.

Abstract: Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers.

Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the semiconductor die. A first insulating layer is formed over the semiconductor die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is formed over the first and second conductive layers within openings of a second insulating layer. The second insulating layer is removed. The interconnect structure can be a conductive pillar or conductive pad. A bump material can be formed over the conductive pillar. A protective coating is formed over the conductive pillar or pad to a thickness less than one micrometer to reduce oxidation. The protective coating is formed by immersing the conductive pillar or pad into the bath containing tin or indium.

Abstract: A semiconductor device includes a barrier layer between a solder bump and a post-passivation interconnect (PPI) layer. The barrier layer is formed of at least one of an electroless nickel (Ni) layer, an electroless palladium (Pd) layer or an immersion gold (Au) layer.

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a first polymer film to a side of a semiconductor chip and forming a first underbump metallization structure with at least a portion on the first polymer film. A second polymer film is applied on the first polymer film with an opening exposing a portion of the first underbump metallization structure.

Abstract: In connection with a semiconductor device in which a conductive member is coupled to the surface of a bonding pad exposed from an opening formed in a passivation film, there is provided a technique able to suppress the occurrence of a crack in the passivation film. A second planar distance between a first end of an electrode layer and a first end of a pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the pad.

Abstract: In one embodiment, a preliminary solder layer made of a Sn alloy is formed on a connecting pad of a wiring substrate. A solder bump made of a Sn alloy is formed on an electrode pad of a semiconductor chip. After contacting the preliminary solder layer and the solder bump, the preliminary solder layer and the solder bump are melted by heating to a temperature of their melting points or higher to form a solder connecting part made of a Sn alloy containing Ag and Cu. Only the preliminary solder layer of the preliminary solder layer and the solder bump is composed of a Sn alloy containing Ag.

Abstract: A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block and the second polymer block are located at two sides of the first groove, the first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first connection slot and the first groove. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove, a third connection slot and a fourth connection slot communicated with each other. The connection metal layer covers the under bump metallurgy layer to form a third groove, a fifth connection slot and a sixth connection slot communicated with each other.

Abstract: A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Abstract: A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block and the second polymer block are located at two sides of the first groove, the first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first connection slot and the first groove. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove, a third connection slot and a fourth connection slot communicated with each other. The connection metal layer covers the under bump metallurgy layer to form a third groove, a fifth connection slot and a sixth connection slot communicated with each other.

Abstract: A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier.

Abstract: A semiconductor wafer has a first conductive layer formed over its active surface. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A UBM layer is formed around a bump formation area over the second conductive layer. The UBM layer can be two stacked metal layers or three stacked metal layers. The second conductive layer is exposed in the bump formation area. A second insulating layer is formed over the UBM layer and second conductive layer. A portion of the second insulating layer is removed over the bump formation area and a portion of the UBM layer. A bump is formed over the second conductive layer in the bump formation area. The bump contacts the UBM layer to seal a contact interface between the bump and second conductive layer.

Abstract: The manufacturing method includes: forming a seed film on a semiconductor chip; forming a photoresist having an opening above an electrode of the semiconductor chip on the seed film; forming a first Au bump on the seed film in the opening by electrolytic plating with a current density of 1.5 A/dm2 or above; grinding a surface of the first Au bump; stripping the photoresist; and removing the seed film by dry-etching.

Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Abstract: A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose the seed layer on the pads; forming pillars by performing a primary electroplating on a region exposed by the photoresist pattern; forming a solder layer by performing a secondary electroplating on the pillars; removing the photoresist pattern; forming solder bumps, in which solders partially cover surfaces of the pillars, by performing a reflow process on the semiconductor substrate; and removing portions of the seed layer formed in regions other than the solder bumps.

Abstract: A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. A protective layer is formed over the passivation layer. The protective layer is removed over the first contact pad, but not from the second contact pad. A conductive layer is formed over the first contact pad. The conductive layer is coiled on the surface of the substrate to produce inductive properties. The formation of the conductive layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the protective layer. The protective layer is removed from the second contact pad after forming the conductive layer over the first contact pad. An external connection is formed on the second contact pad.

Abstract: A circuit board and method of manufacturing a circuit board. The circuit board includes a substrate, a conductor layer formed on the substrate, and an insulation layer formed on the substrate and the conductor layer, the insulating layer having an opening with an undercut therein, the opening reaching the conductor layer. A metal layer is formed in the opening of the insulation layer and connected to the conductor layer, a solder layer formed in the opening of the insulation layer and outside of the opening; and an alloy layer formed in a boundary region between the metal layer and the solder layer in the opening. The alloy layer includes a metal of the metal layer and a composition of the solder layer, the alloy layer being more fragile than the metal layer and being formed in a position misaligned from an edge of the undercut of the opening formed on the insulation layer.

Abstract: Structures are provided with raised buffer pads for solder bumps. Methods are also provided for forming the raised buffer pads for solder bumps. The method includes forming a raised localized buffer pad structure on a tensile side of a last metal layer of a solder bump connection. The raised localized buffer pad structure increases a height of a portion of a pad structure of the solder bump connection with respect to a compressive side of the last metal layer.

Abstract: A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability.

Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate having a transistor and a metallization layer; forming a metal pad in direct contact with the metallization layer of the substrate; forming a passivation layer in direct contact with the metal pad and covering the substrate; forming a routing trace above the passivation layer in direct contact with the metal pad, and the routing trace is substantially larger than the metal pad, and the routing trace is not electrically insulated by a subsequent layer; and forming a bump connected to the metal pad with the routing trace.

Abstract: A method of making a semiconductor structure includes patterning a barrier layer metallurgy (BLM) which forms an undercut beneath a solder material, and forming a repair material in the undercut and on the solder material. The method also includes removing the repair material from the solder material, and reflowing the solder material.

Abstract: Embodiments of the invention are concerned with a method of manufacturing a radiation detector having one or more conductive contacts on a semiconductor substrate, and comprise the steps of: applying a first conductive layer to a first surface of the semiconductor substrate; applying a second conductive layer to form a plurality of contiguous layers of conductive materials, said plurality of contiguous layers including said first conductive layer; and selectively removing parts of said plurality of contiguous layers so as to form said conductive contacts, the conductive contacts defining one or more radiation detector cells in the semiconductor substrate.