Abstract: Downhill wire bonding process for QFN is performed with a capillary using goldwire that connects die (the Integrated Circuit or the substrate) and the stitch platform also called lead fingers. The goldwire is molten into a ball by applying high current. The molten ball is compressed against the bond pads of the integrated circuit using high temperature and ultrasonic energy. To complete the connection, the capillary is lifted vertically from the bond pads of the die or integrated circuit to loop over to the lead finger so that the goldwire is compressed against the lead finger with a reduced angle of approach of the capillary. Downhill wire bonding of the lead frames is advantageously addressed by increasing the thickness of the stitch platform so as to reduce the angle of approach of the capillary during the downhill wire bonding process between various components of the semiconductor.

Abstract: A wire bond system including providing an integrated circuit die with a bond pad thereon, forming a soft bump on the bond pad, and wire bonding a hard-metal wire on the soft bump.

Abstract: A manufacturing method of a semiconductor device, comprising the steps of forming an insulation layer, which has an opening section in an area including an area on an electrode pad, on a top surface of the semiconductor substrate on which the electrode pad is formed; at least forming a first barrier metal layer, which becomes a part of a leading wiring layer, in an inner peripheral surface of the opening section including the top surface of the electrode pad; at least forming a main conductor layer, which becomes a part of the leading wiring layer, in an area surrounded by the first barrier metal layer in the opening section; eliminating an upper portion of the main conductor layer at least to a position at which the first barrier metal layer is exposed, and forming a second barrier metal layer, which becomes a part of the leading wiring layer, so as to cover the whole top surface of the main conductor layer.

Abstract: A method of making a semiconductor device is disclosed including die bond pads which are heightened to allow wire bonding of offset stacked die even in tight offset configurations. After a first die is affixed to a substrate, one or more layers of an electrical conductor may be provided on some or all of the die bond pads of the first substrate to raise the height of the bond pads. The conductive layers may for example be conductive balls deposited on the die bond pads of the first substrate using a known wire bond capillary. Thereafter, a second die may be added, and wire bonding of the first die may be accomplished using a known wire bond capillary mounting a wire bond ball on a raised surface of a first semiconductor die bond pad.

Abstract: Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over the molding of the first package with the first side of the second substrate facing the die attach side of the first package substrate. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated with both the land side of the second substrate and a portion of the land side of the first package substrate exposed, so that second level interconnection and interconnection with additional components may be made.

Abstract: An integrated circuit provides a carrier substrate, a wiring level above a carrier substrate, wherein the wiring level comprises a first conductor track composed of a first conductive material and a second conductor track composed of the first conductive material, an insulating layer above the wiring level, wherein the insulating layer comprises a first opening in a region of the first conductor track of the wiring level and a second opening in a region of the second conductor track of the wiring level and a contact bridge composed of a second conductive material, wherein the contact bridge is connected to the first conductor track in a region of the first opening and is connected to the second conductor track in a region of the second opening.

Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Abstract: A method of forming solder balls may involve forming bumps through wire boding on land patterns of a circuit substrate. Solder cream may be applied to the bumps through screen printing. The solder cream may be melted via reflow to form solder balls in which the bumps are embedded.

Abstract: A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.

Abstract: A wire bond circuit device has a circuit die in which substantially all of the input/output (I/O) pads are disposed along the outermost row of pads. A substrate onto which the die is disposed has wedges that are similarly arranged in rows, with the wedges used to carry I/O placed closest to the circuit die. As a result, lowest-tiered bond wire is used to connect the I/O-related pads to their respective wedges.

Abstract: System and method for creating single stud bumps having an increased stand-off height. A preferred embodiment comprises a capillary for use in creating stud bumps in a flip chip assembly, comprising a hole section adapted to pass a wire, a chamfer section providing a transition from the hole section to a stud bump section, and a sidewall within the stud bump section, the sidewall having a sidewall height, wherein the side wall height is equal to, or greater than, the a diameter of the stud bump section.

Abstract: A manufacturing method is for providing an excellent wire bonding property in the manufacturing of a semiconductor device using an organic resin wiring substrate. In the manufacturing of the semiconductor device, a thermosonic wire bonding apparatus is used when the electrodes of a semiconductor element fixed to the principal surface of a substrate are connected to lines on the substrate with wires.

Abstract: A semiconductor device includes a first wiring layer having a first wiring pitch and a second wiring layer having a second wiring pitch that differs from the first wiring pitch. The device further includes a third wiring layer which connects the first wiring layer and the second wiring layer and has a wiring incident angle of less than 45 degrees to at least the first wiring layer.

Abstract: Configuration for testing the bonding positions of conductive drops and test method by using the same is disclosed. In the invention, a special configured contact pad for setting a conductive drop and an associated wire pattern are useful for knowing the drop condition of single or several displaying panels. The contact pad comprises at least two conductive members respectively coupled to two wires; and an isolating portion between conductive members for separation. The normal dropping position of a conductive drop on the contact pad includes at least a portion of the conductive members. Accordingly, the contact pad is originally an open-circuit without conductive drop thereon, but the contact pad is conductive when the contact drop sets on its normal dropping position. Whether the conductive drop forms on the normal dropping position of the contact pad is determined by measuring the electrical properties of the contact pad.

Abstract: A manufacturing technique that involves embedding one or more semiconductor die into a support substrate and forming conductive traces that lead from die contact pads to redistributed contact pads on the support substrate. Active surfaces of the dice and a working surface of the support substrate are substantially coplanar and the conductive traces are formed on the coplanar surfaces. The redistributed contact pads are sufficiently spaced apart from each other so that conductive balls can be formed thereon. Individual semiconductor device packages are singulated from the support substrate.

Abstract: Methods and apparatus for eliminating wire sweep and shorting while avoiding the use of under-bump metallization and high cost attendant to the use of conventional redistribution layers. An anisotropically conductive (z-axis) conductive layer in the form of a film or tape is applied to the active surface of a die and used as a base for conductive redistribution bumps formed on the anisotropically conductive layer, bonded to the ends of conductive columns thereof and wire bonded to the bond pads of the die. Packages so formed may be connected to substrates either with additional wire bonds extending from the conductive redistribution bumps to terminal pads or by flip-chip bonding using conductive bumps formed on the conductive redistribution bumps to connect to the terminal pads. The acts of the methods may be performed at the wafer level. Semiconductor die assemblies may be formed using the methods.

Abstract: A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.

Abstract: Provided is a method of bonding a wire of a semiconductor package, by which a loop height may be reduced and/or a bonding reliability may be enhanced. In the method, a ball bump may be formed on a bonding pad on a semiconductor chip using a capillary through which a wire may be supplied. The wire may then be cut from the ball bump using the capillary. Subsequently, the capillary may be moved to an interconnection corresponding to the bonding pad of the semiconductor chip to perform stitch bonding of the wire supplied through the capillary on the interconnection. The capillary may again be moved to the ball bump formed on the bonding pad to bond the wire on the ball bump.

Abstract: A method for electrically connecting an integrated circuit to a via in a substrate is disclosed. The method can include deforming a ball over the via to form a bump and attaching a bond wire to the bump. The method also can include attaching the bond wire to the integrated circuit, such as by forming an end of the bond wire into a second ball and deforming the second ball over the integrated circuit. Alternatively, the method can include forming an end of the bond wire into a ball and deforming the ball over the via. Embodiments of a disclosed integrated circuit and substrate assembly can include, for example, a bump aligned with at least a portion of a via in a substrate and a bond wire attached to the integrated circuit and the bump. Other embodiments can include a via with a top metal cap and an upper plating.

Abstract: An integrated circuit system provides a precursor for an integrated wire bond and flip chip structure. The precursor has a plurality of contact pads thereon. A layer of titanium is deposited on the precursor. A layer of nickel-vanadium is deposited on the layer of titanium. A layer of copper is deposited on the layer of nickel-vanadium. A mask is formed on at least a portion of the layer of copper. Portions of the layers of copper and nickel-vanadium not protected by the mask are removed to expose portions of the layer of titanium. The exposed portions of the layer of titanium are etched with an etching solution consisting of an etchant, a viscosity modifier, and an oxidizer.

Abstract: Disclosed are an integrated circuit component capable of simply mounting at low cost a chip part which adjusts impedance of wiring patterns as well as capable of effectively reducing switching noise from an integrated circuit, and a method for mounting the chip part. The integrated circuit component of the present invention has a constitution that a bypass capacitor is mounted on a wiring board side of a gap between the wiring board and an LSI chip. Therefore, as compared with a case where the capacitor is mounted on the LSI chip side, a transmission path through the capacitor can be extremely shortened. As a result, inductance components of the feeder line can be reduced, so that a response delay of power transmitted through the feeder line can be sufficiently suppressed.

Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact.

Abstract: A method and apparatus for bonding a wire and a wire bond device formed by the same are disclosed. The method includes providing a carrier with at least a first pad, providing a semiconductor chip having at least the second pad, the at least second pad being smaller than the first a pad, forming a conductive stud bump on the second pad, and forming a bonding wire that has two terminal portions, which are respectively bonded to the first pad and the stud bump to electrically connect the first pad and the second pad. The stud bump is bonded to the second pad by a ball bonding method which uses a wire that has an approximately smaller diameter than the bonding wire. Further, a prominence formed on one end of the terminal portions is provided which has an approximately larger diameter than the stud bump.

Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, a substrate, and at least one bond wire. The substrate has a reduced-thickness base adjacent terminals of the microelectronic component and a body having a contact surface spaced farther from the microelectronic component than a bond pad surface of the base. The bond wire couples the microelectronic component to a bond pad carried by the bond pad surface and has a maximum height outwardly from the microelectronic component that is no greater than the height of the contact surface from the microelectronic component.

Abstract: Methods and apparatus for eliminating wire sweep and shorting while avoiding the use of under-bump metallization and high cost attendant to the use of conventional redistribution layers. An anisotropically conductive (z-axis) conductive layer in the form of a film or tape is applied to the active surface of a die and used as a base for conductive redistribution bumps formed on the anisotropically conductive layer, bonded to the ends of conductive columns thereof and wire bonded to the bond pads of the die. Packages so formed may be connected to substrates either with additional wire bonds extending from the conductive redistribution bumps to terminal pads or by flip-chip bonding using conductive bumps formed on the conductive redistribution bumps to connect to the terminal pads. The acts of the methods may be performed at the wafer level. Semiconductor die assemblies may be formed using the methods.

Abstract: Aspects of the current invention are directed to a method of mounting a flexible printed circuit and a manufacturing method of an electric optical device. Each of the methods form semiconductor elements and first terminal portions for electrically connecting the semiconductor elements and the outside of the board. These terminal portions have are completely or partially covered with an organic film 37 and are pressed into second terminal portion on the flexible printed circuit from the direction above the organic film thereby creating an electrical connection. Optionally, an anisotropic conductive paste or anisotropic conductive film may be provided between the second terminal portion and the organic film.

Abstract: Methods of forming a semiconductor package including a single-sided substrate are disclosed. In a first embodiment of the present invention, a substrate may include a conductive layer on a top surface of the substrate, i.e., on the same side of the substrate as where the die are mounted. In a second embodiment of the present invention, a substrate may include a conductive layer on a bottom of the substrate, i.e., on the opposite side of the substrate as where the die are mounted.

Abstract: A metal structure for an integrated circuit, which has copper interconnecting metallization (311) protected by an overcoat layer (320). A portion of the metallization is exposed in a window (301) opened through the thickness of the overcoat layer. The metal structure comprises a patterned conductive barrier layer (330) positioned on the copper metallization, wherein this barrier layer forms a trough with walls (331) conformal with the overcoat window. The height (331a) of the wall is less (between 3 and 20 %) than the overcoat thickness (320a), forming a step (340). A plug (350) of bondable metal, preferably aluminum, is positioned in the trough and has a thickness equal to the trough wall height (331a).

Abstract: An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

Abstract: Various semiconductor devices can be formed at the end of a common fabrication process, thereby significantly improving manufacturing flexibility, by selectively wiring bonding different CMOS circuits to different MEMS, which are formed on the same semiconductor die. A semiconductor device that has a number of CMOS circuits and a number of MEMS is formed on the same semiconductor wafer in adjacent regions on the wafer, and then diced such that the CMOS circuits and the MEMS are formed on the same die. After dicing, different CMOS circuits and different MEMS can be selectively connected during the wire bonding step to form the different semiconductor devices.

Abstract: Disclosed is a method of realizing thermosonic wire bonding between metal wires and copper pads by depositing a thin film to surfaces of semiconductor chips with copper pads, where a thin film that provides the effect of self-passivation to prevent oxidization of the copper pads located thereunder is deposited on surfaces of the copper pads to provide sufficient protection to the chips with copper pads thereby preventing copper from oxidizing at elevated temperature during packaging, due to die sawing, die mounting or curing and thermosonic wire bonding, which would result in failure of bonding metal wires to the copper pads, poor bondability between the metal wires and the copper pads, or low bonding strength of the bonds.

Abstract: An integrated circuit device comprising an integrated circuit die having a plurality of bond pads that are selectively connected to a plurality of inner leads of a leadframe. At least two bond pads are connected to at least one of the inner leads, and/or at least two inner leads are connected to at least one of bond pads with a single bond wire. A single bond wire is ball or wedge bonded to a first bond pad or inner lead and subsequently wedge bonded to one or more second bond pads or inner leads, then it is connected to a third or last bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and/or inner lead(s). The bond pad(s) of the die and/or inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.

Abstract: A multilayer ceramic capacitor (10) having reduced inductance which is separated into a first layer body (11) and a second layer body (12). The first layer body (11) and the second layer body (12) are formed by alternately layering inner electrodes (inner electrode 13a, inner electrode 13b) so as to face each other and sandwich ceramic layers (14). The ceramic layers (14) of the second layer body (12) are thicker than the ceramic layers (14) of the first layer body (11), so as to compensate for electrode height difference. Moreover, in the second layer body (12), the inner electrodes (13b) are electrically connected by via electrode (15b) so that the part of the via electrode (15b) extending without connection to an inner electrode (13b) is shortened.

Abstract: A tip of a first wire is bonded to a first electrode. The first wire is drawn from the first electrode to a bump on a second electrode. A part of the first wire is deformed and bonded to the bump. A tip of a second wire formed in the shape of a ball is bonded to the bump by using a tool in a state in which at least a part of the tip is superposed on the first wire. A part of the first wire which is not deformed by bonding is prevented from being deformed by the tip of the second wire and the tool.

Abstract: A carrier-free semiconductor package and a fabrication method thereof are provided. The fabrication method includes the steps of: providing a carrier having a plurality of electrical contacts formed thereon; mounting at least one chip on the carrier; electrically connecting the chip to the electrical contacts via a plurality of bonding wires; forming a coating layer on each of the electrical contacts to encapsulate a bonded end of each of the bonding wires on the electrical contacts; performing a molding process to form an encapsulant for encapsulating the chip, the bonding wires and the electrical contacts; and removing the carrier, such that bottom surfaces of the electrical contacts are exposed from the encapsulant. This obtains a semiconductor package not having a carrier, and the coating layers can enhance adhesion between the electrical contacts and the encapsulant.

Abstract: A method of making a packaged electrical device comprises the steps of (a) connecting one end of a wire to a first point (e.g., a first electrical node) in the package, and (b) connecting the other end of the wire to a second point (e.g., a second electrical node) in the package, characterized by (c) causing energy from an external source to heat at least one predetermined segment of the wire to a temperature that is below its melting point (MP) but not below its recrystallization temperature (RCT), and (d) cooling the heated segment to a temperature below its RCT [e.g., to room temperature (RT)], thereby to increase the stiffness modulus of the segment. In one embodiment, the external source is a laser whose optical output is absorbed by the segment. In another embodiment, the heated segment is rapidly cooled (i.e., quenched) to RT.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.

Abstract: Disclosed is a semiconductor device that includes an electrically insulating, sheet-like substrate with first and second surfaces, at least one opening, and a certain thickness. On the first surface are a plurality of electrically conductive routing strips and a plurality of contact pads; at least one of the contact pads is electrically connected with at least one of the routing strips, and may have a solder body attached. A semiconductor chip is positioned in the opening while leaving a gap to the substrate; the chip has an active surface including at least one bond pad, and a passive surface substantially coplanar with the second substrate surface. Substrate thickness and chip thickness may be substantially equal. Bonding elements bridge the gap to connect electrically bond pad and routing strip.

Abstract: A method for forming a metal wiring line, comprises: (a) forming a bank including a first opening corresponding to a first film pattern and a second opening corresponding to a second film pattern that is coupled to the first film pattern and has a width narrower than a width of the first film pattern; (b) disposing a droplet of a functional liquid in the first opening so as to dispose the functional liquid in the second opening by an autonomous flow of the functional liquid; (c) hardening the functional liquid disposed in the first opening and the second opening; and (d) forming the first film pattern and the second film pattern by alternately repeating step (b) and step (c) at least one time.

Abstract: The method of fabricating a semiconductor device according to the present invention is applied to a semiconductor device fabricated by forming a seed film in recesses formed in an interlayer film and forming a thick film embedded in the recesses by electrolytic plating using the seed film as an electrode. In this fabrication method, the maximum length of time until the electrolytic plating is started after the completion of the seed film is limited based on the formation of the seed film in the recesses. The maximum time is reduced as the recesses have higher aspect ratios, preventing a void from being formed in the recesses during the plating, thereby obtaining highly reliable wiring.

Abstract: A method for sealing an exposed surface of a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN/Ti or TiN/Al cap is used as a protective coating covering exposed surfaces of a wire bond pad. The TiN/Ti or TiN/Al cap is not affected by alkaline chemistries used in forming the Ni/Au metallization, yet it provides a sufficient electrical pathway connecting the bond pads to the Ni/Au pad metallization.

Abstract: A method for forming a wiring pattern according to an aspect of the invention forms a wiring pattern in a certain area on a substrate by using a droplet discharge technique, and includes forming a bank surrounding the certain area on the substrate; discharging a first functional liquid containing a material of the wiring pattern to an area surrounded by the bank to form a first wiring pattern; discharging a second functional liquid onto the first wiring pattern to form a second wiring pattern; and collectively baking the wiring pattern of a plurality of layers including the first wiring pattern and the second wiring pattern.

Abstract: The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO2. Alternatively, the via region of the interconnect structure may be strengthened with a mechanically rigid dielectric comprising SiO2, SiCOH, or doped silicate glass.

Abstract: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.

Abstract: A method for producing a semiconductor device that uses a silicone-based die bonding material with high heat resistance and a low elastic modulus is provide. The method includes the steps of: applying a heat-curable silicone-based die bonding material to a substrate, placing a semiconductor element on the coated surface of the substrate, heating and curing the heat-curable silicone-based die bonding material, removing low molecular weight siloxane components adhered to the semiconductor element, and subsequently conducting wire bonding. The adverse effects of low molecular weight siloxanes are suppressed, and highly reliable wire bonding is attained.

Abstract: This invention provides a wire bonding method, comprising providing an integrated circuit (IC) die having thereon a passivation layer and a plurality of first bonding pads exposed by respective openings in the passivation layer; forming a polymer layer on the passivation layer; forming an adhesive/barrier layer on the polymer layer; forming a metal pad layer on the adhesive/barrier layer; bonding a wire onto the metal pad layer to form a ball bond thereon; and after forming the ball bond on the metal pad layer, running the wire so as to contact the wire with a second bonding pad and forming a wedge bond thereto.

Abstract: Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any circuit of the die, i.e., “dummy” solder balls, and are used to temporarily hold the die in position with respect to the PCB until the circuit is wire bonded and an underfill material is cured between the die and the PCB to more permanently connect them together. The underfill material is selected to have a coefficient of thermal expansion (CTE) that is substantially equal to the CTE of the solder balls to prevent thermal mismatch problems. An overmolding compound is disposed about the die and the underfill material and about the wire bonds to complete the package. Various arrangements of the solder ball pads on the die include columnar and row, corner, diagonal, cross, and periphery arrangements.

Abstract: The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a first topographical region with a first elevational height and a second topographical region with a second elevational height above the first elevational height. The second topographical region can be laterally displaced from the bonding region by at least a lateral width of the first topographical region, with said lateral width being at least about 10 microns. Additionally, or alternatively, the elevational height of the second topographical region can be at least about 2 microns above the elevational height of the first topographical region.

Abstract: A wire loop comprises a wire connecting a first bonding point and a second bonding point therethrough, wherein the wire has a crushed part formed therein by crushing the part of the wire and a top of a ball bonded to the first bonding point with a capillary. The wire loop is formed by a wire bonding method which includes: bonding the wire to the first bonding point; moving the capillary horizontally and vertically while carrying out loop control; bonding the wire to the vicinity of the top of the ball bonded to the first bonding point; and thereafter, moving the capillary horizontally and vertically to the second bonding point while delivering the wire and carrying out loop control, and then bonding the wire to the second bonding point.

Abstract: The invention provides a transfer technique by which the dimensional precision of a thin-film device is not deteriorated, even if the device is produced by transferring a fine structure or a thin-film circuit layer onto a substrate with an inferior shape-stability. The method includes: forming a fine structure or a thin-film circuit layer on a first substrate using a photolithographic patterning process; shifting the fine structure or the thin-film circuit layer from the first substrate onto a second substrate, or shifting the fine structure or the thin-film circuit layer from the first substrate onto the second substrate via a third substrate; and forming a thin-film pattern on the fine structure or the thin-film circuit layer shifted onto the second substrate by a non-photolithographic method.