Abstract: A method and apparatus are discloses for wirebonding leads of a plurality of lead frames being part of a lead frame assembly by a wirebonding tool to semiconductor products mounted on the respective lead frames. The semiconductor products are clamped by a clamping mechanism comprising a stationary clamp and a movable clamp. The movable clamp follows the indexing movement of the lead frame assembly during wirebonding of the semiconductor products clamped by the movable clamp. The wirebonding process does not need to be interrupted for the indexing.

Abstract: A low cost method of forming solder bumps on an integrated circuit (IC) wafer includes depositing solder directly onto stud bumps formed on bond pads of the IC wafer. In some implementations, stud bumps are formed on the IC wafer by performing wire ball-bonding onto metal bond pads of the wafer. Photodefinable solder mask material is applied to the wafer and cured. The photodefinable solder mask material is exposed to form open solder mask areas at the metal bond pad areas. Solder paste is applied into the open solder mask areas. Reflowing the solder paste on the wafer forms solder bumps that wet to the stud bumps. The solder mask is then stripped from the wafer. Other processes (e.g., a wave-soldering machine, stencil or screen printing process) can also be used to wet solder onto stud bumps to form solder bumps.

Abstract: A substrate is electrically connected with an electrical device mounted on the substrate. A ball bond is formed between a first end of a wire and a bonding pad of the substrate. A reverse-motion loop is formed within the wire. A bond is formed between a second end of the wire and a bonding pad of the electrical device.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.

Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

Abstract: A semiconductor device (100A) with plastic encapsulation compound (102) and metal sheets (103a and 104) on both surfaces, acting as heat spreaders. One or more thermal conductors (103a) of preferably uniform height connect one sheet (103b) and the chip surface (101a); the number of conductors is scalable with the chip size. Each conductor consists of an elongated wire loop (preferably copper) with the wire ends attached to a pad (105), preferably both ends to the same pad. The major loop diameter is approximately normal to the first surface and the loop vertex in contact with the sheet (103b). The substrate (104, preferably a second metal sheet) covers at least portions of the second package surface and is thermally conductively connected to the chip.

Abstract: A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire.

Abstract: A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More specifically, each cross-sectional area of the electrode terminals is slightly larger than that of the element part. Therefore, an upper part and lower part of each electrode terminal are slightly higher than (project from) the element part. Through an adhesive, the passive component is fixed such that the element part is located on the high position part so as to be nearly parallel to a substrate surface. Further, a part of each electrode terminal (bottom part) is located in each space within concave parts. Thus, a predetermined space is formed between each of the electrode terminals and the die pad.

Abstract: A manufacturing process for chip package without core is disclosed. First of all, a conductive layer with a first surface and a second surface is provided. A first film is formed onto the first surface, and the conductive layer is patterned to form a patterned circuit layer. A solder resistance layer is formed on the patterned circuit layer and then patterned to expose parts of the patterned circuit layer. After a second film is formed on the solder resistance layer and the first film is removed, a chip is disposed on the first surface and electrically connected to the patterned circuit layer. A molding compound is formed to cover the patterned circuit layer and fix the chip onto the patterned circuit layer. After that, the second film is removed.

Abstract: A semiconductor package is made by providing a wafer having a first electrical contact pad integrated into a top surface of the wafer, forming a through-hole interconnection extending downward from a first surface of the first electrical contact pad, electrically connecting a die to a second surface of the first electrical contact pad, cutting the wafer to form a channel portion and a connecting portion, disposing an encapsulant over the die and the channel portion, backgrinding the wafer to remove the connecting portion and expose a surface of the through-hole interconnection, disposing a second electrical contact pad over the surface of the through-hole interconnection, disposing a dielectric layer along a side surface of the second electrical contact pad, and singulating the wafer into an individual segment containing the die. The dielectric layer is disposed to form a plurality of lands extending across a bottom surface of the semiconductor device.

Abstract: An interlayer insulating film is formed on a semiconductor substrate. An intra-layer insulating film is formed on the interlayer film. A recess is formed through the intra-layer film. The recess has a pad-part and a wiring-part continuous with the pad-part. The pad-part is wider than the width of the wiring-part. Convex regions are left in the pad-part. The convex regions are disposed in such a manner that a recess area ratio in a near wiring area superposed upon an extended area of the wiring-part into the pad-part, within a first frame area having as an outer periphery an outer periphery of the pad-part and having a first width, becomes larger than a recess area ratio in a second frame area having as an outer periphery an inner periphery of the first frame area and having a second width. A conductive film is filled in the recess.

Abstract: An object of the present invention is to provide a method of forming a light-emitting element at a lower cost than a conventional cost with suppressing the deterioration of the substrate due to thermal distortion in comparison with a conventional method of recycling a substrate and further having an effect equal to that of the method of recycling a substrate.

Abstract: A method of forming an identification code for wire bonders is revealed. Firstly, a chip with a plurality of bonding pads is provided and is disposed on a chip carrier with a plurality of bonding fingers. A binary-code baseline is defined on the chip carrier to divide each of the bonding fingers into a first coding area adjacent the bonding pads and a second coding area far away from the bonding pads. Then, a plurality of bonding wires are formed by wire bonding to electrically connect the bonding pads to the bonding fingers and an ID code for wire bonders is formed at the same time where each bonding wire has an end selectively bonded to either the first coding area or the second coding area of the corresponding bonding finger to form an ID code for wire bonders. Since the ID code for wire bonders is constituted by the selected locations of the ends of the bonding wires, the ID code do not get lost or damaged during packaging processes nor contaminate the packages.

Abstract: A method and apparatus for underfilling a gap between a semiconductor die or device and a substrate, where the semiconductor die or device is electrically connected to the substrate so that an active surface of the semiconductor die is facing a top surface of the substrate with the gap therebetween. A silane layer is applied to the active surface of the semiconductor die, the upper surface of the substrate, and/or both to increase the surface tension thereon. The increased surface tension thereby allows the underfill material to fill the gap via capillary action in a lesser flow time more effectively, and therefore, is more efficient than conventional underfilling methods.

Abstract: Provided are a semiconductor package and a method of forming a wire loop of the semiconductor package. The semiconductor package includes: at least one semiconductor chip; a lead frame including a plurality of leads; and a plurality of wire loops, the wire loops connecting an electrode pad of the semiconductor chip to the leads. Wire loops include: a ball connected to the electrode pad; a pressed part formed on an upper surface of the ball by pressing the wire to overlap two parts of the wire; a first wire part extending substantially horizontally from the pressed part and including at least a portion contacting an upper surface of the semiconductor chip; a second wire part extending at a downward incline from the first wire part; and a third wire part extending from the second wire part and including an end connected to one of the leads.

Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

Abstract: A method for manufacturing a wire sweep resistant semiconductor package provides a die attached to an interposer. The die is electrically connected to the interposer with conductive wires. A sealant is applied on the die at the conductive wires for preventing wire sweep and the sealant is free of contact with the interposer. The die, the interposer, the conductive wires, and the sealant are encapsulated in an encapsulant.

Abstract: A manufacturing method of a semiconductor device with a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip.

Abstract: The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a first topographical region with a first elevational height and a second topographical region with a second elevational height above the first elevational height. The second topographical region can be laterally displaced from the bonding region by at least a lateral width of the first topographical region, with said lateral width being at least about 10 microns. Additionally, or alternatively, the elevational height of the second topographical region can be at least about 2 microns above the elevational height of the first topographical region.

Abstract: In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.

Abstract: A method for assembling one or more semiconductor devices with an interposer includes positioning the one or more semiconductor devices within a receptacle that extends through the interposer, on a retention element that extends over at least a portion of the receptacle. Material may be introduced between at least a portion of an outer periphery of the one or more semiconductor devices and an inner periphery of the interposer to facilitate securing of the one or more semiconductor devices in place relative to the interposer. The retention element may be removed from the semiconductor devices. Once the one or more semiconductor devices are in place, they may be electrically connected to the interposer.

Abstract: A junction structure and a method of manufacturing the same are provided which can achieve stable wire bonding between a Poly-Si film bonding pad and an Al wire. The junction structure is made up of a SiO2 film 5 formed on Si 4, a BPSG film 6 formed on the SiO2 film 5, a SiN film 7 formed on the BPSG film 6, a Poly-Si film bonding pad 1 formed on the SiN film 7, and an Al wire 2 bonded on the Poly-Si film bonding pad 1. A pad surface average roughness 8 of the Poly-Si film bonding pad 1 can be reduced. Thus it is possible to reduce gaps between bonding surfaces of the Al wire 2 and the Poly-Si film bonding pad 1 and increase a bonding area, thereby improving wire bonding characteristics.

Abstract: A method of manufacturing a substrate joint body by mounting a TFT on a wiring substrate includes a step of arranging an electrode pad of the wiring substrate and an electrode pad of the TFT at a predetermined interval and mechanically coupling the wiring substrate and the TFT with a adhesive and a step of electrically coupling the wiring substrate and the TFT by growing a bump from the electrode pad of the wiring substrate and/or the electrode pad of the TFT.

Abstract: Methods of forming wire and solder bond structures are disclosed. In one embodiment, a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a protective layer over the wire bond metal region only; forming a silicon nitride layer over a silicon oxide layer over the wire bond metal region and the solder bond metal region; forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered; exposing the wire bond metal region including removing the protective layer; and forming the wire bond to the wire bond metal region. Wire bond and solder bond structures can be made accessible on a single multi-part wafer (MPW) wafer or on a single chip, if necessary.

Abstract: A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.

Abstract: A package substrate and a method for fabricating the same are provided according to the present invention. The package substrate includes: a substrate body with a die attaching side and a ball implanting side lying opposite each other, having a plurality of wire bonding pads and a plurality of solder ball pads respectively, and having a first insulating passivation layer and a second insulating passivation layer respectively, wherein a plurality of first apertures and a plurality of second apertures are formed in the first insulating passivation layer and the second insulation passivation layer respectively to corresponding expose the wire bonding pads and the solder ball pads; a chemical plating metal layer formed on the wire bonding pads and solder ball pads respectively; and a wire bonding metal layer formed on a surface of the chemical plating metal layer of the wire bonding metal layer.

Abstract: The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a first topographical region with a first elevational height and a second topographical region with a second elevational height above the first elevational height. The second topographical region can be laterally displaced from the bonding region by at least a lateral width of the first topographical region, with said lateral width being at least about 10 microns. Additionally, or alternatively, the elevational height of the second topographical region can be at least about 2 microns above the elevational height of the first topographical region.

Abstract: A method is disclosed of repairing wire bond damage on semiconductor chips such as high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices, particularly devices using low-K dielectric materials. The method involves surface modification using reactive liquids. In a preferred embodiment, the method comprises applying a silicon-containing liquid reagent precursor such as TEOS to the surface of the chip and allowing the liquid reagent to react with moisture to form a solid dielectric plug or film (50) to produce a barrier against moisture ingress, thereby enhancing the temperature/humidity/bias (THB) performance of such semiconductor devices.

Abstract: The invention discloses apparatus and methods for the formation of bond wires in integrated circuit assemblies by attaching two separate wires using a dual capillary bond head. The separate wires are preferably non-identical, for example, being of different gauges and/or material composition. According to a preferred embodiment of the invention, dual capillary bond head apparatus includes a rotatable ultrasonic horn with a pair of capillaries for selectably dispensing separate strands of bond wire and for forming bonds on bond targets. According to another aspect of the invention, a method is provided for dual capillary IC wirebonding including steps for using two dual capillary bond heads for contemporaneously attaching non-identical bond wires to selected bond targets on one or more IC package assemblies.

Abstract: A method of manufacturing a semiconductor device includes an improved bump forming process. The bump forming process includes a bump forming step for forming a bump on the pad by feeding a gold wire from a capillary while moving the capillary; a sliding step of slightly moving the capillary in an almost horizontal direction after the formation of the bump to reduce the strength of the base portion of the gold wire connected to the bump; and a wire cutting step of cutting the gold wire at the base portion after the sliding step. In the sliding step, a moving speed of the capillary is made smaller than that in the bump forming step.

Abstract: An integrated circuit includes active circuitry and at least one bond pad. The at least one bond pad, in turn, comprises a metallization layer and a capping layer having one or more grooves. The metallization layer is in electrical contact with at least a portion of the active circuitry. In addition, the capping layer is formed over at least a portion of the metallization layer and is in electrical contact with the metallization layer. The grooves in the capping layer may be located only proximate to the edges of the bond pad or may run throughout the bond pad depending on the application.

Abstract: A Ball Grid Array (BGA) integrated circuit package having (i) an additional dedicated ground ring on the package substrate which provides a reduced area return current loop path to reduce wire bond inductance; and/or (ii) ground wires positioned between adjacent input/output wires on the substrate which provide additional transient current paths among the input/output wires for improved characteristic impedance and cross talk control.

Abstract: A method of manufacturing a redistribution circuit structure is provided. First, a substrate is provided. The substrate has a plurality of pads and a passivation layer. The passivation layer has a plurality of first openings exposing a portion of each of the pads, respectively. A first patterned photoresist layer is formed on the passivation layer. The first patterned photoresist layer has a plurality of second openings exposing a portion of each of the pads. A plurality of first bumps is formed in the second openings, respectively. An under ball metal (UBM) material layer is formed over the substrate to cover the first patterned photoresist layer and the first bumps. A plurality of conductive lines is formed on the UBM material layer. The UBM material layer is patterned to form a plurality of UBM layers using the conductive lines as a mask.

Abstract: In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps to allow wire bonding and testing applications. Various post-passivation passive components may be formed on the integrated circuit and connected via the metal caps.

Abstract: A semiconductor device is provided which can prevent contacts between thin metal wires for electrically connecting the electrodes of a substrate with the electrodes of a semiconductor element. The semiconductor device of the present invention includes metal protrusions formed on the electrodes of the semiconductor element, the metal protrusions having lower hardness than the hardness of the thin metal wires. The metal protrusions are bonded to the thin metal wires.

Abstract: A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.

Abstract: A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the surface of the nickel cap, may be controlled. The phosphorous content of the surface of the nickel cap is suitably determined such that oxidation is inhibited. The resulting nickel cap may be wire-bonded directly, without the deposition of a gold cap layer.

Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up, wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice.

Abstract: A system and method is disclosed for increasing the strength of a bond made by a small diameter wire in ball bonding. In one embodiment of the invention a structure for receiving a ball bond comprises substrate material that has portions that form a substrate cavity and a wire bond pad that covers and fills the substrate cavity. The wire bond pad also has portions that form a wire bond cavity for receiving the ball bond. The ball is wirebonded to the sides and bottom of the wire bond cavity. The sides of the wire bond cavity provide additional strength to the bond to resist shear and tensile forces that may act on the wire.

Abstract: In order to prevent bonded wires from being damaged during another wire bonding in a semiconductor device, there is provided a wire bonding method for wire-connecting pads on a semiconductor chip and multiple leads corresponding to the pads in a semiconductor device to be manufactured by sealing the semiconductor chip and the leads together in one block, in which bumps and are formed with an ultrasonic vibration on all of the pads on the semiconductor chip and the leads included in the one block, and then wires are provided, with no ultrasonic vibration, for connection between the bumps and on the pads and the leads.

Abstract: A substrate is electrically connected with an electrical device mounted on the substrate. A ball bond is formed between a first end of a wire and a bonding pad of the substrate. A reverse-motion loop is formed within the wire. A bond is formed between a second end of the wire and a bonding pad of the electrical device.

Abstract: Provided is a semiconductor package, and a method for constructing the same, including a first substrate, a first semiconductor chip attached to the first substrate, and a first copper wire. At least one of the first substrate and the first semiconductor chip has an Organic Solderability Preservative (OSP) material coated on at least a portion of one surface, and the first copper wire is wire bonded through the OSP material to the first substrate and the first semiconductor chip.

Abstract: There is provided a method for manufacturing the semiconductor device for obtaining capacitance characteristics of a larger capacitance and delay characteristics with higher efficiency. An embodiment according to the present invention employs the configuration of forming the gate polysilicon layer by conducting the customization by using the customized reticle. For example, gate polysilicon layer having a larger dimension such as gate length and the like is formed by using the dedicated gate reticle, only for an user who requests the countermeasure for the EMI noise. Having such process, a larger-scale capacitance can be provided without increasing the process cost.

Abstract: A semiconductor chip is characterized by a structure including a semiconductor chip on which electrode pads are formed, bumps which are formed on the respective electrode pads and which have projection sections, an insulating layer formed on the semiconductor chip, and a conductive pattern to be connected to the bumps, wherein extremities of the projection sections are inserted into the conductive pattern and the inserted extremities are flattened.

Abstract: A method for performing a wire-bonding operation in an integrated circuit utilizes a bonding tool. A wire is bonded to a first bond site in the integrated circuit, and terminated at a second bond site in the integrated circuit. The bonding and terminating steps are repeated for a plurality of additional wire bonds of the integrated circuit. At least two wire bonds in the integrated circuit are substantially perpendicular to one another at a crossing point in a plan view of the integrated circuit.

Abstract: The semiconductor component has several regularly arranged active cells (1), each comprising at least one main defining line (8). A bonding wire (18, 20) is fixed to at least one bonding surface (14, 16) by bonding with a bonding tool, oscillating in a main oscillation direction (22, 24), for external electrical contacting. The bonding surfaces (14, 16) are of such a size and oriented such that the main oscillation direction (22, 24) runs at an angle (?), with a difference of 90° to the main defining line (8).

Abstract: There are provided the steps of connecting a chip component 13 to a first substrate 10 through wire bonding, providing, on a second substrate 20, an electrode 21 having a solder coat 23 coated with a copper core 22, polishing a portion of the electrode 21 which is to be bonded to the connecting pad 12, thereby exposing the copper core 22 from the solder coat 23, bonding the exposed portion of the copper core 22 to the bump connecting pad 12 by using a flux non-containing conductive paste 30, thereby bonding the substrates 10 and 20 to each other, and filling a sealing resin 40 in a clearance portion between the substrates 10 and 20.

Abstract: A method is provided for creating a compound bond in a wire bonding process. The method includes forming a free air ball (804) at a first end (702) of a bonding wire (602). The method also includes determining a dimension and/or a shape of an anchored ball (406) disposed on a bonding site. The method further includes modifying a shape of the free air ball to at least partially conform to a shape of the anchored ball. This modification step also comprises modifying the shape of the free air ball in accordance with at least one of the dimension and the shape of the anchored ball. This modification step further comprises forming a concave surface (1502) on a portion of the free air ball. The method further includes bonding the free air ball to the anchored ball subsequent to modifying a shape of the free air ball.

Abstract: A semiconductor device of the present invention includes a chip which has a pad; a bump electrode formed on the pad; and a wire whose stitch bonding is made on the bump electrode. The wire satisfies a condition: (modulus-of-elasticity/breaking strength per unit area) ?400.

Abstract: According to various exemplary embodiments, a spring device that includes a substrate, a self-releasing layer provided over the substrate and a stressed-metal layer provided over the self-releasing layer is disclosed, wherein an amount of stress inside the stressed-metal layer results in a peeling force that is higher than an adhesion force between the self-releasing layer and the stressed-metal layer. Moreover, a method of manufacturing a spring device, according to various exemplary embodiments, includes providing a substrate, providing a self-releasing layer over the substrate and providing a stressed-metal layer over the self-releasing layer wherein an amount of stress inside the stressed-metal layer results in a peeling force that is higher than an adhesion force between the self-releasing layer and the stressed-metal layer is also disclosed in this invention.