Abstract: A new method of forming controlled voids within the intermetal dielectric and within the passivation layer of an integrated circuit is achieved. A first layer of patterned metallization is provided over semiconductor device structures in and on a semiconductor substrate. An intermetal dielectric layer is deposited overlying the first patterned metal layer wherein the thickness of the intermetal dielectric layer is large enough so as to cause the formation of voids within the intermetal dielectric and wherein said voids are completely covered by said intermetal dielectric. A second layer of metallization is deposited over the intermetal dielectric and patterned. A passivation layer is deposited overlying the second patterned metal layer. The thickness of the passivation layer is large enough so as to cause the formation of voids within the passivation layer wherein said voids are completely covered by said passivation layer.

Abstract: A method for making micromachined structures that includes pinpoint polysilicon bumps for eliminating the stiction problem associated with elements of the micromachined structure, such as movable or fixed beams. The pinpoint polysilicon bumps provide a reduced contact area for the beam which reduces the chances that there will be a stiction problem due to static or surface charge. The method takes advantage of an edge alignment technique to achieve a geometry for pinpoint bump structures of as low as 0.20 .mu.m. The bump structures are located in a region of the movable and fixed beams at the edge adjacent the gaps between the interleaved fingers. The method forms bump structures that have a circular design. The formation of the bump structures is carefully controlled with respect to the overlap of these bump structures into interdigitated structures.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: A method of manufacturing a conductive micro bridge includes the steps of preparing a semiconductor substrate, forming an insulating film on the semiconductor substrate, forming a sacrificial layer on the insulating film, forming a metal-oxide composite film on the sacrificial layer so as to surround the sacrificial layer, and removing the sacrificial layer to thereby form an air gap in the removed portion.

Abstract: A method and structure for reducing capacitance between interconnect lines (11, 24, 26) utilizes air gaps (17, 47) between the interconnect lines (11, 24, 26). Deposited over the interconnect lines (11, 24, 26), a silane oxide layer (14) forms a "breadloaf" shape which can be sputter etched to seal the air gaps (17, 47). Prior to the deposition of the sputter etched silane oxide layer (14), spacers (13, 42, 43) can be formed around the interconnect lines (11, 24, 26) to increase the aspect ratio of gaps (23, 31) between the interconnect lines (11, 24, 26) which facilitates the formation of the "breadloaf" shape of the silane oxide layer (14).

Abstract: A method of using layers of gold metallization and a thick film coating of photo-sensitive material to form an air-filled microwave waveguide structure on the outer surface of a semiconductor body, such as a monolithic microwave integrated circuit commonly referred to as an MMIC, so that the waveguide can be coupled to the active and passive devices of the MMIC. First, a patterned metallization layer is formed on a substrate. A mold of a waveguide is fabricated by masking and then etching another metallization layer. The mold is turned over face down on the patterned metallization layer and bonded to the patterned metallization layer, Then, any unnecessary material is etched away.

Abstract: A fabrication process for vacuum microelectronic devices having multiple electrode levels includes production of a first-level electrode mask on a substrate. The mask pattern is transferred to the substrate to produce a trench surrounding an emitter which is formed by thermal oxidation. The trench is filled with tungsten to form a gate electrode surrounding the emitter, and the resulting wafer is planarized. A second-level electrode is formed on the top surface of the wafer, and is planarized. Additional levels are similarly produced, and thereafter the electrodes are released.