Abstract: An object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device which can improve the flatness after the chemical mechanical polishing by inserting necessary and minimum dummy patterns and has high throughput.

Abstract: An interconnect structure has a substrate having devices already formed thereon. A dielectric layer covers over the substrate. A conductive structure having at least two substructure separated by an air gap is formed on the dielectric layer. A capping layer covers the conductive structure and the air gap. The capping layer at a portion above the air gap also fills into the air gap by a predetermined distance. The air gap may also extend into the dielectric layer to have a greater height. An etching stop layer is formed on the capping layer. An inter-metal dielectric layer is formed on the etching stop layer. The inter-metal dielectric layer, the etching stop layer and the capping layer are patterned to form an opening that exposes a top surface of the conductive structure.

Abstract: A semiconductor device is fabricated first by thermocompression-bonding a silicon oxide film onto a plurality of conductive films under vacuum using a film having the silicon oxide film formed thereon and then by separating the base film from the silicon oxide film. During the separation, the base film, being composed of a fluorine-containing resin, has smaller surface energy than a silicon oxide film and thus is easy to separate, leaving the silicon oxide film on the conductive films. As a result, the silicon oxide film is adhered on the conductive films so as to cover the conductive films, and an air gap is hence provided between the conductive films. Thus, a highly reliable semiconductor device capable of high-speed-operation is provided by controlling parasitic capacitances between interconnections arranged accurately and adequately adjacent to each other so that recent needs for further miniaturization and higher integration of semiconductor elements can be met.

Abstract: An integrated circuit having at least one electrical interconnect for connecting at least two components and a process for forming the same are disclosed.

Abstract: A method for forming at least one conductive line intended to receive high-frequency or high-value currents, formed above a given portion of a solid substrate outside of which are formed other elements, including the steps of digging at least one trench in the solid substrate; forming an insulating area in the trench; and forming said conductive line above the insulating area.

Abstract: A method for forming an conductive interconnection in an electronic semiconductor device includes forming a layer of insulating material on a substrate of semiconductor material having a contact region therein, and forming a first opening through the layer of insulating material to expose the contact region. The first opening is filled with a material to form a first connection element. A first layer comprising a first removable conductive material is formed adjacent the layer of insulating material and the first connection element. The method further includes forming a second opening in the first layer to expose the first connection element, and filling the second opening with the material to form a second connection element. The first removable conductive material is removed except for a portion underlying the second connection element to expose the layer of insulating material. The areas left free after removing the first removable conductive material are filled with a dielectric material.

Abstract: An electrical isolation method for silicon microelectromechanical systems provides trenches filled with insulation layers that support released silicon structures. The insulation layer that fills the trenches passes through the middle portion of the electrodes, anchors the electrodes to the silicon substrate and supports the electrode. The insulation layers do not attach the electrode to the sidewalls of the substrate, thereby forming an electrode having an “island” shape. Such an electrode is spaced far apart from the adjacent walls of the silicon substrate providing a small parasitic capacitance for the resulting structure. The isolation method is consistent with fabricating a complex structure or a structure with a complicated electrode arrangement. Furthermore, the structure and the electrode are separated from the silicon substrate in a single release step.

Abstract: The present invention provides a high-Q inductance device and a method for fabricating the same. The inductance device is formed on a semiconductor substrate and includes at least one spiral conducting line and a passivation layer formed above the spiral conducting line, the passivation layer including a spiral air gap formed within the space around the spiral conducting line. By means of the at least one spiral conducting line, the resistance of the inductance device can be decreased. Moreover, the parasitic capacitance can be decreased by means of the air gap with a low dielectric constant. Therefore, the Q value of the inductance device of the present invention can be effectively increased.

Abstract: A sealing film is formed on a semiconductor substrate on which a number of columnar electrodes are formed, and then the upper surface of the sealing film is polished to expose the upper surfaces of the columnar electrodes made of a soft metal. During the polishing, laterally broadened edges are generated on the upper sides of the columnar electrodes. Then, the upper surfaces of the columnar electrodes, including the laterally broadened edges, are etched so as to remove the edges. In this manner, the shape of the upper surfaces of the columnar electrodes can be formed as initially designed, and therefore the bonding strengths can be made uniform. Thus, the reliability of the device can be improved.

Abstract: A protective pattern is formed on a semiconductor substrate in a shape covering a circuit region and exposing an air bridge connecting portion, a metallic film and an insulating film are formed to cover the protective pattern, the metallic film and the insulating film are patterned to form air bridge wiring and an air bridge protective film covering the air bridge wiring, and thereafter, the protective pattern is removed to form a hollow between the air bridge wiring and the circuit region.

Abstract: A semiconductor device and an improved method for making it are described. The semiconductor device comprises a dual damascene interconnect that includes a conductive line. The device further includes a support structure that is spaced from the conductive line, and an insulating layer that is formed on the support structure and the conductive line. In the method for forming that device, a support structure is formed on a substrate, and an insulating layer is formed adjacent to it. Portions of the insulating layer are removed to form a via and a trench, which are filled with a conductive material to generate a dual damascene interconnect that includes a conductive line, wherein the conductive line is spaced from the support structure.

Abstract: Conductive structures and methods for preparing conductive structures are provided. Conductive structures according to the present invention can be prepared by controllably deforming and shaping a metal layer by using a hydrogen gas source and thermally treating the hydrogen gas source.

Abstract: A method of forming a semiconductor device having reduced interconnect-line parasitic capacitance is provided. The method includes the following steps. First, a substrate is provided and a plurality of interconnect lines are formed on the substrate. A barrier layer is then formed. Next, the barrier layer is hardened and thinned so as to make the barrier layer having a thin-film attribute. Following that, a separation layer is formed by filling the space between and above the interconnect lines with a dielectric. Then, the dielectric is foamed. After that, an insulating layer is formed. Finally, the dielectric is condensed such that air gaps are formed in the separation layer.

Abstract: A power electronics module has a metal substrate, a printed circuit card carried on one of the faces of the substrate, and components, at least some of which are power components, mounted on the card. The card also carries electrical interconnection tracks between the components themselves and with external power supply. Conductive bridges of a shape enabling each of them to extend over a power component mutually interconnect short segments of interconnection tracks, that carry power current.

Abstract: One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.

Abstract: A semiconductor device and an improved method for making it are described. The semiconductor device comprises a dual damascene interconnect that includes a conductive line. The device further includes a support structure that is spaced from the conductive line, and an insulating layer that is formed on the support structure and the conductive line. In the method for forming that device, a support structure is formed on a substrate, and an insulating layer is formed adjacent to it. Portions of the insulating layer are removed to form a via and a trench, which are filled with a conductive material to generate a dual damascene interconnect that includes a conductive line, wherein the conductive line is spaced from the support structure.

Abstract: In a method for forming a semiconductor device, when polishing the wafer, the photo-resin so as to cure with ultraviolet is buried. Then, after polishing and forming the back side electrode, the photo-resin is removed by organic solvent. Accordingly, the method can improve reliability of bonding and simplify process flow without decreasing electrical characteristics.

Abstract: Air gap insulation regions are formed selectively within high parasitic capacitance regions in which conductive lines are closely proximate and generates an intolerable amount of parasitic capacitance. The selective formation of air gap insulation regions improves circuit performance by reducing the parasitic capacitance and device reliability by reducing the stress fracture problem of conventional air gap insulation schemes.

Abstract: A method for making a layout for an interconnect layer of a semiconductor device to facilitate uniformity of planarization during manufacture of the semiconductor device includes determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout. The method further includes adding dummy fill features to each layout region to obtain a desire density of active interconnect features and dummy fill features to facilitate uniformity of planarization during manufacturing of the semiconductor device. By adding dummy fill features to obtain a desired density of active interconnect features and dummy fill features, dummy fill features are not unnecessarily added, and each layout region has a uniform density.

Abstract: A method for reducing the coupling capacitance between adjacent electrically conductive interconnect lines of an integrated circuit. An electrically conductive layer is deposited and etched to produce electrically conductive interconnect lines having negatively sloped sidewalls. An insulating layer is deposited on the electrically conductive interconnect lines using a directional deposition to create a void between and directly adjacent electrically conductive interconnect lines. The void has a substantially lower dielectric constant than the material of the insulating layer, which reduces the coupling capacitance between adjacent electrically conductive interconnect lines.

Abstract: Highly porous, low-k dielectric materials are mechanically reinforced to enable the use of these low-k materials as intralayer and interlayer dielectrics in advanced integrated circuits such as those which incorporate highly porous materials in a Cu damascene interconnect technology. An integrated circuit, embodying such a mechanically reinforced dielectric layer generally includes a substrate having interconnected electrical elements therein, a copper-diffusion barrier or etch stop layer disposed over the substrate, the copper-diffusion barrier or etch stop layer being patterned so as to provide a plurality of electrically insulating structures, and a low-k dielectric layer disposed around the plurality of structures.

Abstract: Structures and methods are provided for an improved multilevel wiring interconnect in an integrated circuit assembly. The present invention provides for a multilayer copper wiring structure by electroless, selectively deposited copper in a streamlined process which further reduces both intra-level line to line capacitance and the inter-level capacitance. In particular, an illustrative embodiment of the present invention includes a novel methodology for forming multilevel wiring interconnects in an integrated circuit assembly. The method includes forming a number of multilayer metal lines, e.g. copper lines formed by selective electroless plating, separated by air gaps above a substrate. A low dielectric constant material is deposited between the number of metal lines and the substrate using a directional process. According to the teachings of the present invention, using a directional process includes maintaining a number of air gaps in the low dielectric constant material.

Abstract: A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics.

Abstract: A method for forming a structure. A first dielectric material is deposited on a substrate. The first dielectric material is patterned. At least one metal is deposited in and on the first dielectric material. Portions of the at least one metal are removed at least in a region above an upper surface of the first dielectric material. The first dielectric material is removed. A second dielectric material is provided in place of first dielectric material.

Abstract: A method for interconnecting high-temperature silicon carbide (SiC) devices enables such high-temperature devices to be used in fabricating electronic circuits of significant scale. This method comprises empirically measuring operational characteristics of a plurality of the devices to be interconnected, the operational characteristics comprising devices which are measured to be non-working and devices which are measured to be working; characterizing the operational characteristics in an operational characteristics map; designing interconnection paths between and among the devices that are characterized to be working by the operational characteristics map; and excluding from the interconnection paths, devices that are characterized to be non-working by the operational characteristics map.

Abstract: A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.

Abstract: A fabrication of a damascene structure is described. A substrate having a first conductive layer formed thereon is provided. A silicon nitride type of first dielectric layer is formed on the substrate, followed by patterning the first dielectric layer to form a trench like structure. A silicon oxide type of second dielectric layer is then formed on the first dielectric layer and in the trench like structure and an air-gap is concurrently formed in the second dielectric layer that is in the trench like structure. Thereafter, the second dielectric layer is planarized until a surface of the first dielectric layer is exposed. The first dielectric layer is then removed to form a trench, followed by filling the trench with a second conductive layer.

Abstract: A process for reducing device capacitance via inclusion of an air gap in a low dielectric constant (low k), layer, used to fill narrow spaces between metal lines, has been developed. The process features the formation of dual damascene metal lines, comprised with a narrow space between the top portions of the dual damascene metal structures, and a wider space between bottom portions of these same structures. Deposition of a low k layer, using a deposition procedure lacking acceptable conformality properties, results in the narrow space between top portions of the dual damascene metal structures being completely filled with low k layer, while the wider space located between bottom portions of the metal structures remains unfilled. The unfilled portion of the low k layer now features an embedded air gap, resulting in decreased capacitance for the dielectric layer located between metal lines, thus reducing performance degrading RC delays.

Abstract: The semiconductor structure has an interconnect that is isolated by a cavity from an underlying insulating layer on a support. The fabrication method provides for the interconnect firstly to be patterned on a double layer and to be provided with an insulating covering. Then, an opening is etched into the insulating covering, and the lower conductive layer is selectively removed. As a result, one the one hand, low-capacitance wiring can be fabricated and, on the other hand, this enables MOS transistors to be programmed in a simple manner.

Abstract: In one aspect, the invention includes a method of forming a void region associated with a substrate, comprising: a) providing a substrate; b) forming a sacrificial mass over the substrate; c) subjecting the mass to hydrogen to convert a component of the mass to a volatile form; and d) volatilizing the volatile form of the component from the mass to leave a void region associated with the substrate.

Abstract: A process for forming air gaps within an interlayer dielectric is provided to reduce loading capacitance between interconnections. A first dielectric layer is deposited on the spaced interconnections. This first dielectric layer is deposited more thickly at the top sides than at the bottom sides of the interconnections. A second dielectric layer is deposited on the first dielectric layer to a controlled thickness that causes formation of air gaps therewithin between the interconnections. The poor step coverage of the first dielectric layer makes it easier to form the air gaps. Air gaps between interconnections allows reduced permittivity of the overall dielectric structures and thereby reduces the interconnect line to line capacitance, and increases the possible operation speed of the semiconductor device.

Abstract: The invented method produces a silicide region on a silicon body that is useful for a variety of purposes, including the reduction of the electrical contact resistance to the silicon body or an integrated electronic device formed thereon. The invented method includes a step of producing an amorphous region on the silicon body using ion implantation, for example, a step of forming a metal layer such as titanium, cobalt or nickel in contact with the amorphous region, and a step of irradiating the metal with intense light from a source such as a laser, to cause metal atoms to diffuse into the amorphous region to form an alloy region with a silicide composition. In an application of the invented method to the manufacture of a MISFET device, the metal layer is preferably formed with a thickness that is at least sufficient to produce a stoichiometric proportion of metal and silicon atoms in the amorphous region of the gate of the MISFET device.

Abstract: A method of manufacturing semiconductors is provided which avoids metal deposition in voids formed in the dielectric between interconnects. In a preferred embodiment, an etch stop recess portion is provided over the dielectric which encloses the interconnects to prevent via openings from extending into the voids during the etching of the via openings. Accordingly, metal deposition of the voids during metal deposition of the vias is avoided. As a result, the semiconductors so formed has reduced capacitance between the interconnects and improved reliability since the voids are cleared of any metal deposition.

Abstract: A method of manufacturing a metallization scheme with an air gap formed by vaporizing a filler polymer material. The filler material is covered by a critical permeable dielectric layer. The method begins by forming spaced conductive lines over a semiconductor structure. The spaced conductive lines have top surfaces. A filler material is formed over the spaced conductive lines and the semiconductor structure. The filler material is preferably comprised of a material selected from the group consisting of polypropylene glycol (PPG), polybutadine (PB) polyethylene glycol (PEG), fluorinated amorphous carbon and polycaprolactone diol (PCL) and is formed by a spin on process or a CVD process. We etch back the filler material to expose the top surfaces of the spaced conductive lines. Next, the semiconductor structure is loaded into a HDPCVD chamber. In a critical step, a permeable dielectric layer is formed over the filler material.

Abstract: After depositing a metal film on an insulating film on a semiconductor substrate, a first interlayer insulating film is formed on the metal film. After forming first plug openings in the first interlayer insulating film by etching the first interlayer insulating film with a first mask pattern used as a mask, first connection plugs are formed by filling a first conducting film in the first plug openings. A second interlayer insulating film is formed on the first interlayer insulating film. After forming second plug openings respectively on the first connection plugs in the second interlayer insulating film by etching the second interlayer insulating film with a second mask pattern used as a mask, second connection plugs are formed by filling a second conducting film in the second plug openings.

Abstract: An interlayer insulation film has a void that minimally has a height that extends from a position that is above the upper surface of wiring to a position that is below the lower surface of wiring, the side wall of this void being linear at an angle in the range from 80 to 100 degrees with respect to the substrate.

Abstract: A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary to produce air gaps during CVD of the dielectric. Air gaps exist between interconnects to reduce the line-to-line capacitance, and thereby reduce the propagation delay associated with closely spaced interconnects.

Abstract: Insulating layers between transistors that are very close together may have voids. When contacts are formed in these areas between these close transistors, the contact hole is formed at the void location. These voids may extend between the contact locations that are close together so that the deposition of the conductive material into these contact holes may extend sufficiently into the void to short two such contacts. This is prevented by placing a liner in the contact hole, which constricts the void size in the contact hole, prior to depositing the conductive material. This restricts ingress of conductive material into the void. This prevents the void from being an unwanted conduction path between two contacts that are in close proximity. The bottoms of the contact holes are etched to remove the liner prior to depositing the conductive material.

Abstract: A semiconductor device has an air-gap/multi-level interconnection structure. The interconnects are insulated from one another by an air gap in the same layer, and by an interlevel dielectric film between layers and from a semiconductor substrate. A high-speed semiconductor device is obtained due to a lower parasitic capacitance.

Abstract: An integrated circuit having at least one electrical interconnect for connecting at least two components and a process for forming the same are disclosed. The integrated circuit comprises: a substrate, a plurality of adjacent conductive strips, a layer of dielectric material, and a conductive material. The has a surface and the plurality of adjacent conductive strips is disposed on the substrate surface with each adjacent conductive strip having a length. The layer of dielectric material is deposited over the substrate surface and over and around the plurality of adjacent conductive strips to form at least two opposing, contoured, merging dielectric surfaces, each of which overhangs the substrate surface located between at least two of the plurality of adjacent conductive strips. The at least two opposing, contoured, merging dielectric surfaces define at least one elongated passageway which has at least one opening and is substantially encased therein and which extends along the length.

Abstract: The invention proposes methods for producing integrated circuits wherein the dielectric constant between closely spaced and adjacent metal lines is approaching 1. One method of the invention uses low-melting-point dielectric to form a barrier form a void between conductive lines. Another method of the invention uses sidewall film to form a similar barrier.

Abstract: A multilevel interconnect structure is formed which uses air as a dielectric between wiring lines and which is compatible with the presence of unlanded vias in the interconnect structure. A layer of carbon is deposited over an insulating surface and then a pattern for trenches is formed in the surface of the layer of carbon. Metal is deposited in the trenches and over the layer of carbon and then a chemical mechanical polishing process is used to define wiring lines. An ashing or etch back process is performed on the carbon layer to recess its surface below the surfaces of the wiring lines. An oxide capping layer is provided over the recessed surface of the carbon and the wiring lines, for example using HSQ and curing, and then the carbon layer is consumed through the capping layer using an oxidation process. Air replaces the sacrificial carbon layer during the consumption reaction.

Abstract: A multilayer structure is provided which suppresses hillock formation due to post-heat treatment steps in thin aluminum films deposited on other substrates by sandwiching the aluminum film between thin layers of aluminum titanium nitride. The first aluminum titanium nitride layer acts as a compatibilizing layer to provide a better match between the coefficients of thermal expansion of the substrate and aluminum metal layer. The second aluminum titanium nitride layer acts as a cap layer to suppress hillock formation.

Abstract: An improved microelectronic structure is disclosed. The improved structure includes an air-gap region formed by removing an insulating material through an aperture residing in a mask.

Abstract: A process for forming air gaps within an interlayer dielectric is provided to reduce loading capacitance between interconnections. A first dielectric layer is deposited on the spaced interconnections. This first dielectric layer is deposited more thickly at the top sides than at the bottom sides of the interconnections. A second dielectric layer is deposited on the first dielectric layer to a controlled thickness that causes formation of air gaps therewithin between the interconnections. The poor step coverage of the first dielectric layer makes it easier to form the air gaps. Air gaps between interconnections allows reduced permittivity of the overall dielectric structures and thereby reduces the interconnect line to line capacitance, and increases the possible operation speed of the semiconductor device.

Abstract: An outer air spacer structure, applicable to multilevel interconnects technologies, and the method of making the same are disclosed. The outer air spacer is adjacent to a metal line to provide a lower dielectric constant in a metal interconnect structure. The outer air spacer is formed by initially forming a first spacer adjacent to the metal line, followed by forming a second spacer on the first spacer. The first spacer is then removed to form an air gap between the second spacer and the metal line. The air gap is closed to form the outer air spacer by partially sealing the air gap with a portion of passivation layer that is deposited subsequently.

Abstract: A vertical spark gap assembly for electronic circuits employing poly silicon. The assembly permits dissipation of higher voltages in spark discharge without shorting in the circuit. The spark gap assembly includes a first partially conductive layer and a second partially conductive layer and a non-conductive material positioned between the layers and maintaining a vertically spaced apart relationship therebetween. At least one opening is provided in the first layer and the second layer with the non-conductive material removed from the layer having at least one opening. As such, the arrangement provides a vertical gap formed between and communicating with each layer.

Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes providing a substrate having metallic lines thereon. A high molecular weight sacrificial film is formed over the substrate. A portion of the high molecular weight sacrificial layer is removed to form spacers. A dielectric layer is formed over the substrate, the top surface of the metallic lines and the spacers. Finally, a thermal dissociation operation is conducted to remove the spacers, thereby forming an air pocket on each sidewall of the metallic lines.

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components.

Abstract: A method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.