Abstract: A new method of preventing passivation keyhole damage and resist extrusion using a hydrophillic solvent before photoresist coating is described. Semiconductor device structures are formed in and on a semiconductor substrate and covered by an insulating layer. Metal lines are formed overlying the insulating layer wherein there is a gap between two of the metal lines. A passivation layer is deposited overlying the metal lines wherein the gap is not filled completely by the passivation layer. The passivation layer is coated with a hydrophillic solvent wherein the hydrophillic solvent completely fills the gap. The passivation layer is coated with a photoresist layer which is exposed and developed to form a photoresist mask. The hydrophillic solvent completely filling the gap allows a uniform thickness photoresist layer. The passivation layer is etched away where it is not covered by the photoresist mask where a bonding pad is formed.

Abstract: A low dielectric constant material and a process for controllably reducing the dielectric constant of a layer of such material is provided and comprises the step of exposing the layer of dielectric material to a concentration of an oxygen plasma at a temperature and a pressure sufficient for the oxygen plasma to etch the layer of dielectric material to form voids in the layer of dielectric material. The process may also include the step of controlling the reduction of the dielectric constant by controlling the size and density of the voids. The size and density of the voids can be controlled by varying the pressure under which the reaction takes place, by varying the temperature at which the reaction takes place, by varying the concentration of the oxygen plasma used in the reaction or by varying a combination of these parameters. The process of the present invention is particularly useful in the fabrication of semiconductor devices.

Abstract: A method for manufacturing integrated circuits increases the aspect ratio of the electrical conductor members connected to the circuits by increasing the effective height of the conductors, either by forming a thicker layer of conductor material prior to patterning the conductor members, or by adding a capping dielectric layer to the conductor material prior to patterning, or by overetching the dielectric material underlying the conductor members.The structure is then covered by a dielectric layer having poor step coverage, resulting in a number of voids and open spaces in the dielectric layer to thereby reduce the dielectric constant between the patterned conductors. A plasma etchback of the dielectric layer is employed to open and shape additional voids and open spaces in the dielectric layer. This is followed by the deposition of a second layer of dielectric material to seal the structure, including any open spaces in the first layer of dielectric material.

Abstract: A method for forming a semiconductor device having air regions, the method comprises providing a base, forming a pattern of metal leads, depositing a layer of oxide over the metal leads, forming a layer of nitride over said layer of oxide, opening and etching a trench down to the base layer of material, and depositing and planarizing a dielectric layer. An alternate approach teaches the deposition of a layer of SOG over the layer of oxide that has been deposited over the metal leads, planarizing this layer of SOG down to the top of the metal leads, depositing a layer of PECVD oxide, patterning and etching this layer of PECVD oxide thereby creating openings that are in between the metal leads. The SOG that is between the metal leads can be removed thereby creating air gaps as the intra-level dielectric for the metal leads.

Abstract: The present invention is directed to a semiconductor device having a reduced feature size and a method of making same. The device is comprised of a gate dielectric positioned above a semiconducting substrate, and a gate conductor positioned above said gate dielectric. The width of the gate dielectric being less than the width of the gate conductor. The device further comprises a plurality of sidewall spacers adjacent said conductor. The method is comprised of forming a gate dielectric above the surface of a semiconducting substrate, forming a gate conductor above the gate dielectric, and wet etching the gate dielectric to a finished width that is less than the width of the gate conductor.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. Trench digging is time consuming and costly. Accordingly, the invention provides a new "trench-less" or "self-planarizing" method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance.

Abstract: Conductive structures and methods for preparing conductive structures are provided. Conductive structures according to the present invention can be prepared by controllably deforming and shaping a metal layer by using a hydrogen gas source and thermally treating the hydrogen gas source.

Abstract: The present invention provides a method of forming a semiconductor device. The method comprises the following steps. At least a first opening and at least a second opening are concurrently formed in a dielectric layer which has a bottom portion having first level interconnections so that the first and second openings have a bottom level which lies over the first level interconnections. A dielectric film is deposited over the dielectric layer to form an inter-layer insulator so that top portions of the first and second openings are sealed with the dielectric film so as to form at least a first hollow portion and at least a second hollow portion serving as an air gap.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as gold. Accordingly, the invention provides a new "self-trenching" or "self-planarizing" method of making coplanar gold wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts gold with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with gold to form gold wires coplanar with the first layer.

Abstract: A method of forming local interconnects uses a dual damascene process. The process comprises the steps of first providing a substrate, and then forming a first insulating layer over the substrate. Then, a pillar-shaped second insulating layer is formed over the first insulating layer. Thereafter, a first conductive layer is formed over the first insulating layer and the second insulating layer, and then a third insulating layer is formed over the first conductive layer. In the subsequent step, a portion of the third insulating layer and the first conductive layer is polished away using a chemical-mechanical polishing operation, stopping at the surface of the second insulating layer. Next, a fourth insulating layer is formed over the third insulating layer, the second insulating layer and the first conductive layer, wherein the fourth insulating layer and the second insulating layer are made from the same material.

Abstract: A semiconductor device manufacturing method is provided which can reduce the capacitance between adjacent wires by providing a void between wires, without sacrificing the advantage of the buried wiring method. After successively depositing an interlayer insulation film, a silicon nitride film, and a silicon dioxide film onto a silicon substrate, a wiring groove is formed. Then, after forming a contact hole, a barrier metal and aluminum film are deposited over the entire surface, these being removed from areas other than within the groove, so as to form buried wiring patterns. Then, the silicon dioxide film and silicon nitride films are etched away from areas in which the adjacent wiring space is narrow, thereby exposing the above-noted wiring pattern, after which a second silicon dioxide film is deposited over the entire surface, thereby forming a void in the area in which there is a narrow wiring space between adjacent wires.

Abstract: A low-dielectric constant insulation structure is described in which low-dielectric constant insulation layers and silicon oxide layers are alternately stacked on the substrate to form a stacked insulation layer. A required pattern is then etched in the stacked insulation layer followed by a selective etching to remove a portion of the low dielectric insulation layer to form, starting from the sidewall of the stacked insulation layer and extending inwardly, a plurality of recessed regions. A sputtering deposition and etching-back are further conducted on the sidewall of the stacked insulation layer to form a sidewall spacer to enclose the already formed recessed regions. A plurality of air-gaps is formed in the stacked insulation layer to establish a low dielectric insulation structure.

Abstract: The invention proposes methods for producing integrated circuits wherein the dielectric constant between closely spaced and adjacent metal lines is approaching 1. One method of the invention uses low-melting-point dielectric to form a barrier forming a void between conductive lines. Another method of the invention uses sidewall film to form a similar barrier.

Abstract: A method for fabricating a multilevel interconnect, where a first and a second conducting wires are formed respectively on a substrate, while a part of the substrate between the first and the second conducting wires is exposed. A first dielectric layer is then formed to cover the substrate as well as the first and the second conducting wires, wherein the first dielectric layer has an air gap formed between the first and the second conducting wires. An anti-etch layer is formed on the first dielectric layer above the air gap, while a second dielectric layer is then formed on the anti-etch layer and the first dielectric layer. A via opening which exposes the first conducting wire is then formed by etching, followed by forming a barrier layer which covers the profile of the via opening and the exposed surface of the first conducting layer. Consequently, a via plug is formed to fill the via opening.

Abstract: A bridge structure, such as an air bridge, includes a bridge element formed of an alloy including aluminum, copper, and lithium. The alloy may also further include silicon and the amount of lithium of the alloy is generally greater than about 1.0% by weight up to the maximum solubility limit of lithium in aluminum. Methods for forming bridge structures utilizing such an alloy are also described.

Abstract: The process of the present invention can be used for conventional processing or for the Damascene process. The key concept of the present invention is a functional "filler" material which can later be removed (decomposed) to leave an air gap between the conducting lines. The filler material can be deposited as a step during conventional metal etch processing or it can be deposited as a first step of the processing of a semiconductor wafer. Leakage currents can be reduced as part of the present invention by applying passivation layers.

Abstract: A method of forming a multi-layered interconnect structure is provided. A first conductive pattern is formed over an insulation layer. A first dielectric material is deposited over the first conductive pattern, and plugs are formed in the first dielectric material. A second conductive pattern is formed over the first dielectric material and plugs so as to form the multi-layered interconnect structure in part. Then, the first dielectric material is stripped away to leave the multi-layered interconnect structure exposed to air. A thin layer of second dielectric material is deposited so as to coat at least a portion of the interconnect structure. Next, a thin layer of metal is deposited so as to coat the at least a portion of the interconnect structure coated with the thin layer of second dielectric material. A third dielectric material is deposited over the interconnect structure to replace the stripped away first dielectric material.

Abstract: An electronic part having an air-bridge interconnection has a flat air-bridge interconnection body, no interconnection loss, high Q and low power consumption. Also disclosed is a method of manufacturing such electronic parts. The flat air-bridge interconnection body is obtained by conducting two-stage selective plating including selective plating for forming posts on post base electrodes and selective plating for forming the air-bridge interconnection body.

Abstract: An air bridge between closely spaced interconnect lines is formed by a high density plasma chemical vapor deposition of fluorinated amorphous carbon. In one particular embodiment of the present invention, to create the air bridge, high density plasma chemical vapor deposition of fluorocarbon and hydrocarbon precursors, with little or no rf bias applied to the substrate is performed. For mechanical support of subsequently formed layers, the air bridge is capped by a hard mask layer, typically formed from an insulating material such as silicon dioxide, fluorinated silicon dioxide, or silicon nitride.

Abstract: A method of making an integrated circuit interconnect structure having air as the effective dielectric between metallization layers includes the steps of: a) providing an air dielectric formation layer of a sacrificial material over a substrate; b) forming a pillar holes in the air dielectric formation layer; c) filling the pillar holes with a non-sacrificial material; d) constructing a metallization layer over the sacrificial air dielectric formation layer and non-sacrificial material pillars; and e) applying an isotropic etchant to the interconnect structure to remove the sacrificial material, leaving the non-sacrificial material pillars for mechanical support of the metallization layer. An interconnect structure having an air dielectric includes a bottom metallization layer, a top metallization layer, and a plurality of pillars separating the bottom and top metallization layers and mechanically supporting the top metallization layer.

Abstract: A method for manufacturing an inductor with resonant frequency and Q value increased in semiconductor process can reduce substrate coupling effect, because (an) air layer(s) is/are formed just under a spiral metal layer which functions as an inductor. In addition, part of the substrate material still remains around the air layer(s), which can be used as a support for the spiral metal layer. Therefore, a problem causing the above-mentioned spiral metal layer to collapse will never occur.

Abstract: The present invention is a semiconductor device having a plurality of wiring on a semiconductor substrate. It is provided with a first insulating film which covers the surface of all the aforesaid wiring, and a second insulating film containing air gaps which is formed between such of the aforesaid wiring as is mutually adjacent.The method of manufacturing the semiconductor device to which the present invention pertains comprises a process whereby the first insulating film is formed in such a manner as to cover the surface of the plurality of wiring formed on the semiconductor substrate, and a process whereby the second insulating film containing air gaps is formed between such of the wiring on the aforesaid substrate as is mutually adjacent. Here, the first insulating film is formed by means of the plasma CVD or spin coating methods, the second by means of the plasma CVD, spin coating, bias CVD, sputtering or similar methods.

Abstract: A inlaid interconnect is formed in a semiconductor device (30). A first interlayer dielectric (ILD) 40 is deposited and etched to form a via opening (44). An etchstop layer (42) is deposited on ILD (40). A second ILD (45) is deposited on etchstop layer (42) in a manner so that a pinch-off region (46) is formed to prevent substantial deposition of the ILD material into via opening (44). While a small deposit (47) of ILD material may form within the via opening, this can be easily removed in a subsequent etch of ILD (45) which forms a trench opening (48) in ILD (45). A metal layer (50) is then deposited and polished to form a metal interconnect having a trench portion (52) and a via portion (54) in device (30). The present invention avoids the need for a substantial over-etch to clear the via, and avoids the need to form a thick resist mask to form the via opening, while maintaining a controlled via diameter.

Abstract: In producing a multilevel interconnection structure, an insulator film is placed on and bonded to interconnecting lines laid on an insulating layer on a semiconductor substrate such that all the spacings between the interconnecting lines are left as vacant spaces. For example, the insulator film is a polyimide film or a silicon oxide film. The vacant spaces serve the purpose of reducing capacitance between adjacent interconnecting lines. After forming contact holes in the insulator film and filling the contact holes with a metal, upper-level interconnecting lines are laid on the insulator film.

Abstract: The present invention is directed to a semiconductor interconnect structure comprised of a promoter layer defining openings and a metal layer having a portion elevated above the substrate assembly and a portion that fills the openings. The metal layer is in electrical contact with the substrate assembly through the portion of the metal layer that fills the openings. The portion of the metal layer that fills the openings supports the elevated portion of the metal layer. A method of fabricating a semiconductor interconnect structure is also provided. A resist layer is patterned on a substrate assembly to define openings. A metal layer is deposited on the resist layer and into the openings, and the resist layer is removed to form a gap between the metal layer and the underlying substrate assembly.

Abstract: A process for forming air gaps in an interconnect system is disclosed. At least two conductive lines are formed upon a substrate. A low-dielectric constant material (LDCM) is formed between the at least two conductive lines. Formation of the LDCM creates first and second adhesive forces between the LDCM and the at least two conductive lines and between the LDCM and the substrate, respectively. The LDCM is expanded. A dielectric layer is formed onto the LDCM and the at least two conductive lines. Formation of the dielectric layer creates a third adhesive force between the LDCM and the dielectric layer. The LDCM is contracted. Contraction of the LDCM resulting from a fourth force within the LDCM. Each of the first, second, and third adhesive forces are substantially stronger than the fourth force.

Abstract: A semiconductor structure having a first conductive trace fabricated adjacent to a second conductive trace over an insulating layer. A dielectric material is located over and between the first and second conductive traces. A borderless contact extends through the dielectric material to contact the first conductive trace. An air gap is formed in the dielectric material between the first and second conductive traces, thereby increasing the capacitance between the first and second traces. The air gap has a first portion with a first width adjacent to the borderless contact, and a second portion with a second width away from the borderless contact. The second width is greater than the first width, and the second portion of the air gap is substantially longer than the first portion of the air gap. The first portion of the air gap is offset toward the second trace.

Abstract: A first insulator is formed on a base layer. A first conductor is formed on the first insulator. The first conductor is patterned. A second insulator is formed over the first insulator. A via hole is formed in the second insulator and is electrically coupled to the first conductor through the via hole. A second conductor is formed on the second insulator, and is electrically coupled to the first conductor by the via hole. The second conductor is patterned. A cavity is formed under the second conductor, and in the first and second insulators.

Abstract: A structured dielectric layer and fabrication process for separating wiring levels and wires within a level on a semiconductor chip is described incorporating a lower dielectric layer having narrow air gaps to form dielectric pillars or lines and an upper dielectric layer formed over the pillars or fine lines wherein the air gaps function to substantially reduce the effective dielectric constant of the structured layer. The invention overcomes the problem of solid dielectric layers which would have the higher dielectric constant of the solid material used.

Abstract: An air bridge type structure of a bridge shape which joins to a substrate or micro-structure is manufactured by forming an air bridge type structure on a first substrate and transferring the air bridge type structure to a second substrate and/or a micro-structure formed on the second substrate. A mold substrate, comprising a recessed portion provided on the surface of the mold substrate and a peeling layer formed on the recessed portion, is used for formation of the air bridge type structure. A micro-structure can be supported by the air bridge type structure, for example, a probe for detecting tunneling current or micro-force, supported by the air bridge type structure. Accordingly, electrical connection between structures and the substrate or between the structures one to another can be performed, even if there is undercutting underneath the structures.

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors.

Abstract: A method of forming a thick interlevel dielectric layer containing sealed voids, formed in a controlled manner, over a substantially planar surface in semiconductor device structure, and the semiconductor structure formed according to such a method. The sealed voids are used to reduce interlevel capacitance. A plurality of metal signal lines are formed over a globally planarized insulator. A thick layer of first conformal interlevel dielectric is deposited over the metal signal lines and over the intermetal spacings formed between the metal signal lines. Because of the thickness, flow properties, and manner of deposition of the interlevel dielectric and the aspect ratio the intermetal spacings, voids are formed in the first conformal interlevel dielectric, in the intermetal spacings. This interlevel dielectric is then etched or polished back to the desired thickness, which exposes the voids in the wider intermetal spacings, but does not expose voids in the narrower intermetal spacings.

Abstract: A method for fabricating metal lines in multilevel VLSI semiconductor integrated circuit devices is provided so as to reduce parasitic capacitance. An undercutting etching step is performed so as to form trenches underneath the metal lines for accommodating air voids, followed by forming an intra-layer dielectric between the metal lines and into the trenches so as to form air voids underneath the metal lines. As a result, the parasitic capacitance will be decreased.

Abstract: A handle wafer has a cavity coated with a dielectric. A device wafer is bonded to the handle wafer. Metal lines, devices or circuits fabricated on device layer overlay the cavity in the handle wafer thus reducing parasitic capacitances to the handle wafer and crosstalk through the handle wafer. This constitutes a rugged air bridge structure capable of being passivated and/or being placed in plastic packages.

Abstract: A method for making air-insulated planar metal interconnections having low interlevel capacitance with improved RC time delays for integrated circuits is achieved. The method involves using a multilayer of negative and positive photoresists in which open regions are developed in the negative photoresist for the metal interconnections, and open regions are developed in the positive photoresist for via holes. The open regions are then filled with a Ti/TiN diffusion barrier deposited at room temperature and an electroless plated copper, and polished back using a Dual Damazene to form the interconnecting metal level and the via hole stud. The method is repeated several times to form multilevel metal interconnections. The remaining photoresist is then totally removed by oxygen ashing to leave a free-standing multilevel metal interconnection structure that is conformally coated with a thin Al.sub.2 O.sub.3 passivation layer and having air insulation.

Abstract: The read only memory has a plurality of conductor track planes one above the other. The conductor tracks in adjacent planes are oriented such that they intersect in intersecting regions. In these intersecting regions, either a VIA tunnel contact is provided, which represents a logic "1" or no VIA tunnel contact is provided, so that this intersecting region represents a logic "0". In this way, over the same surface area, a plurality of memory cells can be produced one above the other. The read only memory is produced with a defined sequence of process steps and it is operated by selectively applying predetermined voltages across the various conductor tracks.

Abstract: A method of forming integrated circuitry includes, a) providing a pair of spaced and adjacent electrically conductive elongated lines; and b) providing electrically insulative material over the pair of spaced lines in a manner which leaves an elongated void between the lines, the elongated void being top sealed along its substantial elongated length. Preferably, the electrically insulative material is provided by depositing electrically insulative material over the pair of lines in a manner which produces a retrograde cross-sectional profile of the insulating material relative to the respective line sidewalls and which leaves an elongated top sealed void within the insulating material between the lines, the elongated void being open at at least one end. The void at the one end is subsequently sealed.

Abstract: A terminal metallization (8) is applied onto and structured on a layer structure on the upper side of the component, the terminal metallization is applied on the upper side of an insulating layer (7) with an opening on a metallization (6) provided for electrical connection. By filling a hole produced in a covering dielectric with metal, a contact rod (12) seated on this terminal metallization (8) is formed. This contact rod is resiliently movable in a surrounding opening (14) of the component on the free part of the terminal metallization (8) anchored in the layer structure. This enables the reversible contacting of the component to a further component arranged vertically thereto, whereby the planar upper sides lying opposite one another can be brought into intimate contact because the contact rod (12) pressed against a contact (15) of the other component is pressed back into the opening (14) and an adequately firm connection of the contacts is achieved by the spring power of the terminal metallization (8).

Abstract: A new method of forming the dielectric layer of an integrated circuit using metal layout is described. An insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. Metal lines are formed overlying the insulating layer wherein the metal line mask is modified so that narrow trenches with constant width and depth are etched surrounding the metal lines and the remaining metal areas are not etched away but are left as dummy metal areas. A dielectric layer is deposited over the metal lines and dummy metal areas wherein voids are formed within the trenches between metal lines and wherein the top surface of the dielectric layer is planarized. The voids act to release system stress and to lower capacitance between the metal lines.

Abstract: Disclosed herein is a method for forming an interconnect line having low conductor line capacitance between devices formed on an integrated circuit.

Abstract: A process of manufacturing integrated circuits is disclosed for designing and implementing a hierarchical wiring system. The interconnection requirements are sorted and designed into a particular wiring level according to length. Support structures may be constructed to allow more flexibility in designing air bridge dimensions. The support structures may take the form of lateral ribs or intermediate posts, and may be fabricated of either insulating or conductive material. One integrated circuit described is a memory device, such as a dynamic random access memory.

Abstract: Methods of wet etching through a silicon substrate using composite etch-stop layers are disclosed. In one embodiment, the composite etch stop comprises a layer of silicon dioxide and a layer of polyimide.

Abstract: A method of manufacturing a semiconductor component, wherein capacitances occurring between contacts, interconnects or metallizations are reduced by filling cavities with air or gas is provided. The cavities are produced between the semiconductor material and a passivation layer in a region wherein the interconnects are surrounded by dielectric and are subsequently closed by a further passivation layer.

Abstract: An ultimate low k (k=1) gap structure for high speed logic devices in which the sidewalls fully or partially cover the gaps between the interconnects by dry etching the already formed aluminum interconnects after the photoresist has been stripped. This method is particularly useful for the subsequent deposition of silicon dioxide and for forming air gaps.

Abstract: An interconnect structure having a dielectric layer with low dielectric constant is formed within an integrated circuit. In one embodiment of the invention, portions of a silicon dioxide layer (18) lying adjacent to a conductive interconnect (21) are removed to expose portions of a silicon nitride etch stop layer (16). A dielectric layer (22) having a low dielectric constant is then formed overlying the conductive interconnect (21) and the exposed portions of the silicon nitride etch stop layer (16). A portion of the dielectric layer (22) is then removed to expose the top surface of the conductive interconnect (21) to leave portions of the dielectric layer (22) between adjacent conductive interconnects (21). The resulting interconnect structure has reduced cross-talk between conductive interconnects (21) while avoiding prior art disadvantages of reduced thermal dissipation and increased mechanical stress.

Abstract: A method and apparatus for providing a sub-ground plane for a micromachined device. The sub-ground plane is formed in or on the substrate. Above the sub-ground plane is a dielectric and then a discontinuous conductive layer used for interconnects for parts of the micromachined device. A movable microstructure is suspended above the interconnect layer. A conductive layer can be suspended above the movable microstructure. In one embodiment, the sub-ground plane is diffused into the substrate or a well in the substrate, and is of an opposite type from the type of silicon into which it is diffused. Alternatively, the sub-ground plane is formed from a conductive layer, deposited over the substrate before the layer used for interconnects.

Abstract: The present invention provides an interconnect system. The interconnect system includes a substrate, a first dielectric layer deposited upon the substrate. The interconnect system further includes at least two electrically conductive interconnect lines formed upon the first dielectric layer. Each of the at least two interconnect lines have a top surface and side surfaces. Adjacent side surfaces of two adjacent interconnect lines define therebetween a space that has a dielectric constant substantially equal to 1. A dielectric film is bonded upon the top surface of the at least two interconnect lines. The dielectric film substantially prevents obstruction of the space by further process.

Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposition of the nonconformal source material is stopped and a flowable insulating material, such as spin on glass, is coated on nonconformal insulating material to fill the remaining gaps. After etching the surfaces of the nonconformal and flowable insulating materials, another insulating layer is deposited and planarized to the desired overall thickness of the insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines.

Abstract: A reduced permittivity interlevel dielectric in a semiconductor device arranged between two levels of interconnect. The dielectric comprises a first dielectric layer preferably from a silane source deposited on a first level interconnect to form air gaps at midpoints between adjacent first interconnect structures, a second dielectric containing air gap trenches at spaced intervals across the second dielectric, and a third dielectric formed upon said second dielectric. A second interconnect level is formed on the third dielectric.

Abstract: A fast economical method for modification or repair of micro-circuit wiring patterns covered by a dielectric using a conducting bridge and focused ion beam technology. A conducting bridge is formed on the dielectric between selected points of the wiring pattern using a mask formed by assembling selectively shaped pieces of a transparent mask material such as plastic. The conducting bridge is formed from a material such as gold, copper, or platinum and has sufficient conductivity for long distances. A focused ion beam is then used to form contact holes in the dielectric thereby exposing selected regions of the wiring pattern for connection to the conducting bridge. Connecting material is then selectively deposited using focussed ion beam assisted chemical vapor deposition to connect the conducting bridge to the appropriate points of the wiring pattern. The length of the connecting material does not exceed about 200 micrometers and thus has adequate conductivity.