Air Bridge Structure Patents (Class 438/619)
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Patent number: 6309946Abstract: A void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. For one approach, hollow silicon define the void. The spheres are fabricated to a known inner diameter, wall thickness and outer diameter. The spheres are ridgid enough to withstand the mechanical processes occurring during semiconductor fabrication. The spheres withstand elevated temperature up to a prescribed temperature range. At or above a desired temperature, the sphere walls disintegrate leaving the void in place. For an alternative approach, adjacent wiring lines are “T-topped” (i.e., viewed cross-sectionally). Dielectric fill deposited in the spacing between lines. As the dielectric material accumulates on the line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off and internal void.Type: GrantFiled: December 8, 1998Date of Patent: October 30, 2001Assignee: Micron Technology, Inc.Inventor: John H. Givens
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Publication number: 20010034117Abstract: A microelectronic device package and method for manufacture. In one embodiment, the device package can include a microelectronic substrate having first and second device features, a conductive link that includes a conductive material extending between the first and second device features, and an external cover or enclosure disposed around at least a portion of the substrate and the conductive link. The package can be filled with a liquid or a pressurized gas to transfer heat away from the conductive link. In one embodiment, the enclosure can have a composition substantially identical to the composition of the conductive links and the enclosure can be formed simultaneously with formation of the conductive link to reduce the number of process steps required to form the microelectronic device package. A sacrificial material can temporarily support the conductive link during manufacture and can subsequently be removed to suspend at least a portion of the conductive link between two points.Type: ApplicationFiled: June 27, 2001Publication date: October 25, 2001Inventors: Jerome M. Eldridge, Paul A. Farrar
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Patent number: 6307265Abstract: Wires are provided on an insulating layer, reaching the source region and drain region of a MOS transistor. Each wire is composed of a conductor and a barrier layer covering the surfaces of the conductor. An insulating layer is mounted on the wires, an insulating layer on the insulating layer, and an insulating layer on the insulating layer. Cavities are provided among the wires. The cavities are filled with air or a mixture gas of oxygen and carbon dioxide. Wires are provided on the insulating layer. Cavities are provided among the wires. These cavities are filled with air or a mixture gas of oxygen and carbon dioxide.Type: GrantFiled: August 15, 1996Date of Patent: October 23, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Minakshisundaran Balasubramanian Anand, Hideki Shibata, Masaki Yamada
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Patent number: 6306753Abstract: Wires are provided on an insulating layer, reaching the source region and drain region of a MOS transistor. Each wire is composed of a conductor and a barrier layer covering the surfaces of the conductor. An insulating layer is mounted on the wires, an insulating layer on the insulating layer, and an insulating layer on the insulating layer. Cavities are provided among the wires. The cavities are filled with air or a mixture gas of oxygen and carbon dioxide. Wires are provided on the insulating layer. Cavities are provided among the wires. These cavities are filled with air or a mixture gas of oxygen and carbon dioxide.Type: GrantFiled: March 14, 2000Date of Patent: October 23, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Minakshisundaran Balasubramanian Anand, Hideki Shibata, Masaki Yamada
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Patent number: 6306754Abstract: A method for creating metal layers in a microelectronic device where air is the primary dielectric separating adjacent metal features within a layer. A temporary structural solid, such as a photoresist, is deposited on a substrate with exposed metal features. The photoresist is etched back to expose at least the top surfaces of the metal features. A porous dielectric is then deposited on the substrate and cured to stabilize the structure. The substrate is then treated with a supercritical fluid, such as supercritical CO2, to extract the photoresist through the pores of the porous dielectric layer.Type: GrantFiled: June 29, 1999Date of Patent: October 23, 2001Assignee: Micron Technology, Inc.Inventor: Vishnu K. Agarwal
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Patent number: 6306761Abstract: A hard Al oxide film having a high melting point, which grows on the surface of an Al—Cu film during a wafer is carried in atmospheric air, obstructs the burying of a viahole with the Al—Cu film by high pressure reflow, with a result that a void remains in the hole. The present invention is intended to remove such an Al oxide film grown on the Al—Cu film formed by sputtering, by Ar+ sputtering/etching directly before high pressure reflow. Moreover, when a Ti oxide film is present on the surface of a Ti based underlying film formed by CVD, an Al oxide film is possibly grown at the boundary between the Ti based underlying film and an Al—Cu film laminated thereon. In this case, the Ti oxide film is similarly removed directly before formation of the Al—Cu film, thereby preventing the growth of the Al oxide film.Type: GrantFiled: April 25, 1996Date of Patent: October 23, 2001Assignee: Sony CorporationInventor: Mitsuru Taguchi
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Patent number: 6303487Abstract: In a method for forming an air gap in an insulating film between adjacent interconnection conductors in a semiconductor device, a substrate having a first insulator film and a plurality of lower level interconnection conductors formed separately from each other on the first insulator film is set in a chemical vapor process machine. A second insulator film is deposited to completely cover the plurality of lower level interconnection conductors and the first insulator film in a chemical vapor process under the condition that a growth speed in a vertical direction perpendicular to a principal surface of the substrate is lower than a growth speed in a horizontal direction in parallel to the principal surface of the substrate, until the second insulator film has such a thickness that an air gap is formed within the second insulator film between the adjacent interconnection conductors.Type: GrantFiled: December 3, 1999Date of Patent: October 16, 2001Assignee: NEC CorporationInventor: Masaki Kagamihara
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Patent number: 6303464Abstract: A reduced capacitance interconnect system. A first metal layer is formed to a predetermined level above a first dielectric layer which is formed on a semiconductor substrate. The first metal layer level forms multiple interconnect lines wherein each interconnect line is separated from each adjacent interconnect line by a trench including a trench having a highest aspect ratio. A second dielectric layer is formed on the first metal layer and in the trenches between the interconnect lines such that an enclosed void having a void tip substantially level with the top of the metal layer is formed in at least each trench having an aspect ratio above a predetermined minimum aspect ratio, wherein the enclosed void in the trench having the highest aspect ratio has a void volume which is at least 15% of the volume of the trench.Type: GrantFiled: December 30, 1996Date of Patent: October 16, 2001Assignee: Intel CorporationInventors: Eng T. Gaw, Quat T. Vu, David B. Fraser, Chien Chiang, Ian A. Young, Thomas N. D. Marieb
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Patent number: 6303486Abstract: A method is provided for forming a copper interconnect, the method including forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first copper structure in the first opening. The method also includes forming a sacrificial dielectric layer above the first dielectric layer and above the first copper structure, forming a second opening in the sacrificial dielectric layer above at least a portion of the first copper structure, and forming a second copper structure in the second opening, the second copper structure contacting the at least the portion of the first copper structure. The method further includes removing the sacrificial dielectric layer above the first dielectric layer and adjacent the second copper structure, and forming the copper interconnect by annealing the second copper structure and the first copper structure.Type: GrantFiled: January 28, 2000Date of Patent: October 16, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Stephen Keetai Park
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Patent number: 6297145Abstract: A method of manufacturing a semiconductor device having a wiring layer with an air bridge construction includes the steps of forming a lower layer metal interconnect, depositing an interlayer insulation film, depositing a first and a second insulation film, patterning the second insulation film and of etching the first insulation film and the interlayer insulation film using the second insulation film as a mask so as to form a post opening part and a via hole to connect an upper layer metal interconnect with the lower layer metal interconnect, depositing a third insulation film over the entire surface, etching back so as to leave the third insulation film in a side wall of the post opening part and fill the via hole with the third insulation film, depositing a fourth insulation film over the entire surface of the structure, then removing the fourth insulation film until the via hole is exposed, and then removing the third insulation film inside the via hole, filling the via hole with a metal, and then flattenType: GrantFiled: May 13, 1999Date of Patent: October 2, 2001Assignee: NEC CorporationInventor: Shinya Ito
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Patent number: 6294455Abstract: Conductive lines, such as co-axial lines, integrated circuitry incorporating such conductive lines, and methods of forming the same are described. In one aspect, a substrate having an outer surface is provided. A masking material is formed over the outer surface and subsequently patterned to form a conductive line pattern. An inner conductive layer is formed within the conductive line pattern, followed by formation of a dielectric layer thereover and an outer conductive layer over the dielectric layer. Preferred implementations include forming the inner conductive layer through electroplating, or alternatively, electroless plating techniques. Other preferred implementations include forming the dielectric layer from suitable polymer materials having desired dielectric properties. A vapor-deposited dielectric layer of Parylene is one such preferred dielectric material.Type: GrantFiled: August 20, 1997Date of Patent: September 25, 2001Assignee: Micron Technology, Inc.Inventor: Kie Y. Ahn
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Semiconductor device having multilevel interconnection structure and method for fabricating the same
Publication number: 20010023128Abstract: A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substratType: ApplicationFiled: April 16, 2001Publication date: September 20, 2001Applicant: Matsushita Electrics CorporationInventors: Tetsuya Ueda, Eiji Tamaoka, Nobuo Aoi -
Patent number: 6284621Abstract: A semiconductor structure with a dielectric layer and its producing method are disclosed. The semiconductor structure includes a semiconductor substrate having thereon a plurality of metal lines and there are a plurality of concave regions formed between the metal lines. The dielectric layer is formed on the semiconductor by a method which can prevent the dielectric material from flowing into the concave regions. The method includes the steps of (a) providing a semiconductor substrate having thereon a plurality of metal lines forming therebetween a plurality of concave regions; and (b) forming the dielectric layer on the metal lines. The concave regions are only filled with air so that the capacitance of the semiconductor is lowered.Type: GrantFiled: January 27, 1999Date of Patent: September 4, 2001Assignee: National Science CouncilInventors: Kow-Ming Chang, Ji-Yi Yang
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Publication number: 20010016409Abstract: A first insulator is formed on a base layer. A first conductor is formed on the first insulator. The first conductor is patterned. A second insulator is formed over the first insulator. A via hole is formed in the second insulator and is electrically coupled to the first conductor through the via hole. A second conductor is formed on the second insulator, and is electrically coupled to the first conductor by the via hole. The second conductor is patterned. A cavity is formed under the second conductor, and in the first and second insulators.Type: ApplicationFiled: December 20, 1999Publication date: August 23, 2001Inventors: PAUL A. FARRAR, LEONARD FORBES
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Patent number: 6277705Abstract: A fabrication method for an air-gap, in which method hard mask is used, is described. A patterned hard mask layer is formed on a semiconductor substrate. Taking advantage of the etching selectivity of the hard mask layer to the dielectric layer, an opening with a high aspect ratio is formed in the dielectric layer. A conductive plug is then formed in the opening, followed by forming a conductive layer on the hard mask layer to cover the conductive plug. The hard mask layer is further removed. A silicon oxide layer with poor step coverage is formed to cover the substrate. Using the space remaining after the removal of the hard mask layer, an air-gap is formed between the conductive layer and the dielectric layer to enhance the insulation effect.Type: GrantFiled: January 14, 2000Date of Patent: August 21, 2001Assignee: United Microelectronics Corp.Inventor: Robin Lee
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Patent number: 6277728Abstract: A multilevel interconnect structure with a low-k dielectric constant is fabricated in an integrated circuit structure by the steps of depositing a layer of photoresist on a substrate assembly, etching the photoresist to form openings, forming a metal layer on the photoresist layer to fill the openings and then removing the photoresist layer by, for example, ashing. The metal layer is supported by the metal which filled the openings formed in the photoresist.Type: GrantFiled: August 17, 1999Date of Patent: August 21, 2001Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Publication number: 20010014526Abstract: Disclosed is a structure and process for incorporating air or other gas as a permanent dielectric medium in a multilevel chip by providing CVD diamond as a semi-sacrificial interlevel and intralevel dielectric material. The semi-sacrificial dielectric is subsequently at least partially removed in an isotropic oxygen etch. A variation of the disclosure includes providing a final, permanent CVD diamond encapsulant to contain the gaseous dielectric medium within the chip.Type: ApplicationFiled: April 4, 2001Publication date: August 16, 2001Inventors: Lawrence A. Clevenger, Louis Lu-Chen Hsu
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Patent number: 6268276Abstract: A new method of forming air gaps between adjacent conducting lines of a semiconductor circuit by using a “holes everywhere” or a “reverse metal holes” mask that can be used to create holes in a dielectric layer. The dielectric that is being etched has been deposited across conducting lines, the holes that are being formed in this manner are closed by depositing a dielectric across the top of the holes. The holes can be etched across the entire layer of the deposited dielectric or can be etched in between the conducting lines.Type: GrantFiled: December 21, 1998Date of Patent: July 31, 2001Assignees: Chartered Semiconductor Manufacturing Ltd., Nanyang Technological University of SingaporeInventors: Lap Chan, Kheng Chok Tee, Kok Keng Ong, Chin Hwee Seah
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Patent number: 6268261Abstract: A process for manufacturing a semiconductor circuit. The process comprises creating a plurality of adjacent conductive lines having a solid fill between the conductive lines; creating one or more layers above the lines and the fill; creating one or more pathways to the fill through the layers; and converting the fill to a gas that escapes through the pathways, leaving an air void between adjacent lines. To protect the lines from oxidation during processing, a related process for encapsulating conductive lines in one or more adhesion-promotion barrier layers may be performed. The encapsulation process may also be practiced in conjunction with other semiconductor manufacturing processes. The processes result in a multi-layer semiconductor circuit comprising conductive lines, wherein the lines have air as a dielectric between them, are encapsulated by an adhesion-promotion barrier layer, or both.Type: GrantFiled: November 3, 1998Date of Patent: July 31, 2001Assignee: International Business Machines CorporationInventors: Kevin S. Petrarca, Rebecca D. Mih
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Patent number: 6268277Abstract: A method of reducing intralevel capacitance in a damascene metalization process employs entrapped air gaps between metal lines. The method involves forming a metalization pattern using a damascene process which includes forming at least first and second metal regions separated by a dielectric region, forming an air gap at least partially within the dielectric region, and sealing the air gap to entrap the air gap between the first and second metal regions thereby reducing intralevel capacitance between the first and second metal regions.Type: GrantFiled: July 16, 1999Date of Patent: July 31, 2001Assignee: Advanced Micro Devices, Inc.Inventor: David Bang
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Patent number: 6268262Abstract: Disclosed is a method for making an air bridge in an electronic device. This method uses amorphous silicon carbide to protect electrical conductors in the device during formation of the bridge. The silicon carbide also provides hermetic and physical protection to the device after formation.Type: GrantFiled: August 11, 1997Date of Patent: July 31, 2001Assignee: Dow Corning CorporationInventor: Mark Jon Loboda
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Patent number: 6261943Abstract: Methods for fabricating a free-standing thin metal film are provided. In one method, a sacrificial silicon nitride membrane structure is provided comprising a silicon wafer having first and second surfaces, a first silicon nitride layer applied to the first surface of the silicon wafer and a second silicon nitride layer applied to the second surface of the silicon wafer. The second silicon nitride layer and the silicon wafer are etched to provide a window that exposes a predetermined area of the first silicon nitride layer, whereby the exposed predetermined area of the front silicon nitride layer comprises a sacrificial silicon nitride membrane unsupported by any auxiliary substrate over the predetermined area. A thin metal film is then deposited on the first silicon nitride layer. Finally, the sacrificial silicon nitride membrane is removed, whereby the portion of the thin metal film exposed by the removal of the silicon nitride membrane comprises the free-standing thin metal film.Type: GrantFiled: February 8, 2000Date of Patent: July 17, 2001Assignee: NEC Research Institute, Inc.Inventor: Daniel E. Grupp
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Patent number: 6261942Abstract: A method for introducing air into the gaps between neighboring conducting structures in a microelectronics fabrication in order to reduce the capacitative coupling between them. A patterned metal layer is deposited on a substrate. The layer is lined with a CVD-oxide. A disposable gap-filling material is deposited over the lined metal layer. A two layer “air-bridge” is formed over the gap-fill by depositing a layer of TiN over a layer of CVD-oxide. This structure is rendered porous by several chemical processes. An oxygen plasma is passed through the porous air-bridge to react with and dissolve the gap-fill beneath it. The reaction products escape through the porous air-bridge resulting in air-filled gaps.Type: GrantFiled: January 24, 2000Date of Patent: July 17, 2001Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Mei Sheng Zhou, Simon Chooi, Xu Yi
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Patent number: 6255137Abstract: A method for making an HDI-connected circuit is described, which in a simple manner allows an air pocket, space, gap, or bubble to be formed over pressure- or dielectric-sensitive portions of a semiconductor chip. The method applies a layer of uncured adhesive over a dielectric film, and also over any electrical conductors deposited on the film. The adhesive is exposed through a mask to a laser beam, which selectively vaporizes the adhesive in the exposed regions, to define the air pocket region. The semiconductor chips are applied, electrode-side down, on the adhesive, with the sensitive regions registered with the pockets. The adhesive is cured, and conductive vias are formed through the dielectric film and the adhesive to make contact with the electrodes of the semiconductor chips. Other layers of HDI interconnect are then applied over the dielectric film, and interconnected by vias, if needed.Type: GrantFiled: July 1, 1999Date of Patent: July 3, 2001Assignee: Lockheed Martin Corp.Inventors: Thomas Bert Gorczyca, Herbert Stanley Cole
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Patent number: 6251798Abstract: A method for the formation of an air gap structure for use in inter-metal applications. A metal pattern of metal lines is formed, a layer of Plasma Polymerized Methylsilane (PPMS) resist is deposited on top of this pattern. The surface of the PPMS resist is subjected to selective exposure. The unexposed PPMS is removed after which the process is completed by closing up the openings within the PPMS.Type: GrantFiled: July 26, 1999Date of Patent: June 26, 2001Assignees: Chartered Semiconductor Manufacturing Company, National University of Singapore, Nanyang Technological University of SingaporeInventors: Choi Pheng Soo, Kheng Chok Tee, Kok Keng Ong, Lap Chan
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Patent number: 6248622Abstract: A fabrication method for an ultra short channel device comprising a self-aligned landing pad is described in which a first opening is formed in the oxide layer to define a gate structure region. A pad oxide layer is then formed in the first opening covering the substrate followed by forming a spacer on the inner sidewall of the first opening. Using the spacer as an etching mask, a portion of the oxide layer is removed to form a second opening exposing the substrate. A gate oxide layer is then deposited in the second opening, followed by forming a first conductive layer to fill the second opening. A third opening is then formed in the oxide layer to expose the substrate and to define the source/drain region. An ion implantation is then conducted in the substrate of the third opening to form a heavily doped region of the source/drain region. Thereafter, a landing pad is formed to fill the third opening and to electrically connect with the source/drain region.Type: GrantFiled: October 27, 1999Date of Patent: June 19, 2001Assignee: United Microelectronics Corp.Inventor: Robin Lee
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Patent number: 6245658Abstract: Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and supporting the interconnection system with a metal silicide lining. Embodiments include depositing a dielectric sealing layer, e.g., silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, electroplating or electroless plating a metal, such as cobalt or nickel, to line the interconnection system, depositing a thin layer of polycrystalline silicon on the metal, heating to form the metal silicide lining on the interconnection system, and forming dielectric protective layers, e.g. a silane derived oxide bottommost protective layer, on the uppermost metallization level.Type: GrantFiled: February 18, 1999Date of Patent: June 12, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Matthew S. Buynoski
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Semiconductor device having multilevel interconnection structure and method for fabricating the same
Patent number: 6242336Abstract: A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substratType: GrantFiled: November 5, 1998Date of Patent: June 5, 2001Assignee: Matsushita Electronics CorporationInventors: Tetsuya Ueda, Eiji Tamaoka, Nobuo Aoi -
Patent number: 6239016Abstract: In a multilevel interconnection structure for a semiconductor device, lower level interconnections 3 are formed on an insulator film 2 formed on a substrate 1, and a silicon oxide film 4a is formed to cover the lower level interconnections 3 and to fill up a region between adjacent lower level interconnections 3, by means of a biased ECR-CVD process so that a cavity 5 is formed in the silicon oxide film 4a between the adjacent lower level interconnections 3. The silicon oxide film 4a is selectively removed from a tolerable region covering the extent in which a hole for the metal pillar 6 is allowed to deviate from a target lower level interconnection 3, and then, another silicon oxide 4b is formed to fill up the removed portion and to cover the first silicon oxide film. The metal pillar 6 is formed to extended through the silicon oxide film 4b filling the removed portion off silicon oxide film 4a, so as to reach the target lower level interconnection 3.Type: GrantFiled: August 17, 1998Date of Patent: May 29, 2001Assignee: NEC CorporationInventor: Hiraku Ishikawa
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Patent number: 6235625Abstract: A method of fabricating a Cu damascene, the method comprises of forming an amorphous silicon layer in a trench line and a via. The amorphous silicon layer is then displaced with a Cu layer using a Cu displacement process. With the Cu layer serving as a seeding layer, a Cu electroplating or a Cu electroless plating is performed, so that the trench line and the via is selectively filled with the Cu layer.Type: GrantFiled: June 18, 1999Date of Patent: May 22, 2001Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chine-Gie Lou
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Patent number: 6235354Abstract: The present invention relates to a method of forming a level silicon oxide layer on a semiconductor wafer. The semiconductor wafer comprises a substrate having a first region containing no silicon nitride on its surface and a second region which is higher than the first region and contains a silicon nitride layer on its surface. The method comprises performing a cleaning process on the semiconductor wafer with an alkaline solution to uniform the deposition rate over the surface of the first region; and performing a deposition process employing ozone as a reactive gas with a flow capacity of 80-200 g/L to form a silicon oxide layer above the first and second regions wherein the deposition rate of the silicon oxide layer on the first region is higher than that on the second region and the silicon oxide layer above the first region is leveled with that above the second region after a predetermined period of time.Type: GrantFiled: November 1, 1999Date of Patent: May 22, 2001Assignee: United Microelectronics Corp.Inventors: Chin-Hui Lee, Ting-Chi Lin, Chih-Cheng Liu
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Patent number: 6232220Abstract: A method for fabricating a semiconductor component having a low contact resistance with respect to heavily doped or siliconized zones in a semiconductor body. Fluorine ions are implanted into the heavily doped or siliconized zone in the vicinity of a contact hole before a titanium layer is applied to the heavily doped or siliconized zone in the vicinity of the contact hole. As a result of the fluorine, any oxide layers present in the contact hole region can be broken up by less titanium, with the result that a thinner titanium layer is sufficient. In addition, the formation of titanium silicide in the contact hole is promoted.Type: GrantFiled: January 15, 1999Date of Patent: May 15, 2001Assignee: Infineon Technologies AGInventors: Volker Penka, Reinhard Mahnkopf, Helmut Wurzer
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Patent number: 6232214Abstract: A method for fabricating an inter-metal dielectric layer. Several conducting wires are formed on a substrate, and openings lie between the adjacent conducting wires. A first dielectric layer fills the openings, and the surface of the first dielectric layer is lower than that of the conducting wires. A spacer is formed on a sidewall of each of the conducting wires. The first dielectric layer is removed to expose the bottom of the spacer. A second dielectric layer is formed to cover the conducting wires.Type: GrantFiled: May 21, 1999Date of Patent: May 15, 2001Assignee: United Microelectronics Corp.Inventors: Claymens Lee, Gary Hong
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Patent number: 6228763Abstract: A fabrication method for a metal interconnect having an inner air spacer, applicable to multilevel interconnects technologies, is disclosed. The inner air spacer is formed adjacent to a metal layer to provide a lower dielectric constant in a metal interconnect structure. The inner air spacer is formed by initially forming a dielectric spacer on a sidewall of a second dielectric layer, which sidewall defines a trench opening. The trench opening is then filled with the metal layer. The dielectric spacer is removed to form an air gap between the metal layer and the second dielectric layer. The air gap is sealed off with a portion of a third dielectric layer to form the inner air spacer adjacent to a sidewall of the metal layer.Type: GrantFiled: February 29, 2000Date of Patent: May 8, 2001Assignee: United Microelectronics Corp.Inventor: Robin Lee
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Patent number: 6228756Abstract: A method of manufacturing an inter-metal dielectric layer. A substrate having a plurality of wires formed thereon is provided. A portion of the substrate is exposed to form an opening between the wires. The opening is filled with a flowable dielectric material, wherein a surface level of the flowable dielectric material is lower than that of the wires. A plurality of spacers is formed on the sidewall of the wires exposed by the flowable dielectric material. The flowable dielectric material is removed. An anisotropic deposition process with a poor-lateral-filling ability is performed to form a dielectric layer with a void under the spacer over the substrate.Type: GrantFiled: August 10, 1999Date of Patent: May 8, 2001Assignee: United Microelectronics Corp.Inventor: Tong-Hsin Lee
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Patent number: 6221754Abstract: A method of fabricating a plug etches back the first plug material layer to form a dished surface on the first plug material layer and then performs a second coverage step. A second plug material layer is formed to fill the dished surface and a hole. Thus, the slurry cannot fill the hole during chemical mechanical polishing nor can slurry react with the plug material or the first metallic layer. The reliability of the plug according to the present invention is increased. The thickness of the second plug material layer is thinner than the plug material layer of the conventional method. The thickness is decreased by about 60% when compared with the conventional method, which decreases fabrication costs.Type: GrantFiled: October 28, 1998Date of Patent: April 24, 2001Assignee: United Microelectronics Corp.Inventors: J. C. Chiou, Hsiao-Pang Chou
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Patent number: 6218282Abstract: Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigration performance by removing the inter-layer dielectrics and chemical vapor depositing W to line the interconnection system. Embodiments include depositing a dielectric sealing layer, e.g., silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, depositing W by CVD to line the interconnection system and forming dielectric protective layers, e.g. a silane derived oxide bottommost protective layer, on the uppermost metallization level.Type: GrantFiled: February 18, 1999Date of Patent: April 17, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Matthew S. Buynoski
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Patent number: 6214719Abstract: Air-gap technology is introduced in the damascene scheme, reducing the capacitance between interconnect metal lines on an integrated circuit substrate, and ultimately enhancing the speed of the device. Reduction of extraneous signal energy (cross-talk) from traversing from one metal line to another is also realized. The method for implementing an air-gap filled dielectric between the interconnect metal lines involves depositing a first dielectric layer on the substrate at a predetermined height. Next the first dielectric is patterned and etched to form lines. A second dielectric layer is then deposited using air-gap technology, such that the second dielectric contains air-gaps between the first dielectric lines. These air-gaps are situated below the predetermined height of the first dielectric. The substrate is then polished so that the top surface of the first dielectric is exposed. The first dielectric lines are then etched and removed.Type: GrantFiled: September 30, 1999Date of Patent: April 10, 2001Assignee: Novellus Systems, Inc.Inventor: Somnath Nag
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Patent number: 6211057Abstract: In accordance with the objectives of the invention a new method of forming air gaps between adjacent conducting lines of a semiconductor circuit is achieved. A pattern of metal lines is deposited over an insulating layer. A layer of oxynitride (SiON) is deposited over the pattern of metal lines and the exposed surface of the insulating layer. PECVD oxide is deposited over the layer of oxynitride; the PECVD oxide is removed down to the top surface of the layer of oxynitride overlying the metal pattern. A layer of SOON is deposited over the surface of the polished oxynitride and the polished PECVD oxide. A trench is etched between the conducting line pattern through the layer of SOON and into the PECVD oxide. The profile of this trench is aggressively expanded converting the trench profile from a rectangular profile into an arch-shaped profile. The top region of the arch-shaped profile is closed off by depositing a layer of dielectric over the surface of the layer of SOON.Type: GrantFiled: September 3, 1999Date of Patent: April 3, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Shih-Chi Lin, Yen-Ming Chen
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Patent number: 6211056Abstract: Conductive elements which provide interconnections (air bridges between circuits) and components such as capacitors and inductors may be incorporated in the devices in a manner to reduce parasitic effects in the operation of the devices while providing close spacing which enhances the performance of the devices at high frequency. Separate substrates are provided respectively having the integrated circuits formed therein and covering, preferably sealing the integrated circuits. The air bridge conductive components (interconnections, capacitors or inductors) are formed separately in the covering substrate which is assembled with the substrate having the integrated circuit as a lid which seals and packages the circuits and the conductive element or component contained in the lid. The conductive component may be separated by cavities formed in the lid substrate or in the substrate having the integrated circuit device already formed therein.Type: GrantFiled: November 24, 1998Date of Patent: April 3, 2001Assignee: Intersil CorporationInventors: Patrick A. Begley, William R. Young, Anthony L. Rivoli, Jose Avelino Delgado, Stephen J. Gaul
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Patent number: 6204165Abstract: A method of fabricating an integrated circuit having air-gaps between interconnect levels. In a preferred embodiment, an integrated circuit is partially fabricated. The partially fabricated integrated circuit includes a top layer, interconnect structures having a cladding layer, dielectric layers and an etch stop layer resistant to certain first types of etchants. The top layer of the integrated circuit is etched with a second type of etchant. The dielectric layers are then etched with one of the first types of etchants until the etch stop layer is reached. Thus, portions of the interconnect structures are exposed to create interconnect islands surrounded by air. A cover is mechanically placed over the exposed interconnect islands to protect the integrated circuit from dust particles.Type: GrantFiled: June 24, 1999Date of Patent: March 20, 2001Assignee: International Business Machines CorporationInventor: Uttam Shyamalindu Ghoshal
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Patent number: 6187647Abstract: A method of forming an inductor for a semiconductor device comprises the steps of forming the bottom legs on a first substrate; depositing a second substrate layer over the first substrate; forming the pair of side legs for each loop through the second substrate layer; and, forming top legs connecting pairs of side legs extending from adjacent bottom legs. The step of providing the side legs includes forming a pair of vias through the second substrate layer to the bottom legs, and depositing side legs in the vias. The step of forming the top legs preferably includes forming a channel between the pairs of vias respectively communicating with the adjacent bottom legs, and depositing top legs in the channels. Additionally, the steps of forming the side and top legs are performed concurrently.Type: GrantFiled: October 12, 1999Date of Patent: February 13, 2001Assignee: Lucent Technologies Inc.Inventor: Jerome Tsu-Rong Chu
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Patent number: 6184121Abstract: A method to achieve a very low effective dielectric constant in high performance back end of the line chip interconnect wiring and the resulting multilayer structure are disclosed. The process involves fabricating the multilayer interconnect wiring structure by methods and materials currently known in the state of the art of semiconductor processing; removing the intralevel dielectric between the adjacent metal features by a suitable etching process; applying a thin passivation coating over the exposed etched structure; annealing the etched structure to remove plasma damage; laminating an insulating cover layer to the top surface of the passivated metal features; optionally depositing an insulating environmental barrier layer on top of the cover layer; etching vias in the environmental barrier layer, cover layer and the thin passivation layer for terminal pad contacts; and completing the device by fabricating terminal input/output pads.Type: GrantFiled: July 9, 1998Date of Patent: February 6, 2001Assignee: International Business Machines CorporationInventors: Leena P. Buchwalter, Alessandro Cesare Callegari, Stephan Alan Cohen, Teresita Ordonez Graham, John P. Hummel, Christopher V. Jahnes, Sampath Purushothaman, Katherine Lynn Saenger, Jane Margaret Shaw
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Patent number: 6165890Abstract: A method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce capacitive coupling between electrical elements such as metal lines, wherein a norbornene-type polymer is used as a sacrificial material to occupy a closed interior volume in a semiconductor structure. The sacrificial material is caused to decompose into one or more gaseous decomposition products which are removed, preferably by diffusion, through an overcoat layer. The decomposition of the sacrificial material leaves an air gap or gaps at the closed interior volume previously occupied by the norbornene-type polymer. The air gaps may be disposed between electrical leads to minimize capacitive coupling therebetween.Type: GrantFiled: January 21, 1998Date of Patent: December 26, 2000Assignee: Georgia Tech Research CorporationInventors: Paul A. Kohl, Qiang Zhao, Sue Ann Bidstrup Allen
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Method of fabricating lateral power MOSFET having metal strap layer to reduce distributed resistance
Patent number: 6159841Abstract: To reduce the distributed resistance in an integrated circuit die, a relatively thick metal strap layer is deposited on a bus or other conductive path in the top metal layer. The metal strap layer is formed by etching a longitudinal channel in the passivation layer over the bus and plating a thick metal layer, preferably nickel, in the channel. The metal strap layer dramatically reduces the resistance of the bus.Type: GrantFiled: March 8, 1999Date of Patent: December 12, 2000Assignee: Siliconix incorporatedInventors: Richard K. Williams, Mohammad Kasem -
Patent number: 6159845Abstract: A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.Type: GrantFiled: September 11, 1999Date of Patent: December 12, 2000Assignees: United Microelectronics Corp., United Silicon IncorporatedInventors: Tri-Rung Yew, Water Lur, Hsien-Ta Chung
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Patent number: 6159840Abstract: A fabrication method for a dual damascene structure comprising an air-gap is provided. The method includes forming sequentially a first dielectric layer, a stop layer and a second dielectric layer on a substrate comprising a first metal layer. The first and the second dielectric layers are then defined to form a via. opening exposing the first metal layer and an opening in a predetermined position on the first and second dielectric layers. An oxide layer is then formed on the second dielectric layer covering the opening and forming a gap. The oxide layer and the second dielectric layer are then defined to form a trench, which exposes the first metal layer. A second metal layer and a via plug are then formed in the trench and the via. opening, wherein the second metal layer and the first metal layer are electrically connected through the via plug.Type: GrantFiled: November 12, 1999Date of Patent: December 12, 2000Assignees: United Semiconductor Corp., United Microelectronics Corp.Inventor: Jyh-Ming Wang
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Patent number: 6159842Abstract: A method for fabricating a hybrid low dielectric constant intermetal dielectric layer with improved reliability for multilevel electrical interconnections on integrated circuits is achieved. After forming metal lines for interconnecting the semiconductor devices, a protective insulating layer composed of a low-k fluorine-doped oxide (k=3.5) is deposited. A porous low-k spin-on dielectric layer (k less than 3) is formed in the gaps between the metal lines to further minimize the intralevel capacitance. A more dense low-k dielectric layer, such as FSG, is deposited on the porous layer to provide improved structural mechanical strength and over the metal lines to provide reduced intralevel capacitance. Via holes are etched in the FSG and are filled with metal plugs and the method can be repeated for additional metal levels to complete the multilevel interconnections on the integrated circuit.Type: GrantFiled: January 11, 1999Date of Patent: December 12, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Weng Chang, Yao-Yi Cheng
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Patent number: 6146985Abstract: A semiconductor device having reduced parasitic capacitance and, consequentially increased integrated circuit speed, is achieved by removing sections of dielectric interlayers which do not support conductive patterns, as by anisotropic etching, to form air gaps which can remain or are filled in with a dielectric material having a low dielectric constant. In another embodiment, a conformal dielectric coating is deposited, having a low dielectric constant.Type: GrantFiled: May 4, 1998Date of Patent: November 14, 2000Assignee: Advanced Micro Devices, Inc.Inventor: Donald L. Wollesen
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Patent number: 6143642Abstract: Disclosed is a method for making a programmable structure on a semiconductor substrate. The semiconductor structure has a first dielectric layer. The method includes plasma patterning a first metallization layer over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer. Each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over each of the tungsten plugs is not covered by the second metallization layer. Applying a programming electron dose to a portion of the second metallization layer.Type: GrantFiled: December 22, 1997Date of Patent: November 7, 2000Assignee: VLSI Technology, Inc.Inventors: Harlan Lee Sur, Jr., Subhas Bothra