Forming Contacts Of Differing Depths Into Semiconductor Substrate Patents (Class 438/620)
  • Patent number: 9916901
    Abstract: Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: March 13, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Masanobu Saito, Shuji Tanaka, Shinji Sato
  • Patent number: 9716113
    Abstract: The present invention discloses a conductive structure, a method of manufacturing the conductive structure, and an array substrate. The method of manufacturing the conductive structure, comprising steps of: Forming a barrier metal film and a copper metal film in this order on a substrate, wherein the copper metal film being laminated on the barrier metal film; forming a preset photoresist pattern on the copper metal film; etching the barrier metal film and the copper metal film; oxidizing an exposed sidewall of the etched barrier metal film and an exposed sidewall of the etched copper metal film, so as to generate metal oxide layers on the exposed sidewall of the etched barrier metal film and the exposed sidewall of the etched copper metal film, respectively; and stripping off the photoresist pattern by means of a photoresist stripping liquid.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: July 25, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Binbin Cao, Zhiyuan Lin
  • Patent number: 9478354
    Abstract: An inductor manufacturing method includes a first step of press bonding a Cu foil onto a non-magnetic resin sheet, a second step of forming a conductor pattern by performing etching on the Cu foil, a third step of press bonding another non-magnetic resin sheet onto the conductor pattern, and a via conductor formation step of forming a via conductor that penetrates through the other resin sheet and leads to the conductor pattern. The method further includes a step of forming a body in which resin having magnetism is provided outside of a coil, by press bonding magnetic-powder-containing resin sheets onto a multilayer body, obtained by a manufacturing method including the first to third steps and the via conductor formation step, and then thermally curing the magnetic-powder-containing resin sheets.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: October 25, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hironori Suzuki, Yasushi Takeda, Noriko Shimizu, Yoichi Nakatsuji, Gota Shinohara, Junji Kurobe, Kuniaki Yosui
  • Patent number: 9318611
    Abstract: A thin film transistor includes: a gate electrode and a pair of source and drain electrodes; and a semiconductor layer having a channel formed therein, and having a pair of connection sections connected to the pair of source and drain electrodes, respectively, wherein one or both of opposed surfaces of the pair of connection sections is a non-flat surface.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: April 19, 2016
    Assignee: SONY CORPORATION
    Inventor: Koichi Amari
  • Patent number: 9299603
    Abstract: The present disclosure provides a method for forming a semiconductor device. The method includes forming first conductive layer structures in a first dielectric layer on a substrate; forming a patterned photoresist layer having portions that are each disposed over a respective one of the first conductive layer structures; forming an energy removable film (ERF) on the sidewalls of each of the portions; forming a second dielectric layer over the ERFs, the portions of the patterned photoresist layer, and the first dielectric layer; removing the portions to leave behind a plurality of openings; filling a conductive material in the openings, the conductive material defining second conductive layer structures; forming a ceiling layer over the second conductive layer structures, the ERFs, and the second dielectric layer; and applying energy to the ERFs to partially remove the ERFs on the sidewalls of the portions thereby forming air gaps.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: March 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee
  • Patent number: 9214381
    Abstract: A semiconductor device includes a substrate, a conductive pattern, a side spacer, and an air gap. The substrate includes an interlayer insulating layer and a trench penetrating the interlayer insulating layer. The conductive pattern is disposed within the trench of the substrate. The side spacer is disposed within the trench. The side spacer covers an upper side surface of the conductive pattern. The air gap is disposed within the trench. The air gap is bounded by a sidewall of the trench, the side spacer, and a lower side surface of the conductive pattern. A level of a bottom surface of the conductive pattern is lower than a level of bottom surfaces of the side spacer.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: December 15, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woo-Jin Lee, Sang-Hoon Ahn, Gil-Heyun Choi, Jong-Won Hong
  • Patent number: 9040421
    Abstract: Methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate disposed with a device therein and/or thereon. A contact structure including a barrier layer and a plug metal overlying the barrier layer is formed in electrical contact with the device. A hardmask is formed overlying the contact structure. The method includes performing an etch to form a via opening through the hardmask and to expose the barrier layer and the plug metal. Further, the method removes a remaining portion of the hardmask with a wet etchant, while the contact structure is configured to inhibit the wet etchant from etching the barrier layer. In the method, the via opening is filled with a conductive material to form an interconnect to the contact structure.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: May 26, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Xunyuan Zhang, Xuan Lin, Vimal Kamineni
  • Publication number: 20150140804
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes adjacent storage node contact plugs having different heights, and lower-electrode bowing profiles having different heights, such that a spatial margin between the lower electrodes is assured and a bridge fail is prevented, resulting in improved device operation characteristics. The semiconductor device includes a first storage node contact plug and a second storage node contact plug formed over a semiconductor substrate, wherein the second storage node contact plug is arranged at a height different from that of the first storage node contact plug, and a lower electrode formed over the first storage node contact plug and the second storage node contact plug.
    Type: Application
    Filed: December 19, 2014
    Publication date: May 21, 2015
    Inventor: Sang Ho SOHN
  • Patent number: 9018091
    Abstract: Various methods for forming a low profile assembly are described. The low profile assembly may include an integrated circuit. The integrated circuit as well as components associated with the integrated circuit may be positioned below a surface plane of a printed circuit board in which the integrated circuit is located. The integrated circuit may include bond wires configured to electrically connect the integrated circuits to other components. The low profile assembly may include forming various layers over a substrate and later removing some of the layers.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: April 28, 2015
    Assignee: Apple Inc.
    Inventors: Shawn X. Arnold, Terry L. Gilton, Matthew E. Last
  • Patent number: 9012321
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming a sacrificial film as part of a process of forming a semiconductor device. The sacrificial film has a relatively high etch selectivity with respect to other materials of the semiconductor device so as to reduce loss of etching masks and improve the quality of a components (e.g., buried contacts) of the semiconductor device.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang, Nak-jin Son, Ji-young Kim
  • Patent number: 9006896
    Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure located in the dielectric layer and electrically connected to the device region, wherein the conducting pad structure comprises a stacked structure of a plurality of conducting pad layers; a support layer disposed on a top surface of the conducting pad structure; and a protection layer disposed on the second surface of the semiconductor substrate.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: April 14, 2015
    Assignee: Xintec Inc.
    Inventors: Yu-Lung Huang, Tsang-Yu Liu, Shu-Ming Chang
  • Patent number: 8993433
    Abstract: The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: March 31, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chieh-Te Chen, Yu-Tsung Lai, Hsuan-Hsu Chen, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung
  • Patent number: 8994183
    Abstract: A semiconductor device includes a stacked via structure including a plurality of first vias formed over a substrate, a first interconnect formed on the plurality of first vias, a plurality of second vias formed on the first interconnect, and a second interconnect formed on the plurality of second vias. One of the first vias closest to one end part of the first interconnect and one of the second vias closest to the one end part of the first interconnect at least partially overlap with each other as viewed in the plane, and the first interconnect has a first extension part extending from a position of an end of the first via toward the one end part of the first interconnect and having a length which is more than six times as long as a via width of the first via.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: March 31, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Akihisa Iwasaki, Michiya Takahashi, Akira Ueki, Chikako Chida, Dai Motojima
  • Publication number: 20150069627
    Abstract: In one embodiment, a method of manufacturing an interposer wafer includes forming a first hole having a first depth on a first main surface of a semiconductor wafer. The method further includes forming a second hole having a second depth on the first main surface of the semiconductor wafer before forming the first hole or after forming the first hole, the second depth being shallower than the first depth. The method further includes forming an electrode in the first hole. The method further includes forming an alignment mark in the second hole.
    Type: Application
    Filed: March 14, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenji KOJIMA
  • Patent number: 8969193
    Abstract: A semiconductor substrate (1) is provided on a main surface (14) with an intermetal dielectric (4) including metal planes (5) and on an opposite rear surface (15) with an insulation layer (2) and an electrically conductive connection pad (7). An etch stop layer (6) is applied on the intermetal dielectric to prevent a removal of the intermetal dielectric above the metal planes during subsequent method steps. An opening (9) having a side wall (3) and a bottom (13) is formed from the main surface through the substrate above the connection pad. A side wall spacer (10) is formed on the side wall by a production and subsequent partial removal of a dielectric layer (11). The insulation layer is removed from the bottom to uncover an area of the connection pad. A metal layer is applied in the opening and is provided for an interconnect through the substrate.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: March 3, 2015
    Assignee: ams AG
    Inventors: Jochen Kraft, Franz Schrank, Martin Schrems
  • Patent number: 8962490
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon, wherein at least one metal gate is formed in the ILD layer and at least one source/drain region is adjacent to two sides of the metal gate; forming a first dielectric layer on the ILD layer; forming a second dielectric layer on the first dielectric layer; performing a first etching process to partially remove the second dielectric layer; utilizing a first cleaning agent for performing a first wet clean process; performing a second etching process to partially remove the first dielectric layer; and utilizing a second cleaning agent for performing a second wet clean process, wherein the first cleaning agent is different from the second cleaning agent.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Chih-Sen Huang, Chieh-Te Chen
  • Patent number: 8946074
    Abstract: A method of forming a semiconductor device, comprising: providing a Si-containing layer; forming a barrier layer over said Si-containing layer, said barrier layer comprising a compound including a metallic element; forming a metallic nucleation_seed layer over said barrier layer, said nucleation_seed layer including said metallic element; and forming a metallic interconnect layer over said nucleation_seed layer, wherein said barrier layer and said nucleation_seed layer are formed without exposing said semiconductor device to the ambient atmosphere.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies AG
    Inventor: Heinrich Koerner
  • Publication number: 20140374688
    Abstract: A three-dimensional nonvolatile memory array includes a select layer that selectively connects vertical bit lines to horizontal bit lines. Individual select switches of the select layer include two separately controllable transistors that are connected in series between a horizontal bit line and a vertical bit line. Each transistor in a select switch is connected to a different control circuit by a different select line.
    Type: Application
    Filed: June 24, 2013
    Publication date: December 25, 2014
    Inventors: Ming-Che Wu, Wei-Te Wu, Yung-Tin Chen
  • Patent number: 8906801
    Abstract: Processes for forming integrated circuits and integrated circuits formed thereby are provided in which a first dielectric layer including a first dielectric material is formed on an underlying substrate. A first etch mask having at least two patterned recesses is patterned over the first dielectric layer. At least one first-level via is etched in the first dielectric layer through one patterned recess in the first etch mask with a first etchant, and the first-level via is filled with electrically-conductive material. A second dielectric layer including a second dielectric material is formed over the first dielectric layer. A second etch mask having patterned recesses corresponding to the patterned recesses of the first etch mask is patterned over the second dielectric layer. Second-level vias are etched in the second dielectric layer through the patterned recesses in the second etch mask with a second etchant and exposed to the first etchant.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: December 9, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Ralf Richter, Hans-J├╝rgen Thees
  • Patent number: 8906794
    Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: December 9, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Joachim Patzer, Ardechir Pakfar, Clemens Fitz, Dominic Thurmer
  • Patent number: 8907496
    Abstract: Circuit structures and methods of fabrication are provided with enhanced electrical connection between, for instance, a first metal level and a contact surface of a conductive structure. Enhanced electrical connection is achieved using a plurality of contact vias which are differently-sized, and disposed over and electrically coupled to the contact surface. The differently-sized contact vias include at least one center region contact via disposed over a center region of the contact surface, and at least one peripheral region contact via disposed over a peripheral region of the contact surface, where the at least one center region contact via is larger than the at least one peripheral region contact via.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: December 9, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: GuoXiang Ning, Xiang Hu, Sarasvathi Thangaraju, Paul Ackmann
  • Patent number: 8900996
    Abstract: A method of fabricating a through silicon via (TSV) structure is provided, in which, a first dielectric layer is formed on the substrate, the first dielectric layer is patterned to have at least one first opening, a via hole is formed in the first dielectric layer and the substrate, a second dielectric layer is conformally formed on the first dielectric layer, the second dielectric layer has at least one second opening corresponding to the at least one first opening, and the second dielectric layer covers a sidewall of the via hole. A conductive material layer is formed to fill the via hole and the second opening. The conductive material layer is planarized to form a TSV within the via hole. A TSV structure is also provided, in which, the second dielectric layer is disposed within the first opening and on the sidewall of the via hole.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: December 2, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Yu Chen, Home-Been Cheng, Yu-Han Tsai, Ching-Li Yang
  • Patent number: 8900989
    Abstract: The present disclosure provides a method for forming a semiconductor device. The method includes forming first conductive layer structures in a first dielectric layer on a substrate; forming a patterned photoresist layer having portions that are each disposed over a respective one of the first conductive layer structures; forming an energy removable film (ERF) on the sidewalls of each of the portions; forming a second dielectric layer over the ERFs, the portions of the patterned photoresist layer, and the first dielectric layer; removing the portions to leave behind a plurality of openings; filling a conductive material in the openings, the conductive material defining second conductive layer structures; forming a ceiling layer over the second conductive layer structures, the ERFs, and the second dielectric layer; and applying energy to the ERFs to partially remove the ERFs on the sidewalls of the portions thereby forming air gaps.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee
  • Publication number: 20140349476
    Abstract: The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.
    Type: Application
    Filed: May 27, 2013
    Publication date: November 27, 2014
    Inventors: Chieh-Te Chen, Yu-Tsung Lai, Hsuan-Hsu Chen, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung
  • Patent number: 8883630
    Abstract: A method of forming contact holes includes: forming a first conductive layer and a second conductive layer; forming an insulating layer on the first conductive layer and the second conductive layer; forming a photoresist pattern which exposes first and second etch surfaces of a top surface of the insulating layer; performing a first etching process on the insulating layer at a first etching rate; and performing a second etching process on the insulating layer at a second etching rate which is higher than the first etching rate, after a top surface of the first conductive layer is exposed through the insulating layer. The first etch surface is on the first conductive layer, the second etch surface is on the second conductive layer, and a distance between the second etch surface and the second conductive layer is greater than a distance between the first etch surface and the first conductive layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Yong Jae Jang
  • Patent number: 8871633
    Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 28, 2014
    Assignee: Sony Corporation
    Inventor: Masanaga Fukasawa
  • Patent number: 8828862
    Abstract: A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: David V. Horak, Elbert Huang, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8822328
    Abstract: A method for patterning a semiconductor structure is provided. The method comprises following steps. A first mask defining a first pattern in a first region and a second pattern in a second region adjacent to the first region is provided. The first pattern defined by the first mask is transferred to a first film structure in the first region, and the second pattern defined by the first mask is transferred to the first film structure in the second region. A second film structure is formed on the first film structure. A second mask defining a third pattern in the first region is provided. At least 50% of a part of the first region occupied by the first pattern defined by the first mask is identical with a part of the first region occupied by the third pattern defined by the second mask.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: September 2, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Wei Huang, Ming-Jui Chen, Ting-Cheng Tseng, Ping-I Hsieh
  • Publication number: 20140231894
    Abstract: A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.
    Type: Application
    Filed: April 30, 2014
    Publication date: August 21, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Kunal Parekh, Ceredig Roberts, Thy Tran, Jim Jozwiak, David Hwang
  • Patent number: 8796135
    Abstract: A microelectronic unit includes a microelectronic element, e.g., an integrated circuit chip, having a semiconductor region of monocrystalline form. The semiconductor region has a front surface extending in a first direction, an active circuit element adjacent the front surface, a rear surface remote from the front surface, and a conductive via which extends towards the rear surface. The conductive via can be insulated from the semiconductor region by an inorganic dielectric layer. An opening can extend from the rear surface partially through a thickness of the semiconductor region, with the opening and the conductive via having respective widths in the first direction. The width of the opening may be greater than the width of the conductive via where the opening meets the conductive via.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: August 5, 2014
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Patent number: 8791510
    Abstract: A semiconductor device includes a gate structure on a semiconductor substrate, an impurity region at a side of the gate structure and the impurity region is within the semiconductor substrate, an interlayer insulating layer covering the gate structure and the impurity region, a contact structure extending through the interlayer insulating layer and connected to the impurity region, and an insulating region. The contact structure includes a first contact structure that has a side surface surrounded by the interlayer insulating layer and a second contact structure that has a side surface surrounded by the impurity region. The insulating region is under the second contact structure.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Kyu Lee
  • Patent number: 8785283
    Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: July 22, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Chih-Sen Huang, Ching-Wen Hung, Ching-Pin Hsu
  • Publication number: 20140193973
    Abstract: A method forms interlayer connectors extending to conductive layers of a stack of W conductive layers interleaved with dielectric layers. The stack is etched to expose landing areas at W?1 conductive layers using a set of M etch masks. For each etch mask m, m going from 0 to M?1, there is a first etching step, at least one mask trimming step, and a subsequent etching step following each trimming step. The etch mask may cover Nm+1 of the landing areas and the open etch region may cover Nm of the landing areas. N equals 2 plus the number of trimming steps. The trimming step may be carried out so that the increased size open etch region overlies an additional 1/N of the landing areas. Part of the stack surface may be shielded during the removing step to create dummy areas without contact openings.
    Type: Application
    Filed: January 7, 2013
    Publication date: July 10, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung CHEN
  • Patent number: 8765600
    Abstract: A semiconductor device having a gate on a substrate with source/drain (S/D) regions adjacent to the gate. A first dielectric layer overlays the gate and the S/D regions, the first dielectric layer having first contact holes over the S/D regions with first contact plugs formed of a first material and the first contact plugs coupled to respective S/D regions. A second dielectric layer overlays the first dielectric layer and the first contact plugs. A second contact hole formed in the first and second dielectric layers is filled with a second contact plug formed of a second material. The second contact plug is coupled to the gate and interconnect structures formed in the second dielectric layer, the interconnect structures coupled to the first contact plugs. The second material is different from the first material, and the second material has an electrical resistance lower than that of the first material.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Long Chang, Chih-Ping Chao, Chun-Hung Chen, Hua-Chao Tseng, Jye-Yen Cheng, Harry-Hak-Lay Chuang
  • Patent number: 8765602
    Abstract: A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Daniel C. Edelstein, Tze-man Ko, Andrew H. Simon, Wei-tsu Tseng
  • Publication number: 20140148004
    Abstract: A method of forming contact holes includes: forming a first conductive layer and a second conductive layer; forming an insulating layer on the first conductive layer and the second conductive layer; forming a photoresist pattern which exposes first and second etch surfaces of a top surface of the insulating layer; performing a first etching process on the insulating layer at a first etching rate; and performing a second etching process on the insulating layer at a second etching rate which is higher than the first etching rate, after a top surface of the first conductive layer is exposed through the insulating layer. The first etch surface is on the first conductive layer, the second etch surface is on the second conductive layer, and a distance between the second etch surface and the second conductive layer is greater than a distance between the first etch surface and the first conductive layer.
    Type: Application
    Filed: March 13, 2013
    Publication date: May 29, 2014
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventor: Yong Jae Jang
  • Patent number: 8735279
    Abstract: A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: David V Horak, Elbert Huang, Charles W Koburger, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8728891
    Abstract: Contact openings are produced in a semiconductor body by forming a plurality of self-aligned structures on a main surface of a semiconductor body, each self-aligned structure filling a trench formed in the semiconductor body and extending above and onto the main surface. Adjacent ones of the self-aligned structures have spaced apart sidewalls which face each other. A spacer layer is formed on the sidewalls of the self-aligned structures. Openings are formed in the semiconductor body between adjacent ones of the self-aligned structures while the spacer layer is on the sidewalls of the self-aligned structures. Each opening has a width and a distance to the sidewall of an adjacent trench which corresponds to a thickness of the spacer layer. Self-aligned contact structures can also be produced on a semiconductor body, with or without using the spacer layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: May 20, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Heimo Hofer, Martin Poelzl
  • Patent number: 8722530
    Abstract: A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: May 13, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gregory S. Spencer, Phillip E. Crabtree, Dean J. Denning, Kurt H. Junker, Gerald A. Martin
  • Patent number: 8709937
    Abstract: According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-sun Park, Gil-heyun Choi, Ji-soon Park, Jong-myeong Lee, Jong-won Hong, Hei-seung Kim
  • Patent number: 8685809
    Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Carl J. Radens, Anthony K. Stamper, Jay W. Strane
  • Patent number: 8669176
    Abstract: Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices by performing a copper deposition process to fill the trench or via with copper, which can be performed by fill, plating or electroless deposition. Copper clearing of copper overburden is performed using CMP to stop on an existing liner. Copper in the trenches or vias is recessed by controlled etch. An Nblok cap layer is deposited to cap the trenches or vias so that copper is not exposed to ILD. Nblok overburden and adjacent liner is then removed by CMP. Nblok cap layer is then deposited. The proposed approach is an alternative CMP integration scheme that will eliminate the exposure of copper to ILD during CMP, will prevent any dendrite formation, can be used for all metal layers in BEOL stack, and can be utilized for multiple layers, as necessary, whenever copper CMP is desired.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: March 11, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Kunaljeet Tanwar
  • Patent number: 8647982
    Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: February 11, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, James M. Wark, William M. Hiatt
  • Publication number: 20140021632
    Abstract: A vertical type semiconductor device includes a pillar structure protruding from a top surface of a substrate of a cell array region. Word lines extend while surrounding the pillar structure. Word line contacts contact edges of the word lines functioning as pad portions. An insulating interlayer pattern is provided on the substrate of a peripheral circuit region, which is disposed at an outer peripheral portion of the cell array region. A first contact plug contacts the substrate of the peripheral circuit region. A second contact plug contacts a top surface of the first contact plug and has a top surface aligned on the same plane with the top surfaces of the word line contacts. The first and second contact plugs are stacked in the peripheral circuit region, so the failure of the vertical type semiconductor device is reduced.
    Type: Application
    Filed: April 18, 2013
    Publication date: January 23, 2014
    Inventors: Jae-Goo LEE, Jin-Soo LIM
  • Publication number: 20140021628
    Abstract: A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N?1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W?1 contact openings to create extended contact openings extending to W?1 conductive layers; 2n?1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.
    Type: Application
    Filed: September 7, 2012
    Publication date: January 23, 2014
    Applicant: Macronix International Co., Ltd.
    Inventors: Yen-Hao Shih, Shih-Hung Chen, Teng-Hao Yeh, Chih-Wei Hu, Feng-Nien Tsai, Lo-Yueh Lin
  • Patent number: 8633099
    Abstract: A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N?1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W?1 contact openings to create extended contact openings extending to W?1 conductive layers; 2n?1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: January 21, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Yen-Hao Shih, Shih-Hung Chen, Teng-Hao Yeh, Chih-Wei Hu, Feng-Nien Tsai, Lo-Yueh Lin
  • Patent number: 8633591
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: January 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Patent number: 8629060
    Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: January 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Dave Pratt, Andy Perkins
  • Patent number: 8592303
    Abstract: There are provided with a wiring structure and a method for manufacturing the same wherein in a wiring structure of multi-layered wiring in which a metal wiring is formed on a substrate forming a semiconductor element thereby obtaining connection of the element, no damage to insulation property between the abutting wirings by occurrence of leakage current and no deterioration of insulation resistance property between the abutting wirings are achieved in case that fine metal wiring is formed in a porous insulation film. The insulation barrier layer 413 is formed between an interlayer insulation film and the metal wiring, in the metal wiring structure on the substrate forming the semiconductor element. The insulation barrier layer enables to reduce leakage current between the abutting wirings and to elevate the insulation credibility.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: November 26, 2013
    Assignees: Renesas Electronics Corporation, NEC Corporation
    Inventors: Munehiro Tada, Yoshihiro Hayashi, Yoshimichi Harada, Fuminori Ito, Hiroto Ohtake, Tatsuya Usami
  • Patent number: 8592302
    Abstract: A patterning method is provided for fabrication of a semiconductor device structure having conductive contact elements, an interlayer dielectric material overlying the contact elements, an organic planarization layer overlying the interlayer dielectric material, an antireflective coating material overlying the organic planarization layer, and a photoresist material overlying the antireflective coating material. The method creates a patterned photoresist layer from the photoresist material to define oversized openings corresponding to respective conductive contact elements. The antireflective coating is etched using the patterned photoresist as an etch mask. A liner material is deposited overlying the patterned antireflective coating layer. The liner material is etched to create sidewall features, which are used as a portion of an etch mask to form contact recesses for the conductive contact elements.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: November 26, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Erik P. Geiss, Peter Baars