Abstract: A method for manufacturing a semiconductor device includes forming a second storage node contact hole with a mask for storage node and securing an overlay margin between a storage node contact hole and a storage node with a hard mask layer that serves as a hard mask as well as an anti-reflection film to reduce contact resistance, prevent reduction of a line-width of a lower interlayer insulating film and eliminate processes for depositing the interlayer insulating film and a polysilicon layer and etching the polysilicon layer to reduce a production period and cost of products.

Abstract: Disclosed is a method for forming a metal interconnection in a semiconductor device. In a damascene process, a capping barrier metal layer is formed generally only on a lower metal interconnection in order to prevent the diffusion of atoms from the lower metal interconnection into an upper dielectric layer. The capping barrier metal layer prevents the increase of an effective dielectric constant of a lower inter-metal dielectric layer that surrounds the lower metal interconnection, and may reduce the resistance of the metal interconnection, thereby improving the reliability, speed and/or other characteristics of the semiconductor device.

Abstract: A display substrate having a fan-out and a method for manufacturing the display substrate are disclosed. The fan-out includes an insulating substrate, a first line, a second line, a resistance control pattern, and first and second detour pattern. The first line is disposed on the insulating substrate and is connected to a pad. The second line is formed from the same layer as the first line and is connected to a thin-film transistor (TFT). The resistance control pattern is formed from a different layer than the first and second lines. The first and second detour patterns are formed from a different layer than the first and second lines and the resistance control pattern, and connect the first and second lines with the resistance control pattern, respectively.

Abstract: A semiconductor device includes a semiconductor substrate with a pattern region and a dummy region, an interlayer dielectric film arranged on the semiconductor substrate, a semiconductor layer pattern arranged on the interlayer dielectric film in the pattern region, a dummy pattern arranged on the interlayer dielectric film in the dummy region, a contact plug arranged inside the interlayer dielectric film, and the contact plug connecting the semiconductor layer pattern to the semiconductor substrate, and a dummy plug arranged inside the interlayer dielectric film, the dummy plug corresponding to the dummy pattern. A method for fabricating the semiconductor device includes forming these structures.

Abstract: A method and apparatus for producing a substrate having a plurality of substantially co-planar bonding pads is provided. The substrate is employed in a probe apparatus used in wafer testing of wafer-mounted semiconductor integrated circuits. The bonding pads are formed by applying a plurality of bumps of electrically conductive material to a mounting surface of the substrate using a dispensing mechanism. The bumps are subsequently deformed into a plurality of substantially co-planar bonding pads using a flattening tool. The bonding pads provide a planar surface to which probes may be mounted, improving the accuracy and precision of positioning of tips of the probes.

Abstract: A method for fabricating a semiconductor device comprises the steps of: forming interconnection grooves 38 in an inter-layer insulation film 34; forming an interconnection layer 44 of Cu as the main material in the interconnection grooves 38; and concurrently injecting nitrogen gas and water to the surface of the interconnection layer 44 buried in the interconnection groove 38.

Abstract: An integrated circuit structure including multiple thin film resistors having different sheet resistances and TCRs includes a first oxide layer (2) formed on a semiconductor substrate (1), a first thin film resistor (3) disposed on the first oxide layer (2), and a second oxide layer (14) disposed over the first oxide layer (2) and first thin film resistor (3). A second thin film resistor (15) is formed on the second oxide layer (14) and a third oxide layer (16) is formed over the second thin film resistor (15) and the second oxide layer (14). Interconnect metallization elements (12A,B & 22A,B) disposed on at least one of the second (14) and third (16) oxide layers electrically contact the circuit element (4), terminals of the first thin film resistor (3), and terminals of the second thin film resistor (15), respectively, through corresponding contact openings through at least one of the second (14) and third (16) oxide layers.

Abstract: Embodiments in accordance with the present invention relate to structures and methods allowing stress-induced electromigration to be tested in multiple interconnect metallization layers. An embodiment of a testing structure in accordance with the present invention comprises at least two segments of a different metal layer through via structures. Each segment includes nodes configured to receive force and sense voltages. Selective application of force and sense voltages to these nodes allows rapid and precise detection of stress-induced immigration in each of the metal layers.

Abstract: A method of forming substrates, e.g., silicon on insulator, silicon on silicon. The method includes providing a donor substrate, e.g., silicon wafer. The method also includes forming a cleave layer on the donor substrate that contains the cleave plane, the plane of eventual separation. In a specific embodiment, the cleave layer comprising silicon germanium. The method also includes forming a device layer (e.g., epitaxial silicon) on the cleave layer. The method also includes introducing particles into the cleave layer to add stress in the cleave layer. The particles within the cleave layer are then redistributed to form a high concentration region of the particles in the vicinity of the cleave plane, where the redistribution of the particles is carried out in a manner substantially free from microbubble or microcavity formation of the particles in the cleave plane. That is, the particles are generally at a low dose, which is defined herein as a lack of microbubble or microcavity formation in the cleave plane.

Abstract: A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.

Abstract: A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.

Abstract: The invention is aimed to prevent that fall of characteristic of a solar battery and producing yield caused by particles of powder condition generating from working part at laser beam process in the method producing the solar battery by laser beam process. The constitution of the invention is characterized by comprising: a first step forming the lower electrode and the semiconductor layer on the insulating substrate by laminating; a second step forming a protective film on surface of the semiconductor; a third step forming an opening portion at the semiconductor layer, or the semiconductor layer and the lower electrode by laser beam process after the second step; and a fourth step removing the protective film.

Abstract: A multilayer interconnection structure is formed by a method comprising the steps of: Forming a low dielectric constant film on a substrate, curing the low dielectric constant film by irradiating it with UV light, laminating a UV blocking film, laminating a next low dielectric constant film, and curing the next low dielectric constant film by irradiating it with UV light.

Abstract: A method for fabricating a semiconductor device is described. The method includes providing a substrate having a trench therein, and a trench device in the trench. The trench device includes two gate structures disposed on the sidewalls of the trench, a doped region in the substrate between the gate structures and an inter-gate dielectric layer disposed on the surface of the gate structures. A thermal treatment process in a nitrogen-containing ambient is performed to remove the native oxide layer formed on the surface of the doped region. Then, a conductive layer is formed to fill in the trench.

Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.

Abstract: In order to form a contact in a layer on a substrate, in particular a contact in a logic circuit in a semiconductor component, the mask layer is structured for etching of the contact holes with a photoresist layer which is exposed using two masks, with the first mask containing a regular pattern of contact structures with a period which corresponds to the order of magnitude of twice the edge length of the contact hole, and with the second mask containing a pattern with a structure which surrounds at least the contact hole area, and thus covers it.

Abstract: A block film is formed on a region which includes a region of an insulating layer where a first hole is to be formed, and in which no second hole is to be formed, and a resist film having openings for forming the first and second holes is formed on the block film and insulating layer. Etching is performed by using the resist film as a mask, thereby forming the first hole in the block film and insulating layer, and the second hole in the insulating layer. The depth of the first hole from the upper surface of the insulating layer is smaller than that of the second hole, so the first hole does not reach the semiconductor substrate.

Abstract: Provided are transistors, semiconductor integrated circuit interconnections and methods of forming the same. The transistors, semiconductor integrated circuit interconnections and methods of forming the same may improve electrical characteristics between gate electrodes or interconnection electrodes and simplify a semiconductor fabrication process related to gate electrodes or interconnection electrodes. A material layer having first and second regions may be prepared. A trench may be formed in a selected portion of the first region. Transistors or semiconductor integrated circuit interconnections may be in the first and second regions, respectively. One of the transistors or the semiconductor integrated circuit interconnections may be formed in the trench. The transistors or the semiconductor integrated circuit interconnections may be electrically insulated from each other.

Abstract: A semiconductor device and a fabricating method thereof are provided. A PMD layer and at least one IMD layer are formed on a semiconductor substrate. A through-electrode penetrates through the PMD layer and the IMD layer, and a connecting electrode connects to the through-electrode.

Abstract: A semiconductor device and a fabricating method thereof are provided. A PMD layer is formed on a semiconductor substrate, and at least one IMD layer is formed on the PMD layer. A through-electrode penetrates through the semiconductor substrate, the PMD layer, and each IMD layer, and a heat emission wiring is formed on an underside of the semiconductor substrate.

Abstract: A semiconductor device and method for manufacturing the same are provided, capable of narrowing feature size by utilizing the property of oxidation of a material. In one method, a polysilicon layer can be patterned into a fine pattern up to a critical dimension using a photolithography process. Then the patterned polysilicon layer can be oxidized, thereby narrowing the gap between adjacent polysilicon patterns and narrowing the polysilicon patterns through the oxidation process. The narrowed polysilicon patterns and/or the narrowed gap between adjacent polysilicon patterns can be used to form vias or trenches in the substrate (or layer) below the polysilicon layer having a width narrower than the critical dimension.

Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.

Abstract: The semiconductor device is capable of coping with speedup of operation using a low dielectric constant material film other than silicon. The base (10) formed by the substrate (11) and the low dielectric constant material film (12) whose relative dielectric constant is lower than silicon is provided. The semiconductor element layer including the MOS transistor (30) is adhered onto the surface of the base (10) for stacking. The transistor (30) is formed by using the island-shaped single-crystal Si film (31) and buried in the insulator films (15), (16) and (17). The multilayer wiring structure (18) is formed on the semiconductor element layer and is electrically connected to the transistor (30). The electrode (20) functioning as a return path for the signals is formed on the back surface of the base (10). Instead of forming the electrode (20) on the base (10), the electrodes (20A) may be arranged on the back surface of the base (10A), configuring the base (10A) as an interposer.

Abstract: A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the conductive layer into a plurality of wire bond pads spaced apart; and forming a protective dielectric layer on the top surface of the substrate in spaces between adjacent wire bond pads, top surfaces of the dielectric layer in the spaces coplanar with coplanar top surfaces of the wire bond pads.

Abstract: The present invention provides an electronic device having high insulating reliability, in which metal portions of a circuit are not electrically conductive with each other via an adhesive layer even when the electronic device is used in high-temperature low-humidity conditions or high-temperature high-humidity conditions, and provides a production method for the electronic device, and a semiconductor device comprising the electronic device. In the electronic device in which a circuit formed by pattern formation of metal portions is attached via an adhesive layer to an insulating base, the adhesive layer, which contacts adjacent metal portions, is divided. Typically, the electronic device is one of a lead frame having a lead frame fixing tape, a TAB tape, and a flexible printed circuit board.

Abstract: A method to form a vertical interconnect advantageous for high-density semiconductor devices. A conductive etch stop layer, preferably of cobalt silicide, is formed. The etch stop layer may be in the form of patterned lines or wires. A layer of contact material is formed on and in contact with the etch stop layer. The layer of contact material is patterned to form posts. Dielectric is deposited over and between the posts, then the dielectric planarized to expose the tops of the posts. The posts can serve as vertical interconnects which electrically connect a next conductive layer formed on and in contact with the vertical interconnects with the underlying etch stop layer. The patterned dimension of vertical interconnects formed according to the present invention can be substantially the same as the minimum feature size, even at very small minimum feature size.

Abstract: An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.

Abstract: A method to form a very low resistivity interconnection in the manufacture of an integrated circuit device is achieved. A bottom conductive layer is formed overlying a substrate. The bottom conductive layer creates a first electrical coupling of a first location and a second location of the integrated circuit device. A dielectric layer is formed overlying the bottom conductive layer. A top conductive layer is formed overlying the dielectric layer. The top conductive layer is coupled to the bottom conductive layer through openings in the dielectric layer to form a second electrical coupling of the first location and the second location. A metal wire is bonded to the top conductive layer to form a third electrical coupling of the first location and the second location to complete the very low resistivity interconnection in the manufacture of the integrated circuit device.

Abstract: A method of manufacturing a semiconductor integrated circuit device is provided including forming a first insulating film comprised of fluorine-containing silicon oxide over a main surface of a semiconductor substrate is formed together with forming a second insulating film comprising silicon oxide as a major component, forming a third insulating film comprising silicon carbide as a major component, and forming a fourth insulating film comprised of fluorine-containing silicon oxide. The fourth insulating film is removed at a wiring groove-forming region thereof by dry etching using a first photoresist film as a mask. A first conductive layer is buried inside the wiring groove and the first conductive layer is removed from outside of the wiring groove by a chemical mechanical polishing method, thereby forming a first wiring including the first conductive layer inside the wiring groove.

Abstract: A method of depositing conformal film into high aspect ratio spaces includes the step of forming a gradient of precursor gas inside the space(s) prior to deposition. The gradient may be formed, for example, by reducing the pressure within the deposition chamber or by partial evacuation of the deposition chamber. The temperature of the substrate is then briefly increased to preferentially deposit precursor material within the closed or “deep” portion of the high aspect ratio space. The process may be repeated for a number of cycles to completely fill the space(s). The process permits the filling of high aspect ratio spaces without any voids or keyholes that may adversely impact the performance of the resulting device.

Abstract: Methods for forming a redistribution layer on microfeature workpieces, and microfeature workpieces having such a redistribution layer are disclosed herein. In one embodiment, a method includes constructing a dielectric structure on a microfeature workpiece having a substrate and a terminal carried by the substrate, and removing a section of the dielectric structure to form an opening. The opening has a first portion extending through the dielectric structure and exposing the terminal and a second portion extending to an intermediate depth in the dielectric structure. The second portion is spaced laterally apart from the terminal. The method further includes forming a conductive layer on the microfeature workpiece with the conductive layer in electrical contact with the terminal and disposed in the first and second portions of the opening.

Abstract: A liquid crystal display device comprises at least two insulating layers formed on a first conductive layer, a second conductive layer formed between the at least two insulating layers, a first contact hole penetrating an upper insulating layer of the at least two insulating layers on the second conductive layer, a second contact hole penetrating the at least two insulating layers and exposing a portion of the first conductive layer, and a contact part comprising a bridge electrode formed of a third conductive layer for connecting the first and second conductive layers through the first and second contact holes. The second contact hole comprises an internal hole penetrating the at least two insulating layers and an external hole surrounding the internal hole forming in the upper insulating layers.

Abstract: In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts.

Abstract: Tails (20) projecting from an electrical component (12) that lies on a circuit board surface, are terminated to traces on a multi-layer circuit board (14) in a manner that minimizes the disadvantages of long through hole soldering and of surface mount techniques. A blind hole is drilled and plated to form a shallow well (70). The well is filled with a soldering composition (130). A tail (20) is projected downward into the soldering composition with the extreme tip of the tail lying above the bottom of the hole, and the soldering composition is heated to solder the tail to the hole plating.

Abstract: The present invention provides methods of forming cobalt layers on a structure comprising forming a preliminary cobalt layer on a semiconductor substrate by introducing an organic metal precursor onto the semiconductor substrate and treating a surface of the preliminary cobalt layer under an atmosphere of a hydrogen-containing gas to remove impurities contained in the preliminary cobalt layer. Compositions of cobalt layers are also provided. Further provided are semiconductor devices comprising cobalt layers provided herein.

Abstract: Circuit edits may be performed through the back side of an integrated circuit die. In one embodiment, a circuit edit is achieved by exposing first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die from the back side. An insulating layer is not deposited over the first and second circuit edit connection targets and the exposed semiconductor substrate. Next, a conductor is deposited over the circuit edit connection targets from the back side of the integrated circuit to couple together the circuit edit connection targets.

Abstract: A method for fabricating dual damascene structures having improved IC performance and reduced RC delay characteristics is provided. In one embodiment, a substrate with an etch stop layer formed thereon is provided. A dielectric layer is formed on the etch stop layer and an anti-reflective coating layer is formed on the dielectric layer. A first patterned photoresist layer having a via hole pattern is formed on the anti-reflective coating layer. The via hole pattern is thereafter etched through the anti-reflective coating layer, the dielectric layer, and the etch stop layer to form a via hole. A sacrificial via fill layer is filled in the via hole. A second patterned photoresist layer having a trench pattern is formed above the sacrificial via fill layer. The trench pattern is etched into the sacrificial via fill layer, the anti-reflective coating layer, and the dielectric layer to form a trench. The sacrificial via fill layer is removed in the via hole.

Abstract: The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed by etching a portion of the substrate disposed in the contact junction region with a predetermined thickness; a dopant diffusion barrier layer formed on sidewalls of the trench; and a contact plug filled into a space created between the gate structures and inside of the trench, wherein the dopant diffusion barrier layer prevents dopants within the contact plug from diffusing out.

Abstract: A method of fabricating dual damascene interconnections is provided. A dual damascene region is formed in a hybrid dielectric layer having a dielectric constant of 3.3 or less, and a carbon-free inorganic material is used as a via filler. The present invention improves electrical properties of dual damascene interconnections and minimizes defects.

Abstract: An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.

Abstract: A method of manufacturing a semiconductor device, including the steps of: forming first and second insulation films on a substrate; sequentially forming an organic sacrificing layer and first and second mask layers thereon; forming a wiring groove pattern in the second mask layer; forming a connection hole pattern for forming connection holes in the second and first mask layers and the organic sacrificing layer; forming a wiring groove pattern in the first mask layer and the organic sacrificing layer and forming the connection holes in the second insulation film, by etching conducted by use of the second and first mask layers as an etching mask; and forming the wiring grooves in the second insulation film and forming the connection holes in the second and first insulation films, by use of the first mask layer and the organic sacrificing layer as a mask.

Abstract: An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.

Abstract: An inventive leadframe includes an outer frame, a die pad, and a plurality of leads each having land portions and connections. The land portions each have an upper surface serving as a bonding pad to be connected with a metal wiring, and a lowermost part serving as an external terminal. The connections are each devoid of its lower part so as to be thinner than the land portion, and are provided between the outer frame and the land portions, between the land portions associated with each other in each lead, and between the land portions and the die pad. Furthermore, the inventive leadframe is provided with no member that functions as a suspension lead for connecting the outer frame and the die pad to each other during plastic encapsulation.

Abstract: A semiconductor chip production method including the steps of: forming a front side recess in a semiconductor substrate; depositing a metal material in the front side recess to form a front side electrode electrically connected to a functional device formed on the front surface; removing a rear surface portion of the semiconductor substrate to reduce the thickness of the semiconductor substrate to a thickness greater than the depth of the front side recess; forming a rear side recess communicating with the front side recess in the rear surface of the semiconductor substrate after the thickness reducing step; and depositing a metal material in the rear side recess to form a rear side electrode electrically connected to the front side electrode for formation of a through-electrode.

Abstract: A method of manufacturing an integrated circuit on a semiconductor wafer. The method comprising forming a bottom plate of a capacitor 50a and a bottom portion of an induction coil 50a, forming an etch stop layer 250?, forming a ferromagnetic capacitor top plate 20a and a ferromagnetic core 20b, forming a top portion of the induction coil 50b plus vias 50c that couple the top portion of the induction coil 50b to the bottom portion of the induction coil 50c.

Abstract: A method for forming a storage node contact plug of a dynamic random access memory includes forming insulating layers on an overall surface of a semiconductor substrate having a plurality of buried contact plugs, etching the insulating layers down to a top surface of the buried contact plugs to form first contact holes on the buried contact plugs, forming a photoresist pattern on the insulating layers and the first contact holes, etching the insulating layers to form second contact holes on the second insulating layer, and filling the first and second contact holes with conductive material.

Abstract: Disclosed are a contact plug in a semiconductor device and method of forming the same. After a junction region where a contact plug is formed upwardly up to the bottom of a metal wire, the raised junction region and the metal wire are connected by a contact plug. Or after a first contact plug of the same area is formed on the junction region up to the bottom of the metal wires, the first contact plug is connected by a second contact plug. Thus, the width of the contact plug except for some portions is increased by maximum. It is thus possible to prevent an electric field from being concentrated and prohibit on-current from reduced, thus improving the electrical properties of devices.

Abstract: Atomic layers can be formed by introducing a tantalum amine derivative reactant onto a substrate, wherein the tantalum amine derivative has a formula: Ta(NR1)(NR2R3)3, wherein R1, R2 and R3 are each independently H or a C1–C6 alkyl functional group, chemisorbing a portion of the reactant on the substrate, removing non-chemisorbed reactant from the substrate and introducing a reacting gas onto the substrate to form a solid material on the substrate. Thin films comprising tantalum nitride (TaN) are also provided.

Abstract: Methods of electroless filling electrically different features such as contact openings to form interconnects and conductive contacts, and semiconductor devices, dies, and systems that incorporate the interconnects and contacts are disclosed. The contact openings are electrically shorted together with a selective material, a nucleation layer is selectively deposited onto the area to be plated (e.g., the base of the opening), and a conductive material is electroless plated onto the nucleation layer to fill the opening. The process achieves substantially simultaneous filling of openings having different surface potentials at an about even rate.

Abstract: An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.