Abstract: A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.

Abstract: A multi-step system and method for curing a dielectric film in which the system includes a drying system configured to reduce the amount of contaminants, such as moisture, in the dielectric film. The system further includes a curing system coupled to the drying system, and configured to treat the dielectric film with ultraviolet (UV) radiation and infrared (IR) radiation in order to cure the dielectric film.

Abstract: A method of fabricating a semiconductor memory device and a structure that forms both a resistor and an etching protection layer to reduce a contact resistance. The method of fabricating a semiconductor memory device according to the invention includes forming an insulation layer on a semiconductor substrate having a cell array region, a core region, and a peripheral region, each having at least one transistor formed therein, and forming both a first landing pad in the core region on the insulation layer and a second landing pad in the peripheral region, the first landing pad being overlapped with a part of a first conductive line. The invention reduces the contact resistance and prevents or minimizes a device failure caused by a misalignment, with the simplified process.

Abstract: Methods of patterning features, methods of patterning material layers of semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a method of patterning features includes providing a workpiece having a material layer disposed thereon. A hard mask is formed over the material layer. A first pattern is formed in an upper portion of the hard mask, and a second pattern is formed in the upper portion of the hard mask. The first pattern and the second pattern are formed in a lower portion of the hard mask and the material layer, forming the features in the material layer.

Abstract: A method of manufacturing a semiconductor device. In this method, a concave portion is formed in one surface in the thickness direction of a primary base plate comprising a semiconductor substrate with a relatively large thickness dimension. Then, through-holes are formed by a reactive-ion etching process using as a mask an opening formed in an oxide film provided on the other surface in the thickness direction of the primary base plate. The opening has a narrow width in a region corresponding to the concave portion and a wide width in the remaining region. Thus, respective times necessary for the wide-width through-hole to penetrate through the primary base plate and necessary for the narrow-width through-hole to reach a bottom surface of the concave portion can be approximately equalized to complete the common etching process of the wide-width through-hole and the narrow-width through-hole approximately simultaneously.

Abstract: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.

Abstract: A method for fabricating a semiconductor device includes preparing a substrate comprising a first surface and a second surface formed at a lower position than the first surface, forming an insulation layer over the substrate, etching the insulation layer to form a first contact hole exposing the first surface and a second contact hole having a larger depth than the first contact hole above the second surface, forming a first sacrificial layer over the insulation layer, the first contact hole, and the second contact hole, forming a second sacrificial layer over the substrate structure and filled in the first contact hole, exposing the first sacrificial layer at a bottom surface of the second contact hole while having the second sacrificial layer remain in the first contact hole, etching the first sacrificial layer, and etching the remaining insulation layer to expose the second surface.

Abstract: It is an object of the present invention to provide a method for manufacturing a highly reliable semiconductor device with preferable yield. In the invention, two-step etching is performed when selectively removing an interlayer insulating film with at least two layers constituting a semiconductor device, and forming an opening. One feature of the invention is that at least either one of a first gas (a first etching gas) and a second gas (a second etching gas) used at the time of the two-step etching is added with an inert gas.

Abstract: A pattern having exceptionally small features is formed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern comprises features formed by self-organizing material, such as diblock copolymers. The organization of the copolymers is directed by spacers which have been formed by a pitch multiplication process in which spacers are formed at the sides of sacrificial mandrels, which are later removed to leave spaced-apart, free-standing spacers. Diblock copolymers, composed of two immiscible block species, are deposited over and in the space between the spacers. The copolymers are made to self-organize, with each block species aggregating with other block species of the same type.

Abstract: A semiconductor structure and methods of making the same. The semiconductor structure includes a substrate having a silicide region disposed above a doped region, and a metal contact extending through the silicide region and being in direct contact with the doped region.

Abstract: A pattern formation method includes the steps of forming a flowable film made of a material with flowability; forming at least one of a concave portion and a convex portion provided on a pressing face of a pressing member onto the flowable film by pressing the pressing member against the flowable film; forming a solidified film by solidifying the flowable film, onto which the at least one of a concave portion and a convex portion has been transferred, through annealing at a first temperature with the pressing member pressed against the flowable film; and forming a pattern made of the solidified film burnt by annealing at a second temperature higher than the first temperature.

Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter Of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

Abstract: To make a metal feature, a non-plateable layer is applied to a workpiece surface and then patterned to form a first plating region and a first non-plating region. Then, metal is deposited on the workpiece to form a raised field region in said first plating region and a recessed region in said first non-plating region. Then, an accelerator film is applied globally on the workpiece. A portion of the accelerator film is selectively removed from the field region, and another portion of the accelerator film remains in the recessed acceleration region. Then, metal is deposited onto the workpiece, and the metal deposits at an accelerated rate in the acceleration region, resulting in a greater thickness of metal in the acceleration region compared to metal in the non-activated field region. Then, metal is completely removed from the field region, thereby forming the metal feature.

Abstract: Methods of forming a gas dielectric structure for a semiconductor structure by using a sacrificial layer. In particular, one embodiment of the invention includes forming an opening for semiconductor structure in a dielectric layer on a substrate; depositing a sacrificial layer over the opening; performing a directional etch on the sacrificial layer to form a sacrificial layer sidewall on the opening; depositing a conductive liner over the opening; depositing a metal in the opening; planarizing the metal and the conductive liner; removing the sacrificial layer sidewall to form a void; and depositing a cap layer over the void to form the gas dielectric structure. The invention is easily implemented in damascene wire formation processes, and improves structural stability.

Abstract: A method for forming a contact hole of a semiconductor device includes: forming a lower pattern over a substrate; forming a spin-on-glass (SOG) layer over the lower pattern; performing a first curing process on the SOG layer; forming an opening exposing a portion of the SOG layer; performing a second curing process on the SOG layer corresponding to a lower portion of the opening; and forming a contact hole exposing the lower pattern.

Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.

Abstract: A method for symmetric deposition of metal layer over a metal layer registration key comprises using MOCVD to form the metal layer. Once the symmetric metal layer is formed, a metal layer registration key can be accurately detected and the metal layer registration key overlay shift can be improved.

Abstract: A method of forming a metal-oxide-semiconductor (MOS) transistor device is provided. First, a semiconductor substrate is prepared. Subsequently, a gate structure is formed on the semiconductor substrate. The gate structure includes a first strip portion and a second strip portion that is not parallel to the first strip portion. The gate structure further includes a junction between the first strip portion and the second strip portion. Thereafter, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure. Next, a portion of the stressed cap layer is removed to expose the junction between the first strip portion and the second strip portion.

Abstract: An electrical structure including a first substrate comprising a plurality of electrical components, a first thermally conductive film layer formed over and in contact with a first electrical component of the plurality of electrical components, a first thermally conductive structure in mechanical contact with a first portion of the first thermally conductive film layer, and a first thermal energy extraction structure formed over the first thermally conductive structure. The first thermal energy extraction structure is in thermal contact with the first thermally conductive structure. The first thermal energy extraction structure is configured to extract a first portion of thermal energy from the first electrical component through the first thermally conductive film layer and the first thermally conductive structure.

Abstract: A method for forming a dielectric cap layer over an interconnect layer formed by a back-end-of-the-line (BEOL) interconnect process, the interconnect process including: lithography, reactive ion etching (RIE), metal filling of BEOL conductors, and chemical-mechanical polishing (CMP), wherein a sacrificial material resides between conductors of the interconnect layer, and wherein the dielectric cap layer is made porous through an oxidation process.

Abstract: A method performed on a semiconductor chip having a doped semiconductor material abutting a substrate involves creating a first via through at least a portion of the substrate extending from an outer side of the substrate towards the doped semiconductor material, the first via having a wall surface and a bottom, introducing a first electrically conductive material into the first via so as to create an electrically conductive path, creating a second via, aligned with the first via, extending from an outer surface of the doped portion of the semiconductor chip to the bottom, and introducing a second electrically conductive material into the second via so as to create an electrically conductive path.

Abstract: Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a pre-existing semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes.

Abstract: A method for manufacturing a substrate of a TFT LCD device is disclosed with following steps: providing a transparent substrate having a thin film transistors area and a storing capacitor area; forming an aluminum metal layer and a metal protecting layer on the substrate; patterning a first pattern on the aluminum metal layer of the TFT area, and a second pattern on the metal protecting layer of the storing capacitor area through a halftone mask; forming an aluminum nitride layer on the patterned metal protecting layer; removing the aluminum nitride layer form a rugged surface; forming patterned gates, patterned sources, and patterned drains over the patterned metal protecting layer of the TFT area, and forming a second metal layer over the rugged surface of the aluminum layer on the storing capacitor area, wherein the second metal layer is electrically connected with the drains; and forming patterned pixel electrodes.

Abstract: An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the overlying line opening, nor does it introduce damages caused by Ar sputtering into the dielectric material including the via and line openings. In accordance with the present invention, such an interconnect structure contains a diffusion barrier layer only within the via opening, but not in the overlying line opening. This feature enhances both mechanical strength and diffusion property around the via opening areas without decreasing volume fraction of conductor inside the line openings.

Abstract: Methods for forming a contact hole in a semiconductor device are provided. An exposed portion of an isolation layer, which may be generated during a process of forming a borderless contact hole, can be covered with a material similar to that of the substrate.

Abstract: The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality of interconnect layers contains an impurity, and the wider the interconnect in the at least one interconnect layer is, the higher concentration of the impurity the interconnect contains.

Abstract: A method for fabricating a 3-D monolithic memory device in which a via and trench are etched using an amorphous carbon hard mask. The via extends in multiple levels of the device as a multi-level vertical interconnect. The trench extends laterally, such as to provide a word line or bit line for memory cells, or to provide other routing paths. A dual damascene process can be used in which the via is formed first and the trench is formed second, or the trench is formed first and the via is formed second. The technique is particularly suitable for deep via applications, such as for via depths of greater than 1 ?m. A dielectric antireflective coating, optionally with a bottom antireflective coating, can be used to etch an amorphous carbon layer to provide the amorphous carbon hard mask.

Abstract: A layered capacitor structure comprises two or more semiconductor/dielectric plates formed above an insulating surface which provides mechanical support, with the plates arranged in a vertical stack on the insulating surface. An insulating layer is on each plate, patterned and etched to provide an opening which allows the top of one plate to be in physical and electrical contact with the bottom of the subsequent plate. Contact openings are provided through the insulating layers, each of which provides access to a respective semiconductor layer and is insulated from any other semiconductor/dielectric plate. Electrical contacts through the contact openings provide electrical connections to respective semiconductor layers. The present structure can include as many stacked layers as needed to provide a desired total capacitance or range of capacitances.

Abstract: A method and apparatus for forming connections within a semiconductor device is disclosed. The semiconductor device incorporates a contact bridge between transistor contacts in close proximity. The contact bridge comprises a plurality of metal pillars each having a lower end in electrical contact with first and second transistor elements, respectively; one or more intermediate metal pillars disposed between and in electrical contact with an upper end of the metal pillars; and one or more separation regions of dielectric disposed below the intermediate metal pillar and between the lower ends of the first and second metal pillars.

Abstract: Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

Abstract: A pattern that includes trenches of different depths is formed on a substrate using nanoimprint lithography. A subsequent metal deposition forms lines of different thicknesses according to trench depth, from a single metal layer. Vias extending down from lines are also formed from the same layer. Individual bit lines are formed having different thicknesses at different locations.

Abstract: Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in the integrated circuit and forming electrically conductive interconnect lines in the integrated circuit after formation of the tungsten plugs. At least one tungsten plug is electrically connected to at least one electrically conductive interconnect line. Thereafter at least one electrically conductive interconnect line is exposed to ionized air.

Abstract: A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is conformally deposited over the contact points, and a second material layer is deposited. A photoresist layer is applied and patterned to leave remaining portions. The remaining portions are trimmed to produce trimmed remaining portions which overlie eventual contact holes to the contact points. Using the trimmed remaining portions as an etch mask, exposed portions the second material layer are etched away to leave sacrificial plugs. The sacrificial plugs are etched away to form contact holes that reach portions the first material layers. Another etching step is performed to extend the contact holes to produce final contact holes that extend to the contact points.

Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.

Abstract: A structure and a method for preventing latchup in a gate array. The structure including: a NFET gate array and a PFET gate array in a substrate; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate the NFET gate array and PFET gate array, the through via electrically contacting the P-well.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a lower interconnection on a semiconductor substrate; forming a first interlayer insulation film in which the lower interconnection is buried; forming an MIM capacitive element on the first interlayer insulation film, the MIM capacitive element being formed by layering a lower electrode, a dielectric film, and an upper electrode; forming a second interlayer insulation film in which the MIM capacitive element is buried; forming via holes in the second interlayer insulation film so as to reach the lower electrode; forming a connection plug by filling the via hole with conductive film; and forming an upper interconnection to be connected to the connection plug above the second interlayer insulation film.

Abstract: An exemplary method of forming a contact hole in a semiconductor device includes: forming a first insulation layer on a lower substrate; forming a first conductive layer on the first insulation layer; forming a second insulation layer on the first insulation layer and the first conductive layer; forming a second conductive layer on the second insulation layer; forming a third insulation layer on the second insulation layer and the second conductive layer; patterning a resist on the third insulation layer using an exposure mask of which transmittance is different at a region over the first conductive layer and at a region over the second conductive layer; and forming a first contact hole and a second contact hole by etching the resist and the third insulation layer such that the first conductive layer and the second conductive layer are exposed.

Abstract: The present invention relates to a semiconductor device and a method of fabricating the same. In an embodiment of the present invention, an insulating layer in which contact holes are formed is formed over a semiconductor substrate in which lower metal lines are formed. A barrier metal layer, having a stack structure of a first tungsten (W) layer and a tungsten nitride (WN) layer, is formed within the contact holes. Contact plugs are formed within the contact holes.

Abstract: Methods for fabricating metal wiring layers of a semiconductor device are provided where damascene interconnect structures are formed in a BEOL process that incorporates a dielectric cap-open-first process to achieve hard mask retention and to control the gouging of a buffer oxide layer to prevent exposure of underlying features protected by the buffer oxide layer.

Abstract: A semiconductor device is manufactured by a method including forming a first interlayer insulating film. A first etching stopper film is formed on the first interlayer insulating film. A conductive layer is formed on the first etching stopper film. A second etching stopper film is formed to cover the conductive layer, an upper surface of the conductive layer and both side surfaces of the conductive layer. A second interlayer insulating film is formed on the second etching stopper film. A hole is formed penetrating the second interlayer insulating film in a direction of thickness and reaching the conductive layer. An interconnect is formed in the hole. The step of forming a hole includes etching the second interlayer insulating film under a first etching condition, and etching the second etching stopper film under a second etching condition different from the first etching condition.

Abstract: A method of forming a bit line of a semiconductor memory device is performed as follows. A first interlayer insulating layer is formed over a semiconductor substrate in which an underlying structure is formed. A region of the first interlayer insulating layer is etched to form contact holes through which a contact region of the semiconductor substrate is exposed. A low-resistance tungsten layer is deposited on the entire surface including the contact holes, thus forming contacts. A CMP process is performed in order to mitigate surface roughness of the low-resistance tungsten layer. The low-resistance tungsten layer on the interlayer insulating layer is patterned in a bit line metal line pattern, forming a bit line.

Abstract: A through via in an ultra high resistivity wafer and related methods are disclosed. A method for forming a through via comprises: providing a semiconductor wafer including a first silicon layer, a buried dielectric layer, and a substrate; forming a device on the first silicon; and forming a via from a side of the substrate opposite to the buried dielectric layer and through the substrate.

Abstract: To make a metal feature, a non-plateable layer is applied to a workpiece surface and then patterned to form a first plating region and a first non-plating region. Then, metal is deposited on the workpiece to form a raised field region in said first plating region and a recessed region in said first non-plating region. Then, an accelerator film is applied globally on the workpiece. A portion of the accelerator film is selectively removed from the field region, and another portion of the accelerator film remains in the recessed acceleration region. Then, metal is deposited onto the workpiece, and the metal deposits at an accelerated rate in the acceleration region, resulting in a greater thickness of metal in the acceleration region compared to metal in the non-activated field region. Then, metal is completely removed from the field region, thereby forming the metal feature.

Abstract: A method for fabricating a semiconductor device. A preferred embodiment comprises forming a via in a semiconductor substrate, filling the via with a disposable material such as amorphous carbon, forming a dielectric layer on the substrate covering the via, performing a back side etch to expose the disposable material in the via. A back side dielectric layer is then depositing, covering the exposed via. A small opening is then formed, and the disposable material is removed, for example by an isotropic etch process. The via may now be filled with a metal and used as a conductor or a dielectric material. The via may also be left unfilled to be used as an air gap.

Abstract: An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate having a semiconductor element formed on a surface thereof; an interwiring insulating film formed above the semiconductor substrate; a wiring formed in the interwiring insulating film; a first intervia insulating film formed under the interwiring insulating film; a first via formed in the first intervia insulating film and connected to a lower surface of the wiring; a second intervia insulating film formed on the interwiring insulating film; a second via formed in the second intervia insulating film and connected to an upper surface of the wiring; and a CuSiN film formed in at least one of a position between the interwiring insulating film and the first intervia insulating film, and a position between the interwiring insulating film and the second intervia insulating film.

Abstract: In a semiconductor device including an upper-layer wiring and a lower-layer wiring that overlaps the upper-layer wiring, an wiring switching option includes a via extending from the upper-layer wiring toward the lower-layer wiring. The wiring switching option switches a wiring connection state according to whether the via extends from the upper-layer wiring to reach the lower-layer wiring or extends from the upper-layer wiring to terminate in between the upper-layer wiring and the lower-layer wiring.

Abstract: A method for forming a semiconductor device is described. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an atomic layer deposited (ALD) TaN barrier is conformably formed in the opening, at a thickness less than 20 ?. A copper layer is formed over the atomic layer deposited (ALD) TaN barrier to fill the opening.

Abstract: A semiconductor structure and methods for forming the same. A semiconductor fabrication method includes steps of providing a structure. A structure includes (a) a dielectric layer, (b) a first electrically conductive region buried in the dielectric layer, wherein the first electrically conductive region comprises a first electrically conductive material, and (c) a second electrically conductive region buried in the dielectric layer, wherein the second electrically conductive region comprises a second electrically conductive material being different from the first electrically conductive material. The method further includes the steps of creating a first hole and a second hole in the dielectric layer resulting in the first and second electrically conductive regions being exposed to a surrounding ambient through the first and second holes, respectively. Then, the method further includes the steps of introducing a basic solvent to bottom walls and side walls of the first and second holes.

Abstract: A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer.