Including Organic Insulating Material Between Metal Levels Patents (Class 438/623)
  • Patent number: 10204925
    Abstract: To provide a novel semiconductor device or a semiconductor device capable of operating at high speed. The semiconductor device includes a plurality of circuits each having a function of storing data and a wiring EL. The plurality of circuits each include a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The wiring EL has a function of a back-gate of the first transistor. A potential for selecting the plurality of circuits is supplied to the wiring EL. Thus, data stored in the plurality of circuits is erased.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: February 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Seiichi Yoneda
  • Patent number: 10170718
    Abstract: The devices can be fabricated by a method that permits active polymer chains to be polymerized on the surface of an electrode such that the active polymer chains are aligned with one another. The active polymer chains can also be covalently linked to a second electrode so the active polymer chains are located in an active layer of the device. The polymerization method can be paused and resumed at any point in the polymerization so nanoparticles can be added into the active layer. Additionally, the polymerization method allows that active polymer chains to be polymerized so they include junctions such as p-n junctions and Schottky junctions.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: January 1, 2019
    Assignee: The California Institute of Technology
    Inventor: Raymond Weitekamp
  • Patent number: 10157775
    Abstract: In a pattern forming method, a stacked structure, including a bottom layer, a middle layer and a first mask layer, is formed. The middle layer includes a first cap layer, an intermediate layer and a second cap layer. The first mask layer is patterned by using a first resist pattern as an etching mask. The second cap layer is patterned by using the patterned first mask layer as an etching mask. A second mask layer is formed over the patterned second cap layer, and is patterned by using a second resist pattern as an etching mask. The second cap layer is patterned by using the patterned second mask layer as an etching mask. The intermediate layer and the first cap layer are patterned by using the patterned second cap layer as an etching mask. The bottom layer is patterned by using the patterned first cap layer as an etching mask.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chen, Jyu-Horng Shieh, Ming-Chung Liang, Shu-Huei Suen, Wen-Yen Chen
  • Patent number: 10153161
    Abstract: A method for manufacturing a semiconductor structure includes forming a target layer, a lower hard mask layer, a middle hard mask layer, and an upper hard mask layer in sequence on a substrate. A first mask layer is then formed on the upper hard mask layer, wherein the first mask layer has a plurality of openings exposing a portion of the upper hard mask layer. A patterned upper hard mask layer having a plurality of apertures exposing a portion of the middle hard mask layer is formed by etching the exposed portion of the upper hard mask layer. A patterned organic layer is then formed on the exposed portion of the middle hard mask layer. A patterned target layer is formed by etching the patterned upper hard mask layer, the patterned organic layer, the middle hard mask layer, the lower hard mask layer, and a portion of the target layer.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 11, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 10147691
    Abstract: A semiconductor structure includes a substrate; a post passivation interconnect (PPI) disposed over the substrate and including a plurality of first elongated members extended over a surface of the substrate and a plurality of second elongated members extended over the surface of the substrate and isolated from the plurality of first elongated members; a first polymeric layer covering the PPI; and a second polymeric layer disposed over the first polymeric layer, wherein the plurality of first elongated members are alternately disposed with the plurality of second elongated members, the first polymeric layer includes a recessed portion disposed between one of the plurality of first elongated members and one of the plurality of second elongated members, and the second polymeric layer includes a protruded portion disposed within the recessed portion.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: December 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 9997611
    Abstract: A graphene wiring structure of an embodiment has a multilayered graphene having a plurality of planar graphene sheets laminated, and a first interlayer substance being a metal oxyhalide between the plurality of planar graphene sheets.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: June 12, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Miyazaki, Tadashi Sakai, Masayuki Katagiri, Yuichi Yamazaki
  • Patent number: 9944554
    Abstract: Methods for chemically strengthening the edges of glass sheets are provided. Voids can be formed in a mother sheet. The edges of these voids may correspond to a portion of the new edges that would normally be created during separation and free shaping of the mother sheet. The mother sheet can then be immersed in a chemical strengthener. The edges of the voids can be chemically strengthened in addition to the front and back sides of the mother sheet. After thin film processing and separation, each of the resulting individual sheets has been chemically strengthened on both sides and on a portion of its edges.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: April 17, 2018
    Assignee: APPLE INC.
    Inventors: Seung Jae Hong, Casey J. Feinstein, Lili Huang, Sunggu Kang, Kuo-Hua Sung, John Z. Zhong
  • Patent number: 9905406
    Abstract: A method of mass spectrometry or ion mobility spectrometry is disclosed wherein a sample is ionized by an electrified sprayer so as to produce multiply charged analyte ions of a first polarity in gas-phase. A reaction region is provided downstream of the electrified sprayer, wherein the reaction region is maintained substantially at atmospheric pressure and is maintained substantially free of electric-fields. A gas flow is provided from said electrified sprayer to said reaction region such that the gas flow carries the analyte ions from the electrified sprayer into the reaction region. Free electrons or reagent ions of a second polarity are generated in the reaction region, wherein the second polarity is opposite to said first polarity. The free electrons or reagent ions are then reacted with the analyte ions in the reaction region so as to reduce the charge state of the multiply charged analyte ions and thereby produce charge-reduced analyte ions.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: February 27, 2018
    Assignee: MICROMASS UK LIMITED
    Inventors: Jeffery Mark Brown, Damon Robb
  • Patent number: 9748175
    Abstract: A method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes forming an organosilicon layer over a substrate and etching the organosilicon layer to have a trench. The method for manufacturing a semiconductor structure further includes forming a conductive structure in the trench. In addition, the organosilicon layer is made of a material including Si—C bonding and Si—O bonding, and a ratio of an amount of the Si—C bonding to an amount of the Si—O bonding is greater than about 0.2.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Jung Liu, Huan-Wei Wu, Chester Tang, Joung-Wei Liou
  • Patent number: 9627316
    Abstract: A field effect transistor comprising a substrate, at least one gate stack structure, source and drain regions and an interconnect structure is described. The interconnect structure comprises a metal interconnect connected to a conductive region, an adhesion sheath structure and a cap layer. The adhesion sheath structure is disposed between the metal interconnect and inter-dielectric layers and surrounds the metal interconnect. The cap layer is disposed on the metal interconnect and covers a gap between the metal interconnect and the inter-dielectric layer.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 9553121
    Abstract: A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier film. The first diffusion barrier film includes a first opening region formed in a semiconductor circuit region that is a partial region in a two-dimensional view and a second opening region formed as an opening region different from the first opening region in a two-dimensional view. The opening regions are formed in a region different from an opening region formed to allow the connection portion to pass through the first diffusion barrier film. A mark wiring layer is arranged immediately above the second opening region as the same layer as the second wiring layer. A second diffusion barrier film is arranged in contact with the upper surface of the mark wiring layer.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: January 24, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroaki Sekikawa, Hidenori Sato, Yotaro Goto, Takuya Maruyama, Masaaki Shinohara
  • Patent number: 9509933
    Abstract: A semiconductor apparatus, a solid-state image sensing apparatus, and a camera system capable of reducing interference between signals transmitted through adjacent via holes, preventing an increase in the number of the via holes, reducing the area of a chip having sensors thereon and the number of mounting steps thereof. First and second chips are bonded together to form a laminated structure, a wiring between the first chip and the second chip being connected through via holes, the first chip transmitting signals obtained by time-discretizing analog signals generated by respective sensors to the second chip through the corresponding via holes, the second chip sampling the signals transmitted from the first chip through the via holes at a timing different from a timing at which the signals are sampled by the first chip and quantizing the sampled signals to obtain digital signals.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: November 29, 2016
    Assignee: Sony Corporation
    Inventors: Toshiaki Nagai, Ken Koseki, Yosuke Ueno, Atsushi Suzuki
  • Patent number: 9412613
    Abstract: Embodiments described herein provide for a method of forming an etch selective hardmask. An amorphous carbon hardmask is implanted with various dopants to increase the hardness and density of the hardmask. The ion implantation of the amorphous carbon hardmask also maintains or reduces the internal stress of the hardmask. The etch selective hardmask generally provides for improved patterning in advanced NAND and DRAM devices.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: August 9, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Pramit Manna, Abhijit Basu Mallick, Ludovic Godet, Yongmei Chen, Jun Xue, Mukund Srinivasan, Ellie Y. Yieh, Srinivas D. Nemani
  • Patent number: 9373785
    Abstract: A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: June 21, 2016
    Assignee: SONY CORPORATION
    Inventor: Yoshihisa Kagawa
  • Patent number: 9306032
    Abstract: A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: April 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Po-Chao Tsao, Ching-Wen Hung, Jia-Rong Wu, Chien-Ting Lin
  • Patent number: 9276112
    Abstract: A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: March 1, 2016
    Assignee: Intel Corporation
    Inventor: Mark T. Bohr
  • Patent number: 9245970
    Abstract: A semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an interfacial layer over the semiconductor substrate, the interfacial layer having a capacitive effective thickness of less than 1.37 nanometers (nm). The semiconductor structure further includes a high-k dielectric layer over the interfacial layer.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: January 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Liang-Gi Yao, Chun-Hu Cheng, Chen-Yi Lee, Jeff J. Xu, Clement Hsingjen Wann
  • Patent number: 9226397
    Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 ?m and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 ?m. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: December 29, 2015
    Assignee: IBIDEN CO., LTD.
    Inventors: Yasushi Inagaki, Katsuyuki Sano
  • Patent number: 9219006
    Abstract: Embodiments of the present invention generally relate to methods for forming a flowable carbon-containing film on a substrate. In one embodiment, an oxygen-containing gas is flowed into a remote plasma region to produce oxygen-containing plasma effluents, and a carbon-containing gas is combined with the oxygen-containing plasma effluents in a substrate processing region which contains the substrate. A carbon-containing film is formed in trenches which are formed on the substrate and a low K dielectric material is deposited on the carbon-containing film in the trenches. The carbon-containing film is decomposed by an UV treatment and airgaps are formed in the trenches under the low K dielectric material.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: December 22, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Amit Chatterjee
  • Patent number: 9080017
    Abstract: A composition containing a metal compound and a siloxane compound (A) represented by general formula (1): wherein X is represented by general formula X1 or X2: wherein the number of X1 is 1-8; the number of X2 is 0-7; the sum of the number of X1 and the number of X2 is 8; R1 to R4 represent a hydrogen atom, a C1-8 alkyl group, alkenyl group, alkynyl group, or a C6-8 aryl group, a hydrogen atom thereof optionally being substituted by a fluorine atom; R5 represents a C1-18 alkyl group, alkenyl group, alkynyl group or aryl group, a hydrogen atom thereof being optionally substituted by a fluorine atom, a carbon atom being optionally substituted by an oxygen atom or a nitrogen atom; R6 represents a hydrogen atom, a vinyl group or an allyl group; m and n represent an integer of 1-4; and 3?m+n.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: July 14, 2015
    Assignee: Central Glass Company, Limited
    Inventors: Kazuhiro Yamanaka, Hiroshi Eguchi, Junya Nakatsuji, Takeshi Suda, Katsuhiro Akiyama
  • Patent number: 9076645
    Abstract: Circuit structure fabrication methods are provided which include: providing an interlayer structure above a substrate, the interlayer structure including porogens dispersed within a dielectric material; and pulse laser annealing the interlayer structure to form a treated interlayer structure, the pulse laser annealing polymerizing the dielectric material of the interlayer structure to form a polymeric dielectric material, that includes pores disposed therein. The pulse laser annealing facilitates increasing elasticity modulus of the treated interlayer structure by, in part, maintaining structural integrity of the treated interlayer structure, notwithstanding that there are pores disposed within the polymeric dielectric material which, for instance, facilitates reducing dielectric constant of the treated interlayer structure.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: July 7, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shishir Ray, Sandeep Gaan, Jin Ping Liu, Zhiguo Sun
  • Patent number: 9054107
    Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: June 9, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Fan Zhang, Xiaomei Bu, Jane Hui, Tae Jong Lee, Liang Choo Hsia
  • Patent number: 9041215
    Abstract: Disclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the land and a protective layer disposed over the first surface of the first substrate and around the stud. The protective layer may optionally have a thickness of at least 3 ?m. A PPI may be disposed over the protective layer and in electrical contact with the stud, with a first portion of the PPI extending laterally from the stud. An interconnect may be disposed on and in electrical contact with the first portion of the PPI, and a second substrate mounted on the interconnect. A molding compound may be disposed over the PPI and around the interconnect. The stud may be a substantially solid material having a cylindrical cross section and may optionally be wirebonded to the land.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo
  • Patent number: 9029252
    Abstract: A nanostructure, an optical device including the nanostructure, and methods of manufacturing the nanostructure and the optical device. A method of manufacturing a nanostructure may include forming a block copolymer template layer and a precursor pattern of metal coupled to the block copolymer template layer on a graphene layer, and forming a metal nanopattern on the graphene layer by removing the block copolymer template layer and reducing the precursor pattern.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: May 12, 2015
    Assignees: Samsung Electronics Co., Ltd., Unist Academy—Industry Research Corporation
    Inventors: Un-jeong Kim, Jin-eun Kim, Young-geun Roh, Soo-jin Park, Yeon-sang Park, Seung-min Yoo, Chang-won Lee, Jae-soong Lee, Sang-mo Cheon
  • Patent number: 9018092
    Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 28, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
  • Patent number: 9018740
    Abstract: A field effect transistor (1) including: a semiconducting substrate (2) having two areas doped with electric charge carriers forming a source area (3) and a drain area (4), respectively; a dielectric layer positioned above the semiconducting substrate (2) between the source (3) and the drain (4) and forming the gate dielectric (9) of the field effect transistor (1); a gate (11) consisting of a reference electrode (8) and of a conductive solution (10), the solution (10) being in contact with the gate dielectric (9); and the gate dielectric (9) consists of a layer of lipids (13) in direct contact with the semiconducting layer (2). The invention also relates to a method for manufacturing such a field effect transistor (1) is disclosed.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: April 28, 2015
    Assignee: Centre National de la Recherche Scientifique (C.N.R.S)
    Inventors: Anne Charrier, Hervé Dallaporta, Tuyen Nguyen Duc
  • Patent number: 8999842
    Abstract: A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Patent number: 8994125
    Abstract: A semiconductor device includes, on a semiconductor substrate, a gate insulating film, a pMIS metal material or an nMIS metal material, a gate electrode material, and a gate sidewall metal layer.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: March 31, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Kenshi Kanegae
  • Patent number: 8994086
    Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroko Abe, Yukie Nemoto, Ryoji Nomura, Mikio Yukawa
  • Patent number: 8962489
    Abstract: Disclosed is a method for etching a film contains cobalt and palladium is provided. A hard mask is provided on the film. The method film includes a process “a” of etching the film by ion sputter etching, a process “b” of exposing a workpiece to plasma of a first gas containing halogen elements after the process “a” of etching of the film, a process “c” of exposing the workpiece to plasma of a second gas containing carbons after the process “b” of exposing the workpiece to the plasma of the first gas, and a process “d” of exposing the workpiece to plasma of a third gas containing a noble gas after the process “c” of exposing the workpiece to the plasma of the second gas. In the method, a temperature of a placement table on which the workpiece is placed is set to a first temperature of 10° C. or less in the process “a”, process “b” and process “c”.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: February 24, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Eiichi Nishimura, Masato Kushibiki
  • Publication number: 20150041814
    Abstract: A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.
    Type: Application
    Filed: April 8, 2014
    Publication date: February 12, 2015
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: JI-SUN KIM, JI-HYUN KIM, SHIN-IL CHOI, YEONG-KEUN KWON
  • Patent number: 8927414
    Abstract: A graphene structure and a method of manufacturing the graphene structure, and a graphene device and a method of manufacturing the graphene device. The graphene structure includes a substrate; a growth layer disposed on the substrate and having exposed side surfaces; and a graphene layer disposed on the side surfaces of the growth layer.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: January 6, 2015
    Assignees: Samsung Electronics Co., Ltd., Sungkyunkwan University Foundation for Corporate Collaboration
    Inventors: Byoung-Iyong Choi, Eun-kyung Lee, Dong-mok Whang
  • Patent number: 8927869
    Abstract: Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Zhong-Xiang He, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Patent number: 8871627
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 28, 2014
    Assignee: Tera Probe, Inc.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 8872334
    Abstract: In a manufacturing method of a semiconductor device incorporating a semiconductor element in a multilayered wiring structure including a plurality of wiring layers and insulating layers, a semiconductor element is mounted on a silicon support body whose thickness is reduced to a desired thickness and which are equipped with a plurality of through-vias running through in the thickness direction; an insulating layer is formed to embed the semiconductor element; then, a plurality of wiring layers is formed on the opposite surfaces of the silicon support body in connection with the semiconductor element. Thus, it is possible to reduce warping which occurs in proximity to the semiconductor element in manufacturing, thus improving a warping profile in the entirety of a semiconductor device. Additionally, it is possible to prevent semiconductor elements from becoming useless, improve a yield rate, and produce a thin-type semiconductor device with high-density packaging property.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: October 28, 2014
    Assignee: NEC Corporation
    Inventors: Shintaro Yamamichi, Katsumi Kikuchi, Yoshiki Nakashima, Kentaro Mori
  • Patent number: 8853659
    Abstract: A switchable electronic device comprises a hole blocking layer and a layer comprising a conductive material between first and second electrodes, wherein the conductivity of the device may be irreversibly switched upon application of a current having a current density of less than or equal to 100 A cm?2 to a conductivity at least 100 times lower than the conductivity of the device before switching. The conductive material is a doped organic material such as doped optionally substituted poly(ethylene dioxythiophene).
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: October 7, 2014
    Assignee: Cambridge Display Technology Limited
    Inventors: Neil Greenham, Jianpu Wang
  • Publication number: 20140291687
    Abstract: Provided is a display unit that includes: a laminated structure including two first wirings, a first insulating layer, and a concave part, in which the first wirings are adjacent to each other, the first insulating layer is provided on the first wirings and is made of an organic material, and the concave part penetrates, between the first wirings, from the first insulating layer to the first wirings in a laminated direction; and a second insulating layer provided in the concave part and on the laminated structure.
    Type: Application
    Filed: March 18, 2014
    Publication date: October 2, 2014
    Applicant: Sony Corporation
    Inventors: Koichi NAGASAWA, Tomoaki HONDA, Hirofumi FUJIOKA
  • Publication number: 20140264546
    Abstract: For certain three dimensionally stacked memory devices, bit lines or word lines for memory cells are stacked in spaced apart ridge like structures arranged to extend in a first direction. In such structures, complementary wordlines or bit lines, can be damascene features between the spaced apart. The damascene conductors can be formed using double patterned masks to etch sub-lithographic sacrificial lines, forming a fill over the sacrificial lines, and then removing the sacrificial lines to leave trenches that act as the damascene molds in the fill. Then the trenches are filled with the conductor material. The 3D memory array can include dielectric charge trapping memory cells, which have a high-K blocking dielectric layer, and in which the conductor material comprises a high work function material.
    Type: Application
    Filed: May 20, 2013
    Publication date: September 18, 2014
    Applicant: MACRONIX INTENATIONAL CO., LTD.
    Inventors: ERH-KUN LAI, YEN-HAO SHIH, GUANRU LEE
  • Patent number: 8835307
    Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hakeem Akinmade-Yusuff, John A. Fitzsimmons, Ranee Wai-Ling Kwong
  • Patent number: 8828841
    Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Bing-Hung Chen, Tze-Liang Lee, Hao-Ming Lien
  • Publication number: 20140217605
    Abstract: An interconnection structure for a package is disclosed. The interconnection structure includes a substrate body having a conductive portion formed on a surface thereof; a first photosensitive dielectric layer formed on the surface of the substrate body and having a via for exposing the conductive potion; a conductive via formed in the via; a second photosensitive dielectric layer formed on the first photosensitive dielectric layer and having a opening for exposing the conductive via and a portion of the first photosensitive dielectric layer; and a conductive trace layer formed in the opening of the second photosensitive dielectric layer so as to be electrically connected to the conductive portion through the conductive via, thereby simplifying the fabrication process and reducing the fabrication cost and time.
    Type: Application
    Filed: May 15, 2013
    Publication date: August 7, 2014
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chun-Hung Lin, Chun-Hung Lu, Guang-Hwa Ma, Hsiao-Chun Huang, Kuang-Hsin Chen
  • Patent number: 8790990
    Abstract: Provided is a silica-based film forming material for formation of air gaps, the material being capable of forming air gaps without employing a CVD method. A silica-based film forming material for formation of air gaps including (a) a certain siloxane polymer, (b) an alkanolamine, and (c) an organic solvent is used when a silica-based film is formed with a spin coating method. According to this silica-based film forming material for formation of air gaps, air gaps with a great degree of opening can be formed even when coated with a spin coating method, without filling the recessed parts.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: July 29, 2014
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventor: Yoshihiro Sawada
  • Patent number: 8785321
    Abstract: A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Chu Ko, Ming-Hsing Tsai, Chien-Hsueh Shih
  • Patent number: 8785319
    Abstract: Methods of forming fine patterns are provided. The methods may include forming first hard mask patterns extending in a first direction on a lower layer, forming second hard mask patterns filling gap regions between the first hard mask patterns, forming first mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the first mask patterns as etch masks to form first openings, forming second mask patterns filling the first openings and extending in the second direction, and etching the second hard mask patterns using the second mask patterns as etch masks to form second openings spaced apart from the first openings in a diagonal direction with respect to the first direction.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Soo Park, Kukhan Yoon, Joon Kim, Cheolhong Kim, Seokwoo Nam
  • Patent number: 8766449
    Abstract: Disclosed is a variable interconnect geometry formed on a substrate that allows for increased electrical performance of the interconnects without compromising mechanical reliability. The compliance of the interconnects varies from the center of the substrate to edges of the substrate. The variation in compliance can either be step-wise or continuous. Exemplary low-compliance interconnects include columnar interconnects and exemplary high-compliance interconnects include helix interconnects. A cost-effective implementation using batch fabrication of the interconnects at a wafer level through sequential lithography and electroplating processes may be employed.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: July 1, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: Suresh K. Sitaraman, Karan Kacker, Thomas Sokol
  • Patent number: 8759212
    Abstract: A method of manufacturing a semiconductor device includes: forming a cap insulating film, including Si and C, on a substrate; forming an organic silica film, having a composition ratio of the number of carbon atoms to the number of silicon atoms higher than that of the cap insulating film, on the cap insulating film; and forming two or more concave portions, having different opening diameters, in the organic silica film, by plasma processing in which mixed gas including inert gas, N-containing gas, fluorocarbon gas and oxidant gas is used.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: June 24, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Ippei Kume, Jun Kawahara, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
  • Patent number: 8741787
    Abstract: A silicon-based low-k dielectric material is formed on the basis of a single precursor material, such as OMTCS, without incorporating a porogen species. To this end, the initial deposition of the low-k dielectric material may be formed on the basis of a reduced process temperature, while a subsequent treatment, such as a UV treatment, may allow the adjustment of the final material characteristics without causing undue out-gassing of volatile organic components.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: June 3, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ulrich Mayer, Hartmut Ruelke, Christof Streck
  • Patent number: 8735300
    Abstract: A method of forming contact hole is disclosed, including the steps of: providing a semiconductor substrate having a first dielectric layer, a second dielectric layer and a third dielectric layer formed thereon in this order; forming a first contact hole through the third dielectric layer, the second dielectric layer and the first dielectric layer by using an etching process to expose the semiconductor substrate; removing the third dielectric layer; forming a fourth dielectric layer over the second dielectric layer, the fourth dielectric layer filling the first contact hole; forming a second contact hole through the fourth dielectric layer, the second dielectric layer and the first dielectric layer to expose the semiconductor substrate; and removing the fourth dielectric layer. The method is capable of improving the stability of the contact-hole formation process.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 27, 2014
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Yu Zhang, Jun Huang, Chenguang Gai
  • Patent number: 8679967
    Abstract: The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: March 25, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Yoichiro Tanaka
  • Patent number: 8673764
    Abstract: Various embodiments provide methods and systems for making and/or cleaning semiconductor devices. In one embodiment, a semiconductor device can be formed including a metal layer and a photoresist polymer. During formation, the semiconductor device can be cleaned in a cleaning chamber by a first cleaning solution provided from a solution supply device. After this cleaning process, a second cleaning solution containing metal ions and/or polymer residues can be produced and processed in a solution processing device to at least partially remove the metal ions and/or polymer residues to produce a third cleaning solution for re-use. In an exemplary fabrication or cleaning system, the solution processing device may be configured connecting to either an inlet or an outlet of the cleaning chamber. After cleaning, the semiconductor device can be processed to include a metal plug or an interconnect wiring.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: March 18, 2014
    Assignee: Semiconductor Manufacturing International Corp.
    Inventor: Zhugen Yuan