Including Organic Insulating Material Between Metal Levels Patents (Class 438/623)
  • Patent number: 11817293
    Abstract: Photoresist layers of semiconductor components including electric fields. The photoresist layer may include a body including a first portion disposed directly over a conductive layer of the semiconductor component. The body may also include a second portion integrally formed with and positioned over the first portion. The second portion may include a surface formed opposite the first portion. Additionally, the second portion may include a plurality of charged-particles implanted therein, where the plurality of charged-particles generating an electric field may extend through the first portion and the second portion of the body.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: November 14, 2023
    Assignee: THE RESEARCH FOUNDATION FOR THE STATE UNIVERSITY OF NEW YORK
    Inventor: Gregory Denbeaux
  • Patent number: 11784240
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a contact layer over a metal silicide layer. The contact layer extends through a first dielectric structure. The semiconductor device structure includes a first metal nitride barrier layer over sidewalls of the contact layer. The first metal nitride barrier layer is directly adjacent to the first dielectric structure. The semiconductor device structure includes a second metal nitride barrier layer partially between the contact layer and the metal silicide layer and partially between the contact layer and the first metal nitride barrier layer. The metal silicide layer is below the first metal nitride barrier layer and the second metal nitride barrier layer.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yang Wu, Shiu-Ko Jangjian, Ting-Chun Wang, Yung-Si Yu
  • Patent number: 11702434
    Abstract: Novel N-alkyl substituted perhydridocyclic silazanes, oligomeric N-alkyl perhydridosilazane compounds, and N-alkylaminodihydridohalosilanes, and a method for their synthesis are provided. The novel compounds may be used to form high silicon nitride content films by thermal or plasma induced decomposition.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: July 18, 2023
    Assignee: GELEST, INC.
    Inventors: Barry C. Arkles, Youlin Pan, Fernando Jove
  • Patent number: 11631585
    Abstract: A method for fabricating a semiconductor structure includes: providing a substrate and a dielectric layer on the substrate; and forming an etching mask on the dielectric layer; and etching the dielectric layer using the etching mask to form at least one opening therein. The etching mask includes: a hard mask layer, a photoresist layer, and a hexamethyldisilazane (HMDS) layer. The photoresist layer is located over the hard mask layer, and the HMDS layer is located between the hard mask layer and the photoresist layer.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: April 18, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Jui-Seng Wang, Yu-Chen Huang
  • Patent number: 11361974
    Abstract: A method for forming a semiconductor structure includes the steps of providing a substrate having a first region and a second region, forming a plurality of semiconductor devices on the first region of the substrate, forming a planarization layer on the substrate and covering the semiconductor devices, wherein the planarization layer on the first region and the planarization layer on the second region have a step-height, performing a first CMP process to remove the step height of the planarization layer, and after the first CMP process, performing a curing process to convert the planarization layer into a porous low-k dielectric layer.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: June 14, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Weiwen Zhong
  • Patent number: 11205617
    Abstract: An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer on the metal interconnect layer. The graphene layer insulates a metal from air and prevents the metal from being oxidized by oxygen in the air, thereby increasing the queue time for the CMP process and the device reliability.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: December 21, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Ming Zhou
  • Patent number: 11164776
    Abstract: A method includes forming a metallic interconnect structure on a semiconductor substrate where the metallic interconnect structure comprises a plurality of metal lines with adjacent metal lines separated by a gap therebetween. The method further includes selectively depositing a first low-k dielectric material onto the semiconductor substrate and onto exposed surfaces of the metal lines of the metallic interconnect structure to form a barrier on at least the metal lines. The barrier is configured to minimize oxidation and diffusion of metal of the metal lines. The method also includes depositing a flowable second low-k dielectric material onto the semiconductor substrate to form a dielectric layer encapsulating the barrier and the metallic interconnect structure.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Son Nguyen, Takeshi Nogami, Thomas Jasper Haigh, Jr., Cornelius Brown Peethala, Matthew T. Shoudy
  • Patent number: 11137364
    Abstract: This invention provides a microsystem comprising a porous thermal insulation body composed of particles of low thermal conductivity. The porous body isolates and stabilizes the microsystem.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 5, 2021
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Thomas Lisec, Hans-Joachim Quenzer
  • Patent number: 11101322
    Abstract: A method is presented for forming vertical crossbar resistive random access memory (RRAM) cells. The method includes forming a substantially U-shaped bottom electrode over a substrate, filling the U-shaped bottom electrode with a first conductive material, capping the U-shaped bottom electrode with a dielectric cap, depositing a high-k material, and forming a top electrode such that active areas of the RRAM cells are vertically aligned and the U-shaped bottom electrode is shared between neighboring RRAM cells.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dexin Kong, Takashi Ando, Kangguo Cheng, Juntao Li
  • Patent number: 11088021
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shiou Chen, Chih-Yuan Ting
  • Patent number: 10957532
    Abstract: Methods and apparatus for forming a conformal SiOC film on a surface are described. A SiCN film is formed on a substrate surface and exposed to a steam annealing process to decrease the nitrogen content, increase the oxygen content and leave the carbon content about the same. The annealed film has one or more of the wet etch rate or dielectric constant of the film.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 23, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ning Li, Zhelin Sun, Mihaela Balseanu, Li-Qun Xia, Bhaskar Jyoti Bhuyan, Mark Saly
  • Patent number: 10950495
    Abstract: One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chih-Yuan Ting, Ya-Lien Lee, Chung-Wen Wu, Jeng-Shiou Chen
  • Patent number: 10847375
    Abstract: A method for selectively etching a dielectric layer with respect to an epitaxial layer or metal-based hardmask is provided. The method comprises performing a plurality of cycles. Each cycle comprises a deposition phase and an activation phase. The deposition phase comprises flowing a deposition gas, wherein the deposition gas comprises helium and a hydrofluorocarbon or fluorocarbon, forming the deposition gas into a plasma to effect a fluorinated polymer deposition, and stopping the flow of the deposition gas. The activation phase comprises flowing an activation gas comprising an ion bombardment gas, forming the activation gas into a plasma, providing an activation bias to cause ion bombardment of the fluorinated polymer deposition, wherein the ion bombardment activates fluorine from the fluorinated polymer deposition to etch the dielectric layer, and stopping the flow of the activation gas.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: November 24, 2020
    Assignee: Lam Research Corporation
    Inventors: Chia-Chun Wang, Eric Hudson, Andrew Clark Serino, Nerissa Draeger, Zhonghao Zhang
  • Patent number: 10714383
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
  • Patent number: 10453790
    Abstract: A semiconductor package includes: a semiconductor chip having connection pads; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface and including an insulating member and a redistribution layer formed on the insulating member and electrically connected to the connection pads; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; and a barrier layer disposed on the second surface of the connection member and including an organic layer containing fluorine.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Hwa Park, Ichiro Ogura
  • Patent number: 10204925
    Abstract: To provide a novel semiconductor device or a semiconductor device capable of operating at high speed. The semiconductor device includes a plurality of circuits each having a function of storing data and a wiring EL. The plurality of circuits each include a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The wiring EL has a function of a back-gate of the first transistor. A potential for selecting the plurality of circuits is supplied to the wiring EL. Thus, data stored in the plurality of circuits is erased.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: February 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Seiichi Yoneda
  • Patent number: 10170718
    Abstract: The devices can be fabricated by a method that permits active polymer chains to be polymerized on the surface of an electrode such that the active polymer chains are aligned with one another. The active polymer chains can also be covalently linked to a second electrode so the active polymer chains are located in an active layer of the device. The polymerization method can be paused and resumed at any point in the polymerization so nanoparticles can be added into the active layer. Additionally, the polymerization method allows that active polymer chains to be polymerized so they include junctions such as p-n junctions and Schottky junctions.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: January 1, 2019
    Assignee: The California Institute of Technology
    Inventor: Raymond Weitekamp
  • Patent number: 10157775
    Abstract: In a pattern forming method, a stacked structure, including a bottom layer, a middle layer and a first mask layer, is formed. The middle layer includes a first cap layer, an intermediate layer and a second cap layer. The first mask layer is patterned by using a first resist pattern as an etching mask. The second cap layer is patterned by using the patterned first mask layer as an etching mask. A second mask layer is formed over the patterned second cap layer, and is patterned by using a second resist pattern as an etching mask. The second cap layer is patterned by using the patterned second mask layer as an etching mask. The intermediate layer and the first cap layer are patterned by using the patterned second cap layer as an etching mask. The bottom layer is patterned by using the patterned first cap layer as an etching mask.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Chen, Jyu-Horng Shieh, Ming-Chung Liang, Shu-Huei Suen, Wen-Yen Chen
  • Patent number: 10153161
    Abstract: A method for manufacturing a semiconductor structure includes forming a target layer, a lower hard mask layer, a middle hard mask layer, and an upper hard mask layer in sequence on a substrate. A first mask layer is then formed on the upper hard mask layer, wherein the first mask layer has a plurality of openings exposing a portion of the upper hard mask layer. A patterned upper hard mask layer having a plurality of apertures exposing a portion of the middle hard mask layer is formed by etching the exposed portion of the upper hard mask layer. A patterned organic layer is then formed on the exposed portion of the middle hard mask layer. A patterned target layer is formed by etching the patterned upper hard mask layer, the patterned organic layer, the middle hard mask layer, the lower hard mask layer, and a portion of the target layer.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 11, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 10147691
    Abstract: A semiconductor structure includes a substrate; a post passivation interconnect (PPI) disposed over the substrate and including a plurality of first elongated members extended over a surface of the substrate and a plurality of second elongated members extended over the surface of the substrate and isolated from the plurality of first elongated members; a first polymeric layer covering the PPI; and a second polymeric layer disposed over the first polymeric layer, wherein the plurality of first elongated members are alternately disposed with the plurality of second elongated members, the first polymeric layer includes a recessed portion disposed between one of the plurality of first elongated members and one of the plurality of second elongated members, and the second polymeric layer includes a protruded portion disposed within the recessed portion.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: December 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 9997611
    Abstract: A graphene wiring structure of an embodiment has a multilayered graphene having a plurality of planar graphene sheets laminated, and a first interlayer substance being a metal oxyhalide between the plurality of planar graphene sheets.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: June 12, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisao Miyazaki, Tadashi Sakai, Masayuki Katagiri, Yuichi Yamazaki
  • Patent number: 9944554
    Abstract: Methods for chemically strengthening the edges of glass sheets are provided. Voids can be formed in a mother sheet. The edges of these voids may correspond to a portion of the new edges that would normally be created during separation and free shaping of the mother sheet. The mother sheet can then be immersed in a chemical strengthener. The edges of the voids can be chemically strengthened in addition to the front and back sides of the mother sheet. After thin film processing and separation, each of the resulting individual sheets has been chemically strengthened on both sides and on a portion of its edges.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: April 17, 2018
    Assignee: APPLE INC.
    Inventors: Seung Jae Hong, Casey J. Feinstein, Lili Huang, Sunggu Kang, Kuo-Hua Sung, John Z. Zhong
  • Patent number: 9905406
    Abstract: A method of mass spectrometry or ion mobility spectrometry is disclosed wherein a sample is ionized by an electrified sprayer so as to produce multiply charged analyte ions of a first polarity in gas-phase. A reaction region is provided downstream of the electrified sprayer, wherein the reaction region is maintained substantially at atmospheric pressure and is maintained substantially free of electric-fields. A gas flow is provided from said electrified sprayer to said reaction region such that the gas flow carries the analyte ions from the electrified sprayer into the reaction region. Free electrons or reagent ions of a second polarity are generated in the reaction region, wherein the second polarity is opposite to said first polarity. The free electrons or reagent ions are then reacted with the analyte ions in the reaction region so as to reduce the charge state of the multiply charged analyte ions and thereby produce charge-reduced analyte ions.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: February 27, 2018
    Assignee: MICROMASS UK LIMITED
    Inventors: Jeffery Mark Brown, Damon Robb
  • Patent number: 9748175
    Abstract: A method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes forming an organosilicon layer over a substrate and etching the organosilicon layer to have a trench. The method for manufacturing a semiconductor structure further includes forming a conductive structure in the trench. In addition, the organosilicon layer is made of a material including Si—C bonding and Si—O bonding, and a ratio of an amount of the Si—C bonding to an amount of the Si—O bonding is greater than about 0.2.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Jung Liu, Huan-Wei Wu, Chester Tang, Joung-Wei Liou
  • Patent number: 9627316
    Abstract: A field effect transistor comprising a substrate, at least one gate stack structure, source and drain regions and an interconnect structure is described. The interconnect structure comprises a metal interconnect connected to a conductive region, an adhesion sheath structure and a cap layer. The adhesion sheath structure is disposed between the metal interconnect and inter-dielectric layers and surrounds the metal interconnect. The cap layer is disposed on the metal interconnect and covers a gap between the metal interconnect and the inter-dielectric layer.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 9553121
    Abstract: A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier film. The first diffusion barrier film includes a first opening region formed in a semiconductor circuit region that is a partial region in a two-dimensional view and a second opening region formed as an opening region different from the first opening region in a two-dimensional view. The opening regions are formed in a region different from an opening region formed to allow the connection portion to pass through the first diffusion barrier film. A mark wiring layer is arranged immediately above the second opening region as the same layer as the second wiring layer. A second diffusion barrier film is arranged in contact with the upper surface of the mark wiring layer.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: January 24, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroaki Sekikawa, Hidenori Sato, Yotaro Goto, Takuya Maruyama, Masaaki Shinohara
  • Patent number: 9509933
    Abstract: A semiconductor apparatus, a solid-state image sensing apparatus, and a camera system capable of reducing interference between signals transmitted through adjacent via holes, preventing an increase in the number of the via holes, reducing the area of a chip having sensors thereon and the number of mounting steps thereof. First and second chips are bonded together to form a laminated structure, a wiring between the first chip and the second chip being connected through via holes, the first chip transmitting signals obtained by time-discretizing analog signals generated by respective sensors to the second chip through the corresponding via holes, the second chip sampling the signals transmitted from the first chip through the via holes at a timing different from a timing at which the signals are sampled by the first chip and quantizing the sampled signals to obtain digital signals.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: November 29, 2016
    Assignee: Sony Corporation
    Inventors: Toshiaki Nagai, Ken Koseki, Yosuke Ueno, Atsushi Suzuki
  • Patent number: 9412613
    Abstract: Embodiments described herein provide for a method of forming an etch selective hardmask. An amorphous carbon hardmask is implanted with various dopants to increase the hardness and density of the hardmask. The ion implantation of the amorphous carbon hardmask also maintains or reduces the internal stress of the hardmask. The etch selective hardmask generally provides for improved patterning in advanced NAND and DRAM devices.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: August 9, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Pramit Manna, Abhijit Basu Mallick, Ludovic Godet, Yongmei Chen, Jun Xue, Mukund Srinivasan, Ellie Y. Yieh, Srinivas D. Nemani
  • Patent number: 9373785
    Abstract: A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: June 21, 2016
    Assignee: SONY CORPORATION
    Inventor: Yoshihisa Kagawa
  • Patent number: 9306032
    Abstract: A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: April 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Po-Chao Tsao, Ching-Wen Hung, Jia-Rong Wu, Chien-Ting Lin
  • Patent number: 9276112
    Abstract: A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: March 1, 2016
    Assignee: Intel Corporation
    Inventor: Mark T. Bohr
  • Patent number: 9245970
    Abstract: A semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an interfacial layer over the semiconductor substrate, the interfacial layer having a capacitive effective thickness of less than 1.37 nanometers (nm). The semiconductor structure further includes a high-k dielectric layer over the interfacial layer.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: January 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Liang-Gi Yao, Chun-Hu Cheng, Chen-Yi Lee, Jeff J. Xu, Clement Hsingjen Wann
  • Patent number: 9226397
    Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 ?m and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 ?m. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: December 29, 2015
    Assignee: IBIDEN CO., LTD.
    Inventors: Yasushi Inagaki, Katsuyuki Sano
  • Patent number: 9219006
    Abstract: Embodiments of the present invention generally relate to methods for forming a flowable carbon-containing film on a substrate. In one embodiment, an oxygen-containing gas is flowed into a remote plasma region to produce oxygen-containing plasma effluents, and a carbon-containing gas is combined with the oxygen-containing plasma effluents in a substrate processing region which contains the substrate. A carbon-containing film is formed in trenches which are formed on the substrate and a low K dielectric material is deposited on the carbon-containing film in the trenches. The carbon-containing film is decomposed by an UV treatment and airgaps are formed in the trenches under the low K dielectric material.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: December 22, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Amit Chatterjee
  • Patent number: 9080017
    Abstract: A composition containing a metal compound and a siloxane compound (A) represented by general formula (1): wherein X is represented by general formula X1 or X2: wherein the number of X1 is 1-8; the number of X2 is 0-7; the sum of the number of X1 and the number of X2 is 8; R1 to R4 represent a hydrogen atom, a C1-8 alkyl group, alkenyl group, alkynyl group, or a C6-8 aryl group, a hydrogen atom thereof optionally being substituted by a fluorine atom; R5 represents a C1-18 alkyl group, alkenyl group, alkynyl group or aryl group, a hydrogen atom thereof being optionally substituted by a fluorine atom, a carbon atom being optionally substituted by an oxygen atom or a nitrogen atom; R6 represents a hydrogen atom, a vinyl group or an allyl group; m and n represent an integer of 1-4; and 3?m+n.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: July 14, 2015
    Assignee: Central Glass Company, Limited
    Inventors: Kazuhiro Yamanaka, Hiroshi Eguchi, Junya Nakatsuji, Takeshi Suda, Katsuhiro Akiyama
  • Patent number: 9076645
    Abstract: Circuit structure fabrication methods are provided which include: providing an interlayer structure above a substrate, the interlayer structure including porogens dispersed within a dielectric material; and pulse laser annealing the interlayer structure to form a treated interlayer structure, the pulse laser annealing polymerizing the dielectric material of the interlayer structure to form a polymeric dielectric material, that includes pores disposed therein. The pulse laser annealing facilitates increasing elasticity modulus of the treated interlayer structure by, in part, maintaining structural integrity of the treated interlayer structure, notwithstanding that there are pores disposed within the polymeric dielectric material which, for instance, facilitates reducing dielectric constant of the treated interlayer structure.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: July 7, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shishir Ray, Sandeep Gaan, Jin Ping Liu, Zhiguo Sun
  • Patent number: 9054107
    Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: June 9, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Fan Zhang, Xiaomei Bu, Jane Hui, Tae Jong Lee, Liang Choo Hsia
  • Patent number: 9041215
    Abstract: Disclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the land and a protective layer disposed over the first surface of the first substrate and around the stud. The protective layer may optionally have a thickness of at least 3 ?m. A PPI may be disposed over the protective layer and in electrical contact with the stud, with a first portion of the PPI extending laterally from the stud. An interconnect may be disposed on and in electrical contact with the first portion of the PPI, and a second substrate mounted on the interconnect. A molding compound may be disposed over the PPI and around the interconnect. The stud may be a substantially solid material having a cylindrical cross section and may optionally be wirebonded to the land.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo
  • Patent number: 9029252
    Abstract: A nanostructure, an optical device including the nanostructure, and methods of manufacturing the nanostructure and the optical device. A method of manufacturing a nanostructure may include forming a block copolymer template layer and a precursor pattern of metal coupled to the block copolymer template layer on a graphene layer, and forming a metal nanopattern on the graphene layer by removing the block copolymer template layer and reducing the precursor pattern.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: May 12, 2015
    Assignees: Samsung Electronics Co., Ltd., Unist Academy—Industry Research Corporation
    Inventors: Un-jeong Kim, Jin-eun Kim, Young-geun Roh, Soo-jin Park, Yeon-sang Park, Seung-min Yoo, Chang-won Lee, Jae-soong Lee, Sang-mo Cheon
  • Patent number: 9018740
    Abstract: A field effect transistor (1) including: a semiconducting substrate (2) having two areas doped with electric charge carriers forming a source area (3) and a drain area (4), respectively; a dielectric layer positioned above the semiconducting substrate (2) between the source (3) and the drain (4) and forming the gate dielectric (9) of the field effect transistor (1); a gate (11) consisting of a reference electrode (8) and of a conductive solution (10), the solution (10) being in contact with the gate dielectric (9); and the gate dielectric (9) consists of a layer of lipids (13) in direct contact with the semiconducting layer (2). The invention also relates to a method for manufacturing such a field effect transistor (1) is disclosed.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: April 28, 2015
    Assignee: Centre National de la Recherche Scientifique (C.N.R.S)
    Inventors: Anne Charrier, Hervé Dallaporta, Tuyen Nguyen Duc
  • Patent number: 9018092
    Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 28, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
  • Patent number: 8999842
    Abstract: A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Patent number: 8994125
    Abstract: A semiconductor device includes, on a semiconductor substrate, a gate insulating film, a pMIS metal material or an nMIS metal material, a gate electrode material, and a gate sidewall metal layer.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: March 31, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Kenshi Kanegae
  • Patent number: 8994086
    Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroko Abe, Yukie Nemoto, Ryoji Nomura, Mikio Yukawa
  • Patent number: 8962489
    Abstract: Disclosed is a method for etching a film contains cobalt and palladium is provided. A hard mask is provided on the film. The method film includes a process “a” of etching the film by ion sputter etching, a process “b” of exposing a workpiece to plasma of a first gas containing halogen elements after the process “a” of etching of the film, a process “c” of exposing the workpiece to plasma of a second gas containing carbons after the process “b” of exposing the workpiece to the plasma of the first gas, and a process “d” of exposing the workpiece to plasma of a third gas containing a noble gas after the process “c” of exposing the workpiece to the plasma of the second gas. In the method, a temperature of a placement table on which the workpiece is placed is set to a first temperature of 10° C. or less in the process “a”, process “b” and process “c”.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: February 24, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Eiichi Nishimura, Masato Kushibiki
  • Publication number: 20150041814
    Abstract: A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.
    Type: Application
    Filed: April 8, 2014
    Publication date: February 12, 2015
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: JI-SUN KIM, JI-HYUN KIM, SHIN-IL CHOI, YEONG-KEUN KWON
  • Patent number: 8927869
    Abstract: Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Zhong-Xiang He, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Patent number: 8927414
    Abstract: A graphene structure and a method of manufacturing the graphene structure, and a graphene device and a method of manufacturing the graphene device. The graphene structure includes a substrate; a growth layer disposed on the substrate and having exposed side surfaces; and a graphene layer disposed on the side surfaces of the growth layer.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: January 6, 2015
    Assignees: Samsung Electronics Co., Ltd., Sungkyunkwan University Foundation for Corporate Collaboration
    Inventors: Byoung-Iyong Choi, Eun-kyung Lee, Dong-mok Whang
  • Patent number: 8871627
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 28, 2014
    Assignee: Tera Probe, Inc.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 8872334
    Abstract: In a manufacturing method of a semiconductor device incorporating a semiconductor element in a multilayered wiring structure including a plurality of wiring layers and insulating layers, a semiconductor element is mounted on a silicon support body whose thickness is reduced to a desired thickness and which are equipped with a plurality of through-vias running through in the thickness direction; an insulating layer is formed to embed the semiconductor element; then, a plurality of wiring layers is formed on the opposite surfaces of the silicon support body in connection with the semiconductor element. Thus, it is possible to reduce warping which occurs in proximity to the semiconductor element in manufacturing, thus improving a warping profile in the entirety of a semiconductor device. Additionally, it is possible to prevent semiconductor elements from becoming useless, improve a yield rate, and produce a thin-type semiconductor device with high-density packaging property.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: October 28, 2014
    Assignee: NEC Corporation
    Inventors: Shintaro Yamamichi, Katsumi Kikuchi, Yoshiki Nakashima, Kentaro Mori