Abstract: A method for fabricating an interconnection structure includes the following steps. Firstly, a substrate having a first conductive layer thereon is provided. Next, an ultra low-k material layer is formed on the substrate. Next, a portion of the ultra low-k material layer is removed, so as to form an opening to expose the first conductive layer. Next, a dry-cleaning process is performed by using gas, so as to clean a surface of the first conductive layer exposed by the opening. The dry-cleaning process is performed at a temperature in a range from the room temperature to 100° C.

Abstract: A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.

Abstract: An apparatus includes a first solid electrode on a substrate, a polyelectrolyte layer over a part of the first solid electrode, a second solid electrode on a portion of the polyelectrolyte layer, and an anchoring layer on the part of the first solid electrode. The polyelectrolyte layer is either chemically bonded to the anchoring layer or has a thickness of less than about 20 nanometers.

Abstract: A method of forming fine patterns of a semiconductor device comprises forming sacrificial film patterns of a line type in a cell region of a semiconductor substrate and, at the same time, forming pad patterns in a peripheral region of the semiconductor substrate, forming a spacer on sidewalls of each of the sacrificial film patterns and the pad patterns, forming a gap-fill layer on sidewalls of the spacers to thereby form line and space patterns, including the sacrificial film patterns and the gap-fill layers, in the cell region, and separating the line and space patterns of the cell region at regular intervals and, at the same time, etching the pad patterns of the peripheral region to thereby form specific patterns in the peripheral region.

Abstract: A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines.

Abstract: An organic EL light-emitting material and an organic EL light-emitting element using the same are provided. Between an anode and a cathode, there are provided a hole transport layer, a light-emitting layer constituted of an organic EL light-emitting material including at least one kind of metal pyrazole complex constituted of a metal ion that is a monovalent cation of a d10 group element and a pyrazole ligand that has a predetermined substituent at the whole or a part of 3, 4 and 5 sites, and an electron transport layer, in this order from the anode side.

Abstract: A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.

Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.

Abstract: A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.

Abstract: An interconnect structure is provided which comprises a semiconductor substrate; a patterned and cured photoresist wherein the photoresist contains a low k dielectric substitutent and contains a fortification layer on its top and sidewall surfaces forming vias or trenches; and a conductive fill material in the vias or trenches. Also provided is a method for fabricating an interconnect structure which comprises depositing a photoresist onto a semiconductor substrate, wherein the photoresist contains a low k dielectric constituent; imagewise exposing the photoresist to actinic radiation; then forming a pattern of vias or trenches in the photoresist; surface fortifying the pattern of vias or trenches proving a fortification layer on the top and sidewalls of the vias or trenches; curing the pattern of vias or trenches thereby converting the photoresist into a dielectric; and filling the vias and trenches with a conductive fill material.

Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.

Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.

Abstract: A method for manufacturing an MEMS device is provided. The method includes steps of a) providing a first substrate having a concavity located thereon, b) providing a second substrate having a connecting area and an actuating area respectively located thereon, c) forming plural microstructures in the actuating area, d) mounting a conducting element in the connecting area and the actuating area, e) forming an insulating layer on the conducting element and f) connecting the first substrate to the connecting area to form the MEMS device. The concavity contains the plural microstructures.

Abstract: Superconducting connections are provided to internal layers of a multi-layer circuit board structure, for example by superconducting vias.

Abstract: A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.

Abstract: A method of forming a thin film pattern includes: forming a thin film on a substrate; forming an amorphous carbon layer including first and second carbon layers on the thin film, wherein the first carbon layer is formed by one of a spin-on method and a plasma enhanced chemical vapor deposition (PECVD) method and the second carbon layer is formed by a physical vapor deposition (PVD) method; forming a hard mask layer on the amorphous carbon layer; forming a PR pattern on the hard mask layer; forming a hard mask pattern by etching the hard mask layer using the PR pattern as an etch mask; forming an amorphous carbon pattern including first and second carbon patterns by etching the amorphous carbon layer using the hard mask pattern as an etch mask; and forming a thin film pattern by etching the thin film using the amorphous carbon pattern.

Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.

Abstract: A manufacturing method of a thin film transistor made of a stack of an organic semiconductor layer, a gate insulating film and a gate electrode in this order on a substrate, which includes the steps of pattern coating a gate electrode material on the gate insulating film by printing; and carrying out a heat treatment to form the gate electrode resulting from drying for solidification of the pattern coated gate electrode material.

Abstract: There are provided a semiconductor device and a semiconductor device manufacturing method capable of preventing electrical leakage while suppressing increase of wiring resistance and deterioration of productivity. The semiconductor device manufacturing method for forming on a substrate a semiconductor device having a porous low-k film serving as an interlayer insulating film. Further, the semiconductor device manufacturing method includes forming the low-k film on the substrate; etching the low-k film to form a trench or a hole therein; reforming a surface of the low-k film exposed by etching the low-k film by allowing plasma of a nitro compound to act on the exposed surface within the trench or the hole; and filling the trench or the hole with a conductor.

Abstract: A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.

Abstract: A semiconductor component includes a carrier and multiple semiconductor substrates stacked and interconnected on the carrier. The carrier includes conductive members bonded to corresponding conductive openings on the semiconductor substrates. The component can also include terminal contacts on the carrier in electrical communication with the conductive members, and an outer member for protecting the semiconductor substrates. A method for fabricating the component includes the steps of providing the carrier with the conductive members, and providing the semiconductor substrates with the conductive openings. The method also includes the step of aligning and placing the conductive openings on the conductive members, and then bonding the conductive members to the conductive openings.

Abstract: A technique for increasing productivity by simplified steps in a manufacturing process of TFTs, electronic circuits using TFTs, and semiconductor devices formed of TFTs is provided. A method for manufacturing a semiconductor device includes forming a light absorbing layer, forming a light-transmitting layer on the light absorbing layer emitting a linear laser beam with a homogenized energy onto a mask and thereby splitting the linear laser beam into a plurality of laser beams and emitting the plurality of laser beams onto the light-transmitting layer on the light absorbing layer, and thereby forming a plurality of openings in the light-transmitting layer and the light absorbing layer.

Abstract: A method for manufacturing an image sensor including forming a microlens array over a color filter array, forming a capping layer over the semiconductor substrate including the microlens array, forming a pad mask over the capping layer, and then exposing a pad in an interlayer dielectric layer.

Abstract: Generally, the subject matter disclosed herein relates to a semiconductor device with embedded low-k metallization. A method is disclosed that includes forming a plurality of copper metallization layers that are coupled to a plurality of logic devices in a logic area of a semiconductor device and, after forming the plurality of copper metallization layers, forming a plurality of capacitors in a memory array of the semiconductor device. The capacitors are formed using a non-low-k dielectric material (k value greater than 3), while the copper metallization layers are formed in layers of low-k dielectric material (k value less than 3).

Abstract: A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second heating temperature in an oxidizing atmosphere under a second pressure in a second process chamber to selectively oxidize at least a surface of the metal film on the element isolating insulation film and form a metal oxide film; conducting third heating processing at a third heating temperature which is higher than the first heating temperature and the second heating temperature in an atmosphere in a third process chamber to increase a concentration of silicon in the silicide film; and selectively removing the metal oxide film and an unreacted part of the metal film on the element isolating insulation film.

Abstract: A method of forming an integrated circuit structure includes forming a first and a second plurality of tracks parallel to a first direction and on a wafer representation. The first and the second plurality of tracks are allocated in an alternating pattern. A first plurality of patterns is laid out on the first plurality of tracks and not on the second plurality of tracks. A second plurality of patterns is laid out on the second plurality of tracks and not on the first plurality of tracks. The first plurality of patterns is extended in the first direction and in a second direction perpendicular to the first direction, so that each of the second plurality of patterns is surrounded by portions of the first plurality of patterns, and substantially none of neighboring ones of the first plurality of patterns on the wafer representation have spacings greater than a pre-determined spacing.

Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.

Abstract: Provided are methods of forming a nano structure and method of forming a solar cell using the same. The method of forming the nano structure includes: preparing a template; ionizing a surface of the template; forming an oxide layer enclosing the template on the surface of the template; and removing the template.

Abstract: In the manufacture of electronic devices that use porous dielectric materials, the properties of the dielectric in a pristine state can be altered by various processing steps. In a method for restoring and preserving the pristine properties of a porous dielectric layer, a substrate is provided with a layer of processed porous dielectric on top, whereby the processed porous dielectric is at least partially exposed. A thin aqueous film is formed at least on the exposed parts of the processed porous dielectric. The exposed porous dielectric with the aqueous film is exposed to an ambient containing a mixture comprising at least one silylation agent and dense CO2, resulting in the restoration and preservation of the pristine properties of the porous dielectric.

Abstract: A layer of a porous insulating film precursor is formed on or over a substrate, a layer of a specific silicon compound is then formed, this silicon compound layer is pre-cured as necessary, and the porous insulating film precursor is exposed to UV through the silicon compound layer or pre-cured layer.

Abstract: Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.

Abstract: This invention provides an interlayer insulating film for a semiconductor device, which has low permittivity, is free from the evolution of gas such as CFx and SiF4 and is stable, and a wiring structure comprising the same. In an interlayer insulating film comprising an insulating film provided on a substrate layer, the interlayer insulating film has an effective permittivity of not more than 3. The wiring structure comprises an interlayer insulating film, a contact hole provided in the interlayer insulating film, and a metal filled into the contact hole. The insulating film comprises a first fluorocarbon film provided on the substrate layer and a second fluorocarbon film provided on the first fluorocarbon film.

Abstract: A manufacturing method of a circuit structure is provided as follows. Firstly, a base conductive layer is formed on the carrier board and a first patterned plating-resistant layer having at least one trench for exposing a part of the base conductive layer is formed on the base conductive layer. A first patterned conductive layer is then formed in the trench and a second patterned plating-resistant layer is formed which covers a part of the first patterned conductive layer and a part of the first patterned plating-resistant layer. A second patterned conductive layer is formed on the exposed first patterned conductive layer. The first and the second patterned plating-resistant layers and the base conductive layer exposed by the first patterned conductive layer are removed. Then, a patterned solder mask is formed for covering a part of the first patterned conductive layer.

Abstract: A method of fabricating a semiconductor device is provided. The method begins by providing a semiconductor device structure having electronic devices formed on a semiconductor substrate, and having an upper metal layer associated with electrical contacts for the electronic devices. The method continues by forming a diffusion barrier layer overlying the upper metal layer. Next, the method deposits a first layer of graded ultra-low-k (ULK) material overlying the diffusion barrier layer, a layer of ULK material overlying the first layer of graded ULK material, and a second layer of graded ULK material overlying the layer of ULK material. The method continues by depositing a layer of low temperature oxide material overlying the second layer of graded ULK material, and forming a layer of metal hard mask material overlying the layer of low temperature oxide material.

Abstract: A system and method for forming post passivation inductors, and related structures, is described. High quality electrical components, such as inductors and transformers, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Abstract: High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to provide planar and parallel sidewalls. A second set of spacers may be formed on planar and parallel sidewalls of the first set of spacers. The second set of spacers serve as a mask to form one or more circuit elements in a layer beneath the second set of spacers. The steps according to embodiments of the invention allow a recursive spacer technique to be used which results in robust, evenly spaced, spacers to be formed and used as masks for the circuit elements.

Abstract: A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The exposed portions of the dielectric layer which form the side walls of the trench are removed. A dielectric liner is then deposited on the side walls of the trench, the liner being made of a second dielectric material.

Abstract: There is provided a method of manufacturing an electronic element for forming the electronic element including one or more wiring layers and an organic insulating layer stacked on a substrate. The method includes a wiring layer formation step of forming the wiring layer on the substrate; an organic insulating layer formation step of forming an organic insulating layer on the wiring layer; and an irradiation step of irradiating a short-circuit portion of the wiring layer through the organic insulating layer with a laser beam having a wavelength transmissive through the organic insulating layer.

Abstract: A method for fabricating a semiconductor device includes the steps of (a) forming a plasma of a gas having carbon and fluorine, and forming an internal insulation film provided with a fluorine-doped carbon film formed on a substrate using the plasma; (b) forming a metal film on the internal insulation film; (c) etching the metal film according to a pattern to form a hard mask; (d) forming a concave part in the fluorine-doped carbon film by etching the fluorine-doped carbon film using the hard mask; (e) forming a film formation of a wiring material on the substrate for filling the concave part with the wiring material; (f) removing an excess part of the wiring material and the hard mask on the fluorine-doped carbon film for exposing a surface of the fluorine-doped carbon film; and (g) removing an oxide formed on the surface of the fluorine-doped film.

Abstract: A method of forming an interconnect joint includes providing a first metal layer (210, 310), providing a film (220, 320) including metal particles (221, 321) and organic molecules (222, 322), placing the film over the first metal layer, placing a second metal layer (230, 330) over the film, and sintering the metal particles such that the organic molecules degrade and the first metal layer and the second metal layer are joined together.

Abstract: A chemical mechanical polishing method comprises polishing an organic film using a slurry including polymer particles having a surface functional group and a water-soluble polymer.

Abstract: Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode structures separated by a gap; and a polymer-based ferroelectric layer overlying and directly abutting some of the electrode structures. Methods may comprise actions to form and operate the apparatus and systems. Additional apparatus, systems, and methods are disclosed.

Abstract: A film forming method includes the steps of forming a F-doped carbon film by using a source gas containing C and F, and modifying the F-doped carbon film by radicals, the source gas having a F/C ratio larger than 1 and smaller than 2, the F/C ratio being defined as a ratio of a number of F atoms to a number of C atoms in a source gas molecule.

Abstract: The present invention essentially relates to a method of preparing an electrically insulating film at the surface of an electrical conductor or semiconductor substrate, such as a silicon substrate. According to the invention, this method comprises: a) bringing said surface into contact with a liquid solution comprising: a protic solvent; at least one diazonium salt; at least one monomer that is chain-polymerizable and soluble in said protic solvent; at least one acid in a sufficient quantity to stabilize said diazonium salt by adjusting the pH of said solution to a value less than 7, preferably less than 2.5; b) the polarization of said surface according to a potentio- or galvano-pulsed mode for a duration sufficient to form a film having a thickness of at least 60 nanometers, and preferably between 80 and 500 nanometers. Application: Metallization of through-vias, especially of 3D integrated circuits.

Abstract: A cleaning solution is provided. The cleaning solution includes (a) 0.01-0.1 wt % of hydrofluoric acid (HF); (b) 1-5 wt % of a strong acid, wherein the strong acid is an inorganic acid; (c) 0.05-0.5 wt % of ammonium fluoride (NH4F); (d) a chelating agent containing a carboxylic group; (e) triethanolamine (TEA); (f) ethylenediaminetetraacetic acid (EDTA); and (g) water for balance.

Abstract: An alpha particle blocking structure and method of making the structure. The structure includes: a semiconductor substrate; a set of interlevel dielectric layers stacked from a lowermost interlevel dielectric layer closest to the substrate to a uppermost interlevel dielectric layer furthest from the substrate, each interlevel dielectric layer of the set of interlevel dielectric layers including electrically conductive wires, top surfaces of the wires substantially coplanar with top surfaces of corresponding interlevel dielectric layers; an electrically conductive terminal pad contacting a wire pad of the uppermost interlevel dielectric layer; an electrically conductive plating base layer contacting a top surface of the terminal pad; and a copper block on the plating base layer.

Abstract: There is provided a semiconductor device manufacturing apparatus and a semiconductor device manufacturing method capable of recovering a damage of a low dielectric insulating film exposed to CO2 plasma to obtain the low dielectric insulating film in a good state, thus improving performance and reliability of a semiconductor device. The semiconductor device manufacturing method includes: an etching process for etching a low dielectric insulating film formed on a substrate; a CO2 plasma process for exposing the substrate to CO2 plasma after the etching process; and a UV process for irradiating UV to the low dielectric insulating film after the CO2 plasma process.

Abstract: On an etching target film formed on a substrate, a three-layer resist is laminated. This three-layer resist includes an organic film and a resist film developed into a resist pattern. Through the resist pattern, the organic film is etched into a mask pattern through which the etching target film will be etched. The organic film is etched with plasma which is obtained by exciting a process gas containing carbon dioxide and hydrogen to the plasma state. This scheme makes it possible to form a high perpendicularity mask pattern in the organic film.

Abstract: There are provided a semiconductor device and a semiconductor device manufacturing method capable of preventing electrical leakage while suppressing increase of wiring resistance and deterioration of productivity. The semiconductor device manufacturing method for forming on a substrate a semiconductor device having a porous low-k film serving as an interlayer insulating film. Further, the semiconductor device manufacturing method includes forming the low-k film on the substrate; etching the low-k film to form a trench or a hole therein; reforming a surface of the low-k film exposed by etching the low-k film by allowing plasma of a nitro compound to act on the exposed surface within the trench or the hole; and filling the trench or the hole with a conductor.

Abstract: The present invention provides a method of remedying deterioration of an insulating film which, during the remedial treatment of an insulating film deteriorated by plasma treatment, does not leave residual remedial agent on the wiring material such as the copper wiring layer, can be conducted using a dry process, and exhibits excellent applicability to mass production. The insulating film that has been deteriorated by plasma treatment is brought into contact with a remedial agent composed of a compound with a molecular structure having at least one of a nitro group and a carbonyl group, and at least one of a hydrocarbon group and a hydrogen group.