Silicide Formation Patents (Class 438/630)
  • Patent number: 9659856
    Abstract: An integrated circuit structure includes a first conductive line, a dielectric layer over the first conductive line, a diffusion barrier layer in the dielectric layer, and a second conductive line in the dielectric layer. The second conductive line includes a first portion of the diffusion barrier layer. A via is underlying the second conductive line and electrically couples the second conductive line to the first conductive line. The via includes a second portion of the diffusion barrier layer, with the second portion of the diffusion barrier layer having a bottom end higher than a bottom surface of the via.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Lien Lee, Chun-Chieh Lin
  • Patent number: 9601519
    Abstract: A thin film transistor is provided, which includes a gate electrode on a substrate; a channel layer overlapping the gate electrode; a dielectric layer between the gate electrode and the channel layer; a source electrode and a drain electrode electrically connecting to the channel layer; a passivation layer overlying the source electrode, the drain electrode, and the gate dielectric layer, wherein the channel layer includes two contact portions being in contact with the source electrode and the drain electrode, respectively, and a non-contact portion located between the two contact portions, and wherein one of the two contact portions has a first thickness in a first direction perpendicular to a surface of the substrate, and the non-contact portion has a second thickness less than the first thickness in the first direction.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: March 21, 2017
    Assignee: INNOLUX CORPORATION
    Inventors: Hsin-Hung Lin, Jung-Fang Chang, Ker-Yih Kao
  • Patent number: 9478426
    Abstract: A number of variations may include a method that may include depositing a first layer on a first semiconductor epi layer (epitaxial layer) in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer. The layer may include a first metal and a second metal. The first semiconductor epi layer may be subjected to at least a first annealing act to provide a first structure. At least a portion of the first structure may be stripped to remove any of the first layer not reacted with silicon to form a silicide during the first annealing act. Thereafter, the stripped first structure may be subjected to a second annealing act.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: October 25, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael Thomason, Mohammed Tanvir Quddus, James Morgan, Mihir Mudholkar, Scott Donaldson
  • Patent number: 9368627
    Abstract: A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; and a stress memorization technology (SMT) sidewall spacer over a sidewall of the gate stack. The gate stack includes a gate dielectric layer over the semiconductor substrate and a gate electrode over the gate dielectric layer. The SMT sidewall spacer provides a stress for a channel region beneath the gate stack.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: June 14, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ping-Chung Liu, Wei-Chiang Hung, Hsiang-Yu Tsai, Kuo Hui Chang
  • Patent number: 9245793
    Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated species. The activated species can be used to treat the surfaces of low-k and/or ultra low-k dielectric materials to facilitate improved deposition of diffusion barrier materials.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: January 26, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Ratsamee Limdulpaiboon, Frank Greer, Chi-I Lang, J. Watanabe, Wenxian Zhu
  • Patent number: 9129854
    Abstract: A NAND flash memory chip is made by forming sacrificial control gate structures and sacrificial select structures, and subsequently replacing these sacrificial structures with metal. Filler structures are formed between sacrificial control gate structures and are subsequently removed to form air gaps between neighboring control gate lines and between floating gates.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: September 8, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Kazuya Tokunaga, Jongsun Sel, Marika Gunji-Yoneoka, Tuan Pham
  • Patent number: 9087762
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a wiring pattern made of copper, annealing the wiring pattern in an atmosphere of inert gas, and performing plasma processing on the wiring pattern using a reducing gas after the annealing. A temperature in the plasma processing is equal to or below a temperature in the annealing.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: July 21, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akihiro Kawano, Hiroaki Sano
  • Patent number: 9023728
    Abstract: According to one embodiment, a method of manufacturing a metal silicide layer, the method includes forming a metal layer including impurities on a silicon layer by a vapor deposition method using a gas of a metal and a gas of the impurities, and forming a metal silicide layer including the impurities by chemically reacting the metal layer with the silicon layer. A thickness and a composition of the metal silicide layer are controlled by an amount of the impurities in the metal layer.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Makoto Honda
  • Patent number: 8993390
    Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 31, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chih Lai, Chia Chang Hsu, Nien-Ting Ho, Bor-Shyang Liao, Shu Min Huang, Min-Chung Cheng, Yu-Ru Yang
  • Patent number: 8956968
    Abstract: A method for fabricating a metal silicide interconnect in a stacked 3D non-volatile memory array. A stack of alternating layers of undoped/lightly doped polysilicon and heavily doped polysilicon is formed on a substrate. Memory holes are etched in cell areas of the stack while an interconnect area is protected. Slits are etched in the cell areas and the interconnect areas. A wet etch is performed via the slits or the memory holes in the cell area to remove portions of the undoped/lightly doped polysilicon layers in the cell area, and dielectric is deposited. Silicidation transforms portions of the heavily doped polysilicon layers in the cell area to metal silicide, and transforms portions of the heavily doped and undoped/lightly doped polysilicon layers in the interconnect area to metal silicide. The metal silicide interconnect can be used for routing power and control signals from below the stack to above the stack.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: February 17, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Masaaki Higashitani, Peter Rabkin
  • Patent number: 8956961
    Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: February 17, 2015
    Assignee: Rexchip Electronics Corporation
    Inventors: Kazuaki Takesako, Wen-Kuei Hsu, Yoshinori Tanaka, Yukihiro Nagai, Chih-Wei Hsiung, Hirotake Fujita, Tomohiro Kadoya, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang
  • Patent number: 8933566
    Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: January 13, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Lo Yueh Lin
  • Patent number: 8927422
    Abstract: A method for forming a raised silicide contact including depositing a layer of silicon at a bottom of a contract trench using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide, a width of the silicide and the contact trench are substantially equal; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° C. in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Nathaniel Berliner, Christian Lavoie, Kam-Leung Lee, Ahmet Serkan Ozcan
  • Patent number: 8927410
    Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: January 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Dave Pratt, Andy Perkins
  • Patent number: 8889552
    Abstract: A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangline Park, Boun Yoon, Jeongnam Han, Kee-Sang Kwon, Byung-Kwon Cho, Wongsang Choi
  • Patent number: 8865556
    Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph S. Newbury, Kenneth Parker Rodbell, Zhen Zhang, Yu Zhu
  • Patent number: 8828853
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming an amorphous semiconductor film on a substrate. The method further includes annealing the amorphous semiconductor film by irradiating the substrate with a microwave to form a polycrystalline semiconductor film from the amorphous semiconductor film. The method further includes forming a transistor whose channel is the polycrystalline semiconductor film.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonori Aoyama, Kiyotaka Miyano
  • Patent number: 8810008
    Abstract: A semiconductor element-embedded substrate includes a semiconductor element; a chip component; a peripheral insulating layer covering at least the outer circumferential side surfaces thereof; an upper surface-side wiring line provided on the upper surface side of the substrate; and a lower surface-side wiring line provided on the lower surface side of the substrate. The built-in semiconductor element includes a terminal on the upper surface side thereof, and this terminal is electrically connected to the upper surface-side wiring line. The built-in chip component includes an upper surface-side terminal electrically connected to the upper surface-side wiring line; a lower surface-side terminal electrically connected to the lower surface-side wiring line; and a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: August 19, 2014
    Assignee: NEC Corporation
    Inventors: Kentaro Mori, Shintaro Yamamichi, Hideya Murai, Katsumi Kikuchi, Yoshiki Nakashima, Daisuke Ohshima
  • Patent number: 8790969
    Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. Several devices are, thus, provided. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: July 29, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Mondo, Markus Gerhard Andreas Muller, Thomas Kormann
  • Patent number: 8785322
    Abstract: Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Christian Lavoie, Vijay Narayanan
  • Patent number: 8785310
    Abstract: A method is provided for forming a metal silicide layer on a substrate. According to one embodiment the method includes providing the substrate in a process chamber, exposing the substrate at a first substrate temperature to a plasma generated from a deposition gas containing a metal precursor, where the plasma exposure forms a conformal metal-containing layer on the substrate in a self-limiting process. The method further includes exposing the metal-containing layer at a second substrate temperature to a reducing gas in the absence of a plasma, where the exposing steps are alternatively performed at least once to form the metal silicide layer, and the deposition gas does not contain the reducing gas. The method provides conformal metal silicide formation in deep trenches with high aspect ratios.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: July 22, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Toshio Hasegawa, Kunihiro Tada, Hideaki Yamasaki, David L. O'Meara, Gerrit J. Leusink
  • Patent number: 8778795
    Abstract: In sophisticated metallization systems of semiconductor devices, a sensitive core metal, such as copper, may be efficiently confined by a conductive barrier material comprising a copper/silicon compound, such as a copper silicide, which may provide superior electromigration behavior and higher electrical conductivity compared to conventionally used tantalum/tantalum nitride barrier systems.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: July 15, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ronny Pfuetzner, Jens Heinrich
  • Patent number: 8778796
    Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: July 15, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Lo Yueh Lin
  • Publication number: 20140103402
    Abstract: The present invention provides a semiconductor structure including at least a contact plug. The structure includes a substrate, a transistor, a first ILD layer, a second ILD layer and a first contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor and levels with a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The first contact plug is disposed in the first ILD layer and the second ILD layer and includes a first trench portion and a first via portion, wherein a boundary of the first trench portion and a first via portion is higher than the top surface of the gate. The present invention further provides a method of making the same.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Po-Chao Tsao
  • Patent number: 8673724
    Abstract: Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Doo-Sung Yun, Bo-Un Yoon, Jeong-Nam Han
  • Patent number: 8658530
    Abstract: An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: February 25, 2014
    Assignees: International Business Machines Corporation, GlobalFoundries Inc.
    Inventors: Marwan H. Khater, Christian Lavoie, Bin Yang, Zhen Zhang
  • Patent number: 8658485
    Abstract: There is provided a semiconductor device and a method of fabricating the same. The method of fabricating a semiconductor device according to the present invention comprises: forming a transistor structure including a gate, and source and drain regions on a semiconductor substrate; carrying out a first silicidation to form a first metal silicide layer on the source and drain regions; depositing a first dielectric layer on the substrate, the top of the first dielectric layer being flush with the top of the gate region; forming contact holes at the portions corresponding to the source and drain regions in the first dielectric layer; and carrying out a second silicidation to form a second metal silicide at the gate region and in the contact holes, wherein the first metal silicide layer is formed to prevent silicidation from occurring at the source and drain regions during the second silicidation.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: February 25, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zhijiong Luo, Haizhou Yin, Huilong Zhu
  • Patent number: 8642435
    Abstract: A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: February 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Po-Chi Wu, Chang-Yin Chen, Zhe-Hao Zhang, Yi-Chen Huang
  • Patent number: 8610233
    Abstract: A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: December 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi
  • Patent number: 8603881
    Abstract: A contact via hole is formed through at least one dielectric layer over a semiconductor substrate. A semiconductor material is deposited at the bottom of the contact via hole and atop the at least one dielectric layer by ion cluster deposition. An angled oxygen cluster deposition is performed to convert portions of the semiconductor material on the top surface of the at least one dielectric layer into a semiconductor oxide, while oxygen is not implanted into the deposited semiconductor material at the bottom of the contact via hole. A metal semiconductor alloy is formed at the bottom of the contact hole by deposition of a metal and an anneal. The semiconductor oxide at the top of the at least one dielectric layer can be removed during a preclean before metal deposition, a postclean after metal semiconductor alloy formation, and/or during planarization for forming contact via structures.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Ahmet S. Ozcan, Viraj Y. Sardesai, Cung D. Tran
  • Patent number: 8569170
    Abstract: It is an object of the present invention to obtain a transistor with a high ON current including a silicide layer without increasing the number of steps. A semiconductor device comprising the transistor includes a first region in which a thickness is increased from an edge on a channel formation region side and a second region in which a thickness is more uniform than that of the first region. The first and second region are separated by a line which is perpendicular to a horizontal line and passes through a point where a line, which passes through the edge of the silicide layer and forms an angle ? (0°<?<45°) with the horizontal line, intersects with an interface between the silicide layer and an impurity region, and the thickness of the second region to a thickness of a silicon film is 0.6 or more.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Hajime Tokunaga
  • Patent number: 8563424
    Abstract: Methods for forming cobalt silicide are provided. One method for forming a cobalt silicide material includes exposing a substrate having a silicon-containing material to either a wet etch solution or a pre-clean plasma during a first step and then to a hydrogen plasma during a second step of a pre-clean process. The method further includes depositing a cobalt metal layer on the silicon-containing material by a CVD process, heating the substrate to form a first cobalt silicide layer comprising CoSi at the interface of the cobalt metal layer and the silicon-containing material during a first annealing process, removing any unreacted cobalt metal from the substrate during an etch process, and heating the substrate to form a second cobalt silicide layer comprising CoSi2 during a second annealing process.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: October 22, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Seshadri Ganguli, Sang-Ho Yu, See-Eng Phan, Mei Chang, Amit Khandelwal, Hyoung-Chan Ha
  • Patent number: 8551874
    Abstract: A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals.
    Type: Grant
    Filed: May 8, 2010
    Date of Patent: October 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Soon-Cheon Seo, Bruce B. Doris, Chih-Chao Yang
  • Publication number: 20130252416
    Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 26, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro TAKEDA, Takao KUMIHASHI, Hiroshi YANAGITA, Takashi TAKEUCHI, Yasushi MATSUDA
  • Patent number: 8536010
    Abstract: Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: September 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Nieh, Hung-Chang Hsu, Wen-Chi Tsai, Mei-Yun Wang, Chii-Ming Wu, Wei-Jung Lin, Chih-Wei Chang
  • Publication number: 20130234230
    Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 12, 2013
    Inventors: Kazuaki Takesako, Wen-Kuei Hsu, Yoshinori Tanaka, Yukihiro Nagai, Chih-Wei Hsiung, Hirotake Fujita, Tomohiro Kadoya, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang
  • Publication number: 20130200461
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL.
    Type: Application
    Filed: February 8, 2012
    Publication date: August 8, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chu Liu, Kuei Shun Chen, Mu-Chi Chiang, Yao-Kwang Wu, Bi-Fen Wu, Huan-Just Lin, Hsiao-Tzu Lu, Hui-Chi Huang
  • Patent number: 8492275
    Abstract: Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: July 23, 2013
    Assignees: International Business Machines Corporation, GlobalFoundries, Inc.
    Inventors: Emre Alptekin, Viraj Y. Sardesai, Cung D. Tran, Bin Yang
  • Patent number: 8481378
    Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake at a temperature lower or equal to 800° C., a subsequent deposition step will prevent deposition in the first surface region. This allows selective deposition in the second surface region, which is not doped with the Boron (or doped with another dopant or not doped). Several devices are, thus, provided. The method saves a usual photolithography sequence, which according to prior art is required for selective deposition of Si or SiGe in the second surface region.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: July 9, 2013
    Assignees: STMicroelectronics (Crolles 2) SAS, NXP B.V.
    Inventors: Alexandre Mondot, Markus Gerhard Andreas Muller, Thomas Kormann
  • Patent number: 8470707
    Abstract: A process for forming an integrated circuit with reduced sidewall spacers to enable improved silicide formation between minimum spaced transistor gates. A process for forming an integrated circuit with reduced sidewall spacers by first forming sidewall spacer by etching a sidewall dielectric and stopping on an etch stop layer, implanting source and drain dopants self aligned to the sidewall spacers, followed by removing a portion of the sidewall dielectric and removing the etch stop layer self aligned to the reduced sidewall spacers prior to forming silicide.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: June 25, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Weize Xiong, Deborah J. Riley
  • Publication number: 20130130495
    Abstract: A method for fabricating a metal silicide interconnect in a stacked 3D non-volatile memory array. A stack of alternating layers of undoped/lightly doped polysilicon and heavily doped polysilicon is formed on a substrate. Memory holes are etched in cell areas of the stack while an interconnect area is protected. Slits are etched in the cell areas and the interconnect areas. A wet etch is performed via the slits or the memory holes in the cell area to remove portions of the undoped/lightly doped polysilicon layers in the cell area, and dielectric is deposited. Silicidation transforms portions of the heavily doped polysilicon layers in the cell area to metal silicide, and transforms portions of the heavily doped and undoped/lightly doped polysilicon layers in the interconnect area to metal silicide. The metal silicide interconnect can be used for routing power and control signals from below the stack to above the stack.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 23, 2013
    Inventors: Masaaki Higashitani, Peter Rabkin
  • Patent number: 8440564
    Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: May 14, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
  • Patent number: 8378496
    Abstract: The interlayer connection of the substrate is formed by a contact-hole filling (4) of a semiconductor layer (11) and metallization (17) of a recess (16) in a reverse-side semiconductor layer (13), wherein the semiconductor layers are separated from each other by a buried insulation layer (12), at whose layer position the contact-hole filling or the metallization ends.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: February 19, 2013
    Assignee: austriamicrosystems AG
    Inventors: Franz Schrank, Martin Schrems, Jochen Kraft
  • Patent number: 8368219
    Abstract: A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: February 5, 2013
    Assignees: Advanced Micro Devices, Inc., Spansion LLC
    Inventors: Arvind Halliyal, Zoran Krivokapic, Matthew S. Buynoski, Nicholas H. Tripsas, Minh Van Ngo, Mark T. Ramsbey, Jeffrey A. Shields, Jusuke Ogura
  • Patent number: 8367549
    Abstract: Provided is a method of manufacturing a semiconductor device. In the method, after a thin liner is formed on a substrate on which a lower interconnection is formed, a silicon source is supplied to form a silicide layer under the liner by a reaction between the silicon source and the lower interconnection, and the silicide layer is nitrided and an etch stop layer is formed. Therefore, the lower interconnection is prevented from making contact with the silicon source, variations of the surface resistance of the lower interconnection can be prevented, and thus high-speed devices can be fabricated.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: February 5, 2013
    Assignee: Wonik IPS Co., Ltd.
    Inventor: Young Soo Kwon
  • Patent number: 8344461
    Abstract: A MOS solid-state imaging device having: a semiconductor substrate provided with a pair of source and drain regions in a pixel area, the pair of source and drain regions constituting part of a transistor in the pixel area; an insulating film formed over the semiconductor substrate; a wiring layer formed over the insulating film; and a contact plug penetrating through the insulating film to connect either one of the pair of source and drain regions with the wiring layer, wherein a surface area of said one of the pair of source and drain regions is silicided, the surface area contacting with the contact plug, and a width of the surface area is equal to a width of the contact plug.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: January 1, 2013
    Assignee: Panasonic Corporation
    Inventor: Tomotsugu Takeda
  • Patent number: 8343867
    Abstract: The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: January 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jin-Aun Ng, Yu-Ying Hsu, Chi-Ju Lee, Sin-Hua Wu, Bao-Ru Young, Harry-Hak-Lay Chuang
  • Patent number: 8330275
    Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Patent number: 8329582
    Abstract: A semiconductor device comprises insulating layer including damascene patterns and formed over a semiconductor substrate, conductive line formed higher than the insulating layer within the respective damascene patterns, and interference-prevention grooves formed within the damascene patterns between sidewalls of the conductive line and the insulating layer.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Tae Kyung Kim
  • Patent number: 8314454
    Abstract: A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: November 20, 2012
    Assignee: Spansion LLC
    Inventor: Simon S. Chan