Simultaneously By Chemical And Mechanical Means Patents (Class 438/633)
  • Patent number: 11018021
    Abstract: A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Kuo Hsieh, Tsung-Hung Chu, Ming-Chung Liang
  • Patent number: 10847529
    Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in the process of selectively depositing a landing pad in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface. The method also includes forming a barrier layer on the stepped structure, forming a mask layer on the barrier layer and exposing at least a portion of the barrier layer by etching at least a portion of the mask layer with a first etching solution The method further includes etching the exposed barrier layer with a second etching solution and etching the mask layer with a third etching solution.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 24, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo
  • Patent number: 10804112
    Abstract: A planarization structure is formed with a planar upper face enclosing a relief projecting from a planar substrate. The process used deposits a layer of a first material over the reliefs and then forms a layer of a second material with a planar upper face. This second material may be etched selectively with respect to the first material. The second layer is processed so that the protuberances of the first material are uncovered. A planarizing is then performed on the first material as far as the layer of the second material by selective chemical-mechanical polishing with respect to the second material.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: October 13, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Loic Gaben
  • Patent number: 10763120
    Abstract: A technique to inhibit the growth of colloidal silica deposits on surfaces treated in phosphoric acid is described. In one embodiment, the disclosed techniques include the use of a colloidal silica growth inhibitor as an additive to a phosphoric acid solution utilized for a silicon nitride etch. In some embodiments, the additive may have chemistry that may contain strong anionic groups. A method and apparatus is provided that monitors the silica concentration and/or the colloidal silica growth inhibitor concentration in the phosphoric acid solution during processing and adjusts the amount of those components as needed. Techniques are provided for a method and apparatus to control the additive concentration to be used as well as the silica concentration in the phosphoric acid solution. The techniques described herein provide a high selectivity etch of silicon nitride towards silicon dioxide without the growth of colloidal silica deposits on the exposed surfaces.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: September 1, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Antonio L. P. Rotondaro, Wallace P. Printz
  • Patent number: 10658270
    Abstract: A semiconductor structure includes a semiconductor substrate and a conductive feature formed over the semiconductor substrate, an etch stop layer formed over the conductive feature, a dielectric layer formed over the etch stop layer, and a contact formed in a contact trench within the dielectric layer. The bottom of the contact is disposed over a top surface of the conductive feature. The semiconductor structure further includes a self-aligned sealing oxide layer formed on the dielectric layer. The self-aligned sealing oxide layer directly contacts the dielectric layer from a bottom-most portion of the self-aligned sealing oxide layer to a top-most portion of the self-aligned sealing oxide layer.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsiang-Wei Lin
  • Patent number: 10570316
    Abstract: A chemical mechanical polishing (CMP) composition (Q) comprising (A) Colloidal or fumed inorganic particles (A) or a mixture thereof in a total amount of from 0.0001 to 2.5 wt.-% based on the total weight of the respective CMP composition (B) at least one amino acid in a total amount of from 0.2 to 1 wt.-% based on the total weight of the respective CMP composition (C) at least one corrosion inhibitor in a total amount of from 0.001 to 0.02 wt.-% based on the total weight of the respective CMP composition (D) hydrogen peroxide as oxidizing agent in a total amount of from 0.0001 to 2 wt.-% based on the total amount of the respective CMP composition (E) aqueous medium wherein the CMP composition (Q) has a pH in the range of from 6 to 9.5.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: February 25, 2020
    Assignee: BASF SE
    Inventors: Robert Reichardt, Max Siebert, Yongqing Lan, Michael Lauter, Haci Osman Guevenc, Julian Proelss, Sheik Ansar Usman Ibrahim, Reza Golzarian
  • Patent number: 10541228
    Abstract: A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: January 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chen-Hua Yu
  • Patent number: 10494547
    Abstract: An additive composition and a positive polishing slurry composition including the additive composition are provided. The additive composition includes a cationic compound, an organic acid, a nonionic compound, and a pH adjuster.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 3, 2019
    Assignee: KCTECH CO., LTD.
    Inventors: Jang Kuk Kwon, Sung Pyo Lee, Chang Gil Kwon, Jun Ha Hwang
  • Patent number: 10475794
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first bit line structure on a substrate; forming a first spacer adjacent to the first bit line structure; forming an interlayer dielectric (ILD) layer adjacent to the first spacer; removing part of the ILD layer and part of the first spacer to expose a sidewall of the first bit line structure; and forming a first storage node contact isolation structure adjacent to the first bit line structure, wherein the first storage node contact isolation structure contacts the first bit line structure and the first spacer directly.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: November 12, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Han Wu, Fu-Che Lee, Chien-Cheng Tsai, Tzu-Tsen Liu, Wen-Chieh Lu
  • Patent number: 10403563
    Abstract: A semiconductor structure includes a semiconductor substrate and a conductive feature formed over the semiconductor substrate, an etch stop layer formed over the conductive feature, a dielectric layer formed over the etch stop layer, a contact trench formed in the dielectric layer, a bottom of the contact trench being disposed over a top surface of the conductive feature, and a self-aligned sealing oxide layer formed on the dielectric layer. The self-aligned sealing oxide layer is conformed to sidewalls of the dielectric layer exposed in the contact trench.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsiang-Wei Lin
  • Patent number: 10181408
    Abstract: A process for chemical mechanical polishing a substrate containing tungsten is disclosed to reduce corrosion rate and inhibit dishing of the tungsten and erosion of underlying dielectrics. The process includes providing a substrate; providing a polishing composition, containing, as initial components: water; an oxidizing agent; a polyglycol or polyglycol derivative; a dicarboxylic acid, a source of iron ions; a colloidal silica abrasive; and, optionally a pH adjusting agent; providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the tungsten (W) is polished away from the substrate, corrosion rate is reduced, dishing of the tungsten (W) is inhibited as well as erosion of dielectrics underlying the tungsten (W).
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: January 15, 2019
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Lin-Chen Ho, Wei-Wen Tsai, Cheng-Ping Lee
  • Patent number: 10130916
    Abstract: The present disclosure is directed to biomimetic membranes and methods of manufacturing such membranes that include structural features that mimic the structures of cellular membrane channels and produce membrane designs capable of high selectivity and high permeability or absorptivity. The membrane structure, material and chemistry can be selected to perform liquid separations, gas separation and capture, ion transport and adsorption for a variety of applications.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: November 20, 2018
    Assignees: National Technology & Engineering Solutions of Sandia, LLC, The Regents of the University of New Mexico
    Inventors: Susan Rempe, C. Jeffrey Brinker, David Michael Rogers, Ying-Bing Jiang, Shaorong Yang
  • Patent number: 10134674
    Abstract: A method of fabricating a metallization layer of a semiconductor device in which copper is used for an interconnect material and cobalt is used to encapsulate the copper. A material is introduced that will interact with the cobalt to cause a hexagonal-close-packed (HCP) crystal structure of cobalt to change to a face-centered-cubic (FCC) crystal structure of cobalt, the FCC crystal structure providing a resistance of the cobalt to migrate.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, James J. Kelly, Koichi Motoyama, Roger Allan Quon, Michael Rizzolo, Theodorus Eduardus Standaert
  • Patent number: 9953834
    Abstract: A method includes providing a structure having a dielectric layer, a 1st hardmask layer, a 2nd hardmask layer and a 1st mandrel layer disposed respectively thereon. A 1st mandrel plug is disposed in the 1st mandrel layer. A 2nd mandrel layer is disposed over the 1st mandrel layer. The 1st and 2nd mandrel layers are etched to form a plurality 1st mandrels, wherein the 1st mandrel plug extends entirely through a single 1st mandrel. The 1st mandrel plug is etched such that it is self-aligned with sidewalls of the single 1st mandrel. The 1st mandrels are utilized to form mandrel metal lines in the dielectric layer. The 1st mandrel plug is utilized to form a self-aligned mandrel continuity cut in a single mandrel metal line formed by the single 1st mandrel.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: April 24, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Sun, Ruilong Xie, Xunyuan Zhang, Ryan Ryoung-Han Kim
  • Patent number: 9899532
    Abstract: A thin-film transistor (TFT) and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display apparatus are provided. The method for manufacturing the TFT includes: forming a gate electrode, a gate insulating layer, a metal oxide semiconductor active layer, a source electrode and a drain electrode on a substrate; the forming the metal oxide semiconductor active layer includes: forming the metal oxide semiconductor active layer by electrochemical reaction. The method for manufacturing the TFT is applied in the production of the TFT and the array substrate and the display apparatus comprising the TFTs and provides a new method for forming the metal oxide semiconductor active layer.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: February 20, 2018
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Chunsheng Jiang, Xuyuan Li, Wei Liu
  • Patent number: 9859120
    Abstract: A method includes providing a structure having a dielectric layer, a 1st hardmask layer, a 2nd hardmask layer and a 1st mandrel layer disposed respectively thereon. A 1st mandrel plug is disposed in the 1st mandrel layer. A 2nd mandrel layer is disposed over the 1st mandrel layer. The 1st and 2nd mandrel layers are etched to form a plurality 1st mandrels, wherein the 1st mandrel plug extends entirely through a single 1st mandrel. The 1st mandrel plug is etched such that it is self-aligned with sidewalls of the single 1st mandrel. The 1st mandrels are utilized to form mandrel metal lines in the dielectric layer. The 1st mandrel plug is utilized to form a self-aligned mandrel continuity cut in a single mandrel metal line formed by the single 1st mandrel.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: January 2, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Sun, Ruilong Xie, Xunyuan Zhang, Ryan Ryoung-Han Kim
  • Patent number: 9589972
    Abstract: An ultraviolet-erasable nonvolatile semiconductor device has a protective film comprised of a silicon nitride film on which is laminated a silicon oxynitride film. The silicon nitride film has a thickness of 1000 ? or more and 2000 ? or less and the silicon oxynitride film has a thickness of about 7000 ? or more. The silicon nitride film and the silicon oxynitride film cooperate to prevent moisture from penetrating into the ultraviolet-erasable nonvolatile semiconductor device. The thickness of the silicon nitride film is set so that the time for erasing data in a nonvolatile semiconductor storage element through irradiation with ultraviolet rays is not increased.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: March 7, 2017
    Assignee: SII Semiconductor Corporation
    Inventor: Tetsuo Someya
  • Patent number: 9583348
    Abstract: Methods of treating metal-containing thin films, such as films comprising titanium carbide, with a silane/borane agent are provided. In some embodiments a film comprising titanium carbide is deposited on a substrate by an atomic layer deposition (ALD) process. The process may include a plurality of deposition cycles involving alternating and sequential pulses of a first source chemical that comprises titanium and at least one halide ligand, a second source chemical comprising metal and carbon, wherein the metal and the carbon from the second source chemical are incorporated into the thin film, and a third source chemical, wherein the third source chemical is a silane or borane that at least partially reduces oxidized portions of the titanium carbide layer formed by the first and second source chemicals. In some embodiments treatment forms a capping layer on the metal carbide film.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: February 28, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventors: Jerry Chen, Vladimir Machkaoutsan, Brennan Milligan, Jan Maes, Suvi Haukka, Eric Shero, Tom Blomberg, Dong Li
  • Patent number: 9548238
    Abstract: A method for manufacturing a semiconductor device, comprises forming an organic planarization layer on a plurality of gates on a substrate, wherein the plurality of gates each include a spacer layer thereon, forming an oxide layer on the organic planarization layer, removing a portion of the oxide layer to expose the organic planarization layer, stripping the organic planarization layer to form a cavity, patterning a direct lithographically-patternable gap dielectric on at least one of the gates in the cavity, and depositing a conductive contact in a remaining portion of the cavity.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: January 17, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Szu-Lin Cheng, Jack O. Chu, Isaac Lauer, Jeng-Bang Yau
  • Patent number: 9549456
    Abstract: Solid state flow control devices, solid state heating sources, and plasma actuators are provided. A plasma actuator can include at least one powered electrode separated from at least one grounded electrode by a dielectric material. The dielectric material can be a ferroelectric material or a silica aerogel. Solid state flow control devices and solid state heating sources can include at least one such plasma actuator.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: January 17, 2017
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Subrata Roy, Ryan Durscher
  • Patent number: 9406677
    Abstract: A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region; and forming at least one first dummy gate in the first region and at least one second dummy gate in the second region. Further, the method includes forming a dielectric layer with a top surface leveling with a surface of the first dummy gate on the semiconductor substrate; oxidizing a top portion of the second dummy gate to form a protective layer to prevent over-polishing on the second region; removing the first dummy gate to form a first gate trench; forming a first metal layer to fill the first gate trench and cover the protective layer and the dielectric layer; and removing a portion of the first metal layer higher than the dielectric layer to form a first metal gate in the first gate trench.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: August 2, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Qun Shao
  • Patent number: 9406557
    Abstract: Provided is a method of forming a copper (Cu) wiring in a recess formed to have a predetermined pattern in an insulating film formed on a surface of a substrate. The method includes: forming a barrier film at least on a surface of the recess, the barrier film serving as a barrier for blocking diffusion of Cu; forming a Ru film on the barrier film by Chemical Mechanical Deposition (CVD); forming a Cu alloy film on the Ru film by Physical Vapor Deposition (PVD) to bury the recess; forming a Cu wiring using the Cu alloy film buried in the recess; and forming a dielectric film on the Cu wiring.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: August 2, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Osamu Yokoyama, Cheonsoo Han, Takashi Sakuma, Chiaki Yasumuro, Tatsuo Hirasawa, Tadahiro Ishizaka, Kenji Suzuki
  • Patent number: 9396959
    Abstract: The present invention provides a method of fabricating a semiconductor device including forming stop layers (32) that include silicon oxy-nitride films above a semiconductor substrate, forming a cover film (34) between and on the stop layers, in which a top surface of the cover film above a region between the stop layers is higher than top surfaces of the stop layers, and polishing the cover film to the stop layers by using ceria slurry, and also provides a semiconductor device including metal layers (30) provided above a semiconductor substrate, silicon oxy-nitride films (32) provided on the metal layers, and an embedded layer (36) provided between the metal layers to have a top surface substantially coplanar with top surfaces of the silicon oxy-nitride films. According to the present invention, it is possible to provide a semiconductor device having a film of excellent planarization on a surface thereof and fabrication method therefor.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: July 19, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Takayuki Enda, Masayuki Moriya
  • Patent number: 9394163
    Abstract: A method for producing a dielectric layer on the surface of a component is described. In particular embodiments, a dielectric layer having a planar surface can be generated over a substrate topography having raised structures. In a trimming process, a component property, which depends on the thickness or the third topography of the dielectric layer, is adjusted.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: July 19, 2016
    Assignee: EPCOS AG
    Inventors: Charles Binninger, Christoph Eggs, Bruno Fuerbacher, Ulrich Knauer, Manfred Maisch, Helmut Zottl
  • Patent number: 9282626
    Abstract: Disclosed are a printed circuit board and a method for manufacturing the same. The method for manufacturing the printed circuit board includes forming a base circuit board including a cavity circuit pattern in a cavity region on upper and lower portions of a substrate and internal circuit layers outside the cavity region, forming a cavity separation layer on the cavity circuit pattern, forming at least one pair of an insulating layer and a circuit layer on the base circuit board, cutting the insulating layer and the cavity separation layer provided on an etch stop pattern by controlling a focal length of a laser beam such that the laser beam reaches a surface of the base circuit board, and removing the insulating layer by separating the cavity separation layer to form the cavity. The cavity separation layer is formed on the cavity circuit pattern, and the resultant structure is cut to the cavity separation layer by using a laser so that the insulating layer is separated.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: March 8, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jae Hyoun Yoo, Hyung Jong Kim, Jun Soo Park, Ki Yong Lee, Jin Goo Jeon
  • Patent number: 9275960
    Abstract: A method of forming a semiconductor device includes depositing a metal spacer over a core supported by a first extremely low-k dielectric layer having metal contacts embedded therein, etching away an upper portion of the metal spacer to expose the core between remaining lower portions of the metal spacer, removing the core from between the remaining lower portions of the metal spacer, and depositing a second extremely low-k dielectric layer over the remaining lower portions of the metal spacer.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chieh Yao, Cheng-Hsiung Tsai, Chung-Ju Lee, Hsiang-Huan Lee
  • Patent number: 9245797
    Abstract: Methods of forming conductive structures and the conductive structures are disclosed. A method includes forming an opening in a dielectric layer over a substrate, performing a cleaning process on the dielectric layer with the opening, forming a nucleation layer in the opening, etching the nucleation layer in the opening, and forming a conductive material in the opening and on the nucleation layer after the etching. An upper portion of the opening is distal from the substrate, and a lower portion of the opening is proximate the substrate. After the etching, a thickness of an upper portion of the nucleation layer in the upper portion of the opening is less than a thickness of a lower portion of the nucleation layer in the lower portion of the opening.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-I Tsai, Chi-Yuan Chen, Wei-Jung Lin, Chia-Han Lai
  • Patent number: 9196501
    Abstract: According to one embodiment, a method for chemical planarization includes: preparing a treatment liquid containing a hydrosilicofluoric acid aqueous solution containing silicon dioxide dissolved therein at a saturated concentration; and decreasing height of irregularity of a silicon dioxide film. In the decreasing, dissolution rate of convex portions is made larger than dissolution rate of concave portion of the irregularity while changing equilibrium state of the treatment liquid at areas being in contact with the convex portions of the irregularity, in a state in which the silicon dioxide film having the irregularity is brought into contact with the treatment liquid.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: November 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masako Kodera, Yukiteru Matsui
  • Patent number: 9184168
    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: November 10, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-In Ryu, Taiheui Cho, Keunnam Kim, Kyehee Yeom, Junghwan Park, Hyeon-Woo Jang
  • Patent number: 9171801
    Abstract: A structure including a first interconnect including a first line overlying a first via and a second interconnect including a second line overlying a second via. The first line and the second line are co-planar. The first interconnect comprises a first conductor, the first conductor comprises a metal silicide including titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, molybdenum silicide, tantalum silicide, or some combination thereof. The second interconnect comprises a second conductor, the second conductor comprising copper.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 9159696
    Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. A via opening extends through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer. A mask on the top surface of the passivation layer includes a mask opening that is aligned with the via opening. A conductive layer is selectively formed in the via opening and the mask opening. The conductive layer projects above the top surface of the passivation layer. The method further includes planarizing the passivation layer and the conductive layer to define a plug in the via opening that is coupled with the metal line.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: October 13, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Ekta Misra, Christopher D. Muzzy, Wolfgang Sauter
  • Patent number: 9129967
    Abstract: A method of forming an interconnect structure of an integrated circuit including providing a first dielectric layer disposed on a semiconductor substrate. A via (or via hole) is etched in the first dielectric layer. A conductive layer including copper is formed that fills the via hole and has a first portion that is disposed on a top surface of the first dielectric layer. A trench is formed in the first portion of the conductive layer to pattern a copper interconnect line disposed on the first dielectric layer. The trench is filled with a second dielectric material. In an embodiment, a barrier layer is self-formed during the removal of a masking element used in the etching of the trench.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Tsung-Min Huang
  • Patent number: 9093387
    Abstract: A stack of a dielectric material layer and a metallic material layer are formed on a substrate. A first organic planarization layer, a non-metallic hard mask layer, and a photoresist layer are sequentially deposited over the metallic material layer. The photoresist layer is lithographically patterned, and the pattern in the photoresist layer is transferred through the non-metallic hard mask layer, the first organic planarization layer, and the metallic material layer to form a cavity. A second organic planarization layer is deposited within the cavity and over remaining portions of the photoresist layer. The second organic planarization layer and the photoresist layer are recessed, and the non-metallic hard mask layer is subsequently removed. Remaining portions of the first and second organic planarization layers are simultaneously removed to provide physically exposed surfaces of the patterned metallic material layer and a top surface of the dielectric material layer.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Scott D. Allen, Kuang-Jung Chen, Huihang Dong, Wai-Kin Li
  • Patent number: 8991042
    Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 31, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Manabu Sakamoto, Tetsuya Shirasu, Naoki Idani
  • Patent number: 8980715
    Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 8975179
    Abstract: The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Hao Tu, Weilun Hong, Ying-Tsung Chen, Liang-Guang Chen
  • Publication number: 20150054136
    Abstract: A method of providing a via hole and routing structure includes: providing a substrate wafer having recesses and blind holes provided in the surface of the wafer; providing an insulating layer in the recesses and holes; metallizing the holes and recesses; and removing the oxide layer in the bottom of the holes to provide contact between the back side and the front side of the wafer. A semiconductor device, including a substrate having at least one metallized via extending through the substrate and at least one metallized recess forming a routing together with the via. There is an oxide layer on the front side field and on the back side field. The metal in the recess and the via is flush with the oxide on the field on at least the front side, whereby a flat front side is provided. The thickness of the semiconductor device is <300 ?m.
    Type: Application
    Filed: March 28, 2013
    Publication date: February 26, 2015
    Applicant: SILEX MICROSYSTEMS AB
    Inventors: Thorbjorn Ebefors, Daniel Perttu
  • Patent number: 8956967
    Abstract: A method of forming an interconnection structure includes forming an opening in an insulation film by a dry etching process that uses an etching gas containing fluorine; cleaning a bottom surface and a sidewall surface of the opening by exposing to a superheated steam; covering the bottom surface and the sidewall surface of the opening with a barrier metal film; depositing a conductor film on the insulation film via the barrier metal film to fill the opening with the conductor film; forming an interconnection pattern by the conductor film in the opening by polishing the conductor film and the barrier metal film underneath the conductor film by a chemical mechanical polishing process until a surface of the insulation film is exposed.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: February 17, 2015
    Assignee: Fujitsu Limited
    Inventors: Shirou Ozaki, Yoshihiro Nakata
  • Patent number: 8951909
    Abstract: One or more integrated circuit structures and techniques for forming such integrated circuit structures are provided. The integrated circuit structures comprise a conductive structure that is formed within a trench in a dielectric layer on a substrate. The conductive structure is formed over a barrier layer formed within the trench, or the conductive structure is formed over a liner formed over the barrier layer. At least some of the dielectric layer, the barrier layer, the liner and the conductive structure are removed, for example, by chemical mechanical polishing, such that a step height exists between a top surface of the substrate and a top surface of the dielectric layer. Removing these layers in this manner removes areas where undesired interlayer peeling is likely to occur. A conductive cap is formed on the conductive structure.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 8937011
    Abstract: Techniques disclosed herein may achieve crack free filling of structures. A flowable film may substantially fill gaps in a structure and extend over a base in an open area adjacent to the structure. The top surface of the flowable film in the open area may slope down and may be lower than top surfaces of the structure. A capping layer having compressive stress may be formed over the flowable film. The bottom surface of the capping layer in the open area adjacent to the structure is lower than the top surfaces of the lines and may be formed on the downward slope of the flowable film. The flowable film is cured after forming the capping layer, which increases tensile stress of the flowable film. The compressive stress of the capping layer counteracts the tensile stress of the flowable film, which may prevent a crack from forming in the base.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: January 20, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Hiroaki Iuchi, Hitomi Fujimoto, Chao Feng Yeh
  • Patent number: 8927413
    Abstract: A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric layer, a transitional layer formed on the first dielectric layer, and a conductive fill penetrated through the transitional layer and into the first dielectric layer; removing the transitional layer; and forming a second dielectric layer over the conductive fill and the first dielectric layer.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee
  • Patent number: 8921166
    Abstract: A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: December 30, 2014
    Assignee: Infineon Technologies AG
    Inventors: Sebastian Schmidt, Thomas Schafbauer, Hang Yip Liu, Yayi Wei
  • Patent number: 8912092
    Abstract: A method of forming a semiconductor device may include, but is not limited to, the following processes. A multi-layered structure is prepared over a semiconductor substrate. The multi-layered structure may include, but is not limited to, first and second patterns of a first insulating film, a second insulating film covering the first pattern of the first insulating film, and a first conductive film covering the second pattern of the first insulating film. The second insulating film and the first conductive film are polished under conditions that the first and second insulating films are greater in polishing rate than the first conductive film, to expose the first and second patterns of the first insulating film.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: December 16, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Kyoko Miyata
  • Publication number: 20140353845
    Abstract: A production method for a semiconductor device having a multi-level interconnection structure including a plurality of interconnection layers stacked one on another on a semiconductor substrate is provided. In the production method, the step of forming each of the interconnection layers of the multi-level interconnection structure includes an interconnection forming step of forming a real interconnection and a dummy interconnection, an insulative film forming step of forming an insulative film covering the real interconnection and the dummy interconnection, and a planarization step of planarizing a surface of the insulative film. The production method includes: a step of computing an in-plane distribution of an overall thickness of the multi-level interconnection structure to be expected when no dummy interconnection is formed; and a step of defining a dummy present zone and a dummy absent zone.
    Type: Application
    Filed: May 30, 2014
    Publication date: December 4, 2014
    Applicant: ROHM CO., LTD.
    Inventor: Takeshi MORITA
  • Patent number: 8900989
    Abstract: The present disclosure provides a method for forming a semiconductor device. The method includes forming first conductive layer structures in a first dielectric layer on a substrate; forming a patterned photoresist layer having portions that are each disposed over a respective one of the first conductive layer structures; forming an energy removable film (ERF) on the sidewalls of each of the portions; forming a second dielectric layer over the ERFs, the portions of the patterned photoresist layer, and the first dielectric layer; removing the portions to leave behind a plurality of openings; filling a conductive material in the openings, the conductive material defining second conductive layer structures; forming a ceiling layer over the second conductive layer structures, the ERFs, and the second dielectric layer; and applying energy to the ERFs to partially remove the ERFs on the sidewalls of the portions thereby forming air gaps.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee
  • Patent number: 8883631
    Abstract: One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the layer of insulating material, performing at least one etching process to define a cavity in the layer of insulating material, forming a layer of sacrificial material so as to overfill the cavity, performing at least one planarization process to remove a portion of the layer of sacrificial material and the patterned hard mask while leaving a remaining portion of the layer of sacrificial material within the cavity, and removing the remaining portion of the layer of sacrificial material positioned within the cavity.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: November 11, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kunaljeet Tanwar, Xunyuan Zhang, Xiuyu Cai
  • Patent number: 8865013
    Abstract: A method for chemical mechanical polishing of a substrate comprising tungsten using a nonselective chemical mechanical polishing composition.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: October 21, 2014
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Yi Guo, Jerry Lee, Raymond L. Lavoie, Jr., Guangyun Zhang
  • Patent number: 8859418
    Abstract: Disclosed herein are various methods of forming conductive structures, such as conductive lines and vias, using a dual metal hard mask integration technique. In one example, the method includes forming a first layer of insulating material, forming a first patterned metal hard mask layer above the first layer of insulating material, forming a second patterned metal hard mask layer above the first patterned metal hard mask layer, performing at least one etching process through both of the second patterned metal hard mask layer and the first patterned metal hard mask layer to define a trench in the first layer of insulating material and forming a conductive structure in the trench.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: October 14, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Torsten Huisinga, Jens Hahn, Kai Frohberg
  • Patent number: 8821750
    Abstract: The present invention relates to a metal polishing slurry containing abrasive grains, a metal-oxide-dissolving agent, and water, wherein the abrasive grains contain two or more abrasive grain species different from each other in average secondary particle diameter. Using the metal polishing slurry of the present invention, a metal polishing slurry can be obtained which gives a large polishing rate of an interlayer dielectric layer, and is high in the flatness of the polished surface. This metal polishing slurry can provide suitable method for a semiconductor device which is excellent in being made finer and thinner and in dimension precision and in electric characteristics, is high in reliability, and can attain a decrease in costs.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: September 2, 2014
    Assignee: Hitachi Chemical Co., Ltd.
    Inventors: Jin Amanokura, Takafumi Sakurada, Sou Anzai, Takashi Shinoda, Shigeru Nobe
  • Patent number: RE45507
    Abstract: An integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element has a geometric shape that exceeds prescribed integrated circuit manufacturing limits in at least one dimension. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. The non-conducting region includes a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: May 5, 2015
    Assignee: Broadcom Corporation
    Inventors: Harry Contopanagos, Christos Komninakis