Utilizing Etch-stop Layer Patents (Class 438/634)
  • Patent number: 10510759
    Abstract: A semiconductor memory device according to an example embodiment of the present inventive concept may include: a plurality of lower electrodes located on a substrate and spaced apart from one another; and an etch stop pattern located on the substrate and surrounding at least a part of each of the plurality of lower electrodes, in which the etch stop pattern includes: a first etch stop pattern including carbon; and a second etch stop pattern located on the first etch stop pattern and including a material different from a material of the first etch stop pattern.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 17, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hui-jung Kim, Bong-soo Kim, Sung-hee Han, Yoo-sang Hwang
  • Patent number: 10276431
    Abstract: A device comprises a semiconductor substrate; a dielectric layer deposited over the semiconductor substrate, the dielectric layer including a trench; and a structure in the trench. The structure includes a chemical vapor deposition (CVD) TaN layer formed on a side wall of the trench; a physical vapor deposition (PVD) Ta layer formed over the CVD TaN layer; and a metal-containing layer formed over the PVD Ta layer.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Lien Lee, Hung-Wen Su, Kuei-Pin Lee, Yu-Hung Lin, Yu-Min Chang
  • Patent number: 9966339
    Abstract: A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming an opening in the dielectric layer, forming a metal-containing layer overlying the opening in the dielectric layer, forming a conformal protective layer overlying the metal-containing layer, filling a conductive layer in the opening, and performing a thermal process to form a metal oxide layer barrier layer underlying the metal-containing layer.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Hung Lin, Ching-Fu Yeh, Yu-Min Chang, You-Hua Chou, Chih-Wei Chang, Sheng-Hsuan Lin
  • Patent number: 9947577
    Abstract: A method of forming an integrated circuit that includes providing a substrate, a metal layer over the substrate, and a first dielectric layer over the metal layer. The first dielectric layer includes a via. A sidewall layer that includes a silicon compound is in the via. A second dielectric layer is over the sidewall layer and an ultra-thick metal (UTM) layer is in the via.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Lu, Ching-Chen Hao
  • Patent number: 9812360
    Abstract: In interconnect fabrication (e.g. a damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect features in the holes. To prevent erosion/dishing of the conductive layer at the holes, the conductive layer is covered by a sacrificial layer (possibly conformal) before polishing; then both layers are polished. Initially, before polishing, the conductive layer and the sacrificial layer are recessed over the holes, but the sacrificial layer is polished at a lower rate to result in a protrusion of the conductive layer at a location of each hole. The polishing can continue to remove the protrusions and provide a planar surface.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: November 7, 2017
    Assignee: Tessera, Inc.
    Inventors: Cyprian Uzoh, Vage Oganesian, Ilyas Mohammed
  • Patent number: 9698100
    Abstract: The present disclosure provides a method of fabricating an integrated circuit in accordance with some embodiments. The method includes providing a substrate having a first conductive feature in a first dielectric material layer; selectively etching the first conductive feature, thereby forming a recessed trench on the first conductive feature; forming an etch stop layer on the first dielectric material layer, on the first conductive feature and sidewalls of the recessed trench; forming a second dielectric material layer on the etch stop layer; forming an opening in the second dielectric material layer; and forming a second conductive feature in the opening of the second dielectric material layer. The second conductive feature is electrically connected with the first conductive feature.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Tien-I Bao
  • Patent number: 9275888
    Abstract: Temporary substrates may include a bonding surface prepared for receiving an additional substrate that will transfer a thin layer. Such substrates may include a principal part or support and a surface layer thereon with the surface layer having a plurality of inserts therein. The inserts are made of a material having a coefficient of thermal expansion that is significantly different from that of the material constituting the surface layer. Processing methods for transferring a selected portion of an original substrate may involve such temporary substrates and productions methods may produce such temporary substrates.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: March 1, 2016
    Assignee: Soitec
    Inventor: Gregory Riou
  • Patent number: 9184297
    Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: November 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Toshinari Sasaki, Katsuaki Tochibayashi, Shunpei Yamazaki
  • Patent number: 9024439
    Abstract: Substrates and semiconductor chips are provided. The substrate or the semiconductor chip includes a body and a substantially pillar-shaped bump disposed on a first surface of the body. The pillar-shaped bump has a hole penetrating a portion thereof. Related semiconductor packages are also provided. Further, related methods are provided.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventors: In Chul Hwang, Il Hwan Cho, Ki Young Kim
  • Patent number: 8993435
    Abstract: In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor and a carbon-source gas including carbon as precursors. The carbon-source gas is free from carbon dioxide (CO2). The precursor is selected from the group consisting essentially of 1-methylsilane (1MS), 2-methylsilane (2MS), 3-methylsilane (3MS), 4-methylsilane (4MS), and combinations thereof.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Chen Wang, Po-Cheng Shih, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
  • Patent number: 8981422
    Abstract: To prevent contact plugs formed to sandwich an abutting portion between gate electrodes, from being short-circuited via a void formed inside an insulating film of the abutting portion. Over sidewalls SW facing each other in the abutting portion between gate electrodes G2 and G5, a liner insulating film 6 and an interlayer insulating film 7 are formed. Between the sidewalls SW, the liner insulating film 6 formed on each of the side walls of the sidewalls SW are brought in contact with each other to close a space between the sidewalls SW to prevent a void from being generated inside the interlayer insulating film 7 and the liner insulating film 6.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: March 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Masahiko Takeuchi
  • Patent number: 8937011
    Abstract: Techniques disclosed herein may achieve crack free filling of structures. A flowable film may substantially fill gaps in a structure and extend over a base in an open area adjacent to the structure. The top surface of the flowable film in the open area may slope down and may be lower than top surfaces of the structure. A capping layer having compressive stress may be formed over the flowable film. The bottom surface of the capping layer in the open area adjacent to the structure is lower than the top surfaces of the lines and may be formed on the downward slope of the flowable film. The flowable film is cured after forming the capping layer, which increases tensile stress of the flowable film. The compressive stress of the capping layer counteracts the tensile stress of the flowable film, which may prevent a crack from forming in the base.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: January 20, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Hiroaki Iuchi, Hitomi Fujimoto, Chao Feng Yeh
  • Publication number: 20140342549
    Abstract: A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.
    Type: Application
    Filed: August 1, 2014
    Publication date: November 20, 2014
    Inventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8846525
    Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Vishwanathan Rangarajan, George Andrew Antonelli, Ananda Banerji, Bart Van Schravendijk
  • Publication number: 20140252628
    Abstract: A method for forming a semiconductor interconnect structure comprises forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening therein. The opening is filled and the dielectric layer is covered with a metal layer having a first etch rate. The metal layer is thereafter planarized so that the metal layer is co-planar with the top of the dielectric layer. The metal layer is annealed to change the first etch rate into a second etch rate, the second etch rate being lower than the first etch rate. A copper-containing layer is formed over the annealed metal layer and the dielectric layer. The copper-containing layer has an etch rate greater than the second etch rate of the annealed metal layer. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the top of the annealed metal layer and does not etch thereunder.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Patent number: 8802561
    Abstract: Techniques disclosed herein prevent wire flaking (collapse). One aspect is an improved way of forming wires over trenches, which may be located in a hookup region of a 3D memory array, and may be used to form electrical connections between conductive lines in the memory array and drivers. The trenches are formed between CMP dummy structures. The trenches are partially filled with a flowable oxide film, which leaves a gap in the trench that is at least as wide as the total pitch of the wires to be formed. A capping layer is formed over the flowable film. After forming a conductive layer over the dielectric layer, the conductive layer is etched to form conductive wires. Some of the capping layer, as well as the CMP dummy structures may be removed. Thus, the conductive wires may be at least temporarily supported by lines of material formed from the capping layer.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: August 12, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Chao Feng Yeh, Hiroaki Iuchi, Hitomi Fujimoto, Hisayuki Nozawa
  • Patent number: 8803321
    Abstract: A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8791017
    Abstract: Disclosed herein are various methods of forming conductive structures, such as conductive lines and via, on an integrated circuit device using a spacer erosion technique. In one example, the method includes forming a patterned hard mask layer above a layer of insulating material, the patterned hard mask having a hard mask opening, forming an erodible spacer in the hard mask opening to thereby define a spacer opening and performing at least one etching process through the spacer opening on the layer of insulating material to define a trench therein for a conductive structure, wherein the erodible spacer is substantially eroded away during the at least one etching process.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: July 29, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Gunter Grasshoff
  • Publication number: 20140197470
    Abstract: A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.
    Type: Application
    Filed: March 18, 2014
    Publication date: July 17, 2014
    Inventors: Jaegoo Lee, Youngwoo Park
  • Patent number: 8772154
    Abstract: Embodiments of a method for fabricating integrated circuits are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes the steps of depositing an interlayer dielectric (“ILD”) layer over a semiconductor device, depositing a barrier polish stop layer over the ILD layer, and patterning at least the barrier polish stop layer and the ILD layer to create a plurality of etch features therein. Copper is plated over the barrier polish stop layer and into the plurality of etch features to produce a copper overburden overlying the barrier polish stop layer and a plurality of conductive interconnect features in the ILD layer and barrier polish stop layer. The integrated circuit is polished to remove the copper overburden and expose the barrier polish stop layer.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: July 8, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Egon Ronny Pfützner, Carsten Peters, Jens Heinrich
  • Patent number: 8766445
    Abstract: A semiconductor device includes: a semiconductor substrate; an underlying wiring on the semiconductor substrate; a resin film extending to the semiconductor substrate and the underlying wiring, and having a first opening on the underlying wiring; a first SiN film on the underlying wiring and the resin film, and having a second opening in the first opening; an upper layer wiring on the underlying wiring and part of the resin film; and a second SiN film on the upper layer wiring and the resin film, and joined to the first SiN film on the resin film. The upper layer wiring includes a Ti film, connected to the underlying wiring via the first and second openings, and an Au film on the Ti film. The first and second SiN films circumferentially protect the Ti film.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: July 1, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takayuki Hisaka, Takahiro Nakamoto, Toshihiko Shiga, Koichiro Nishizawa
  • Patent number: 8765511
    Abstract: A method for manufacturing a semiconductor device including at least one of the following steps: (1) Forming a lower electrode pattern on/over a substrate. (2) Forming a first interlayer insulating layer on the lower electrode pattern. (3) Forming an upper electrode pattern on the first interlayer insulating layer. (4) Forming a passivation layer on a side of the upper electrode pattern. (5) Forming a second interlayer insulating layer on the upper electrode pattern. (6) Etching the second interlayer insulating layer to form a cavity which exposes the passivation layer. (7) Forming a contact ball in the cavity.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 1, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Chung Kyung Jung, Sung Wook Joo
  • Patent number: 8753974
    Abstract: Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brian Griffin, Russ Benson
  • Patent number: 8753977
    Abstract: A method for manufacturing a semiconductor device includes dry etching an interlayer insulating layer provided on a foundation layer by using a mask having a plurality of first openings and a plurality of second openings arranged more closely than the first openings to form simultaneously a first hole reaching the foundation layer under each of the first openings and a second hole reaching the foundation layer under the second openings. The first hole reaches the foundation layer without contacting any other first holes. After starting of the dry etching, a plurality of holes are formed under each of the plurality of second openings, and with the progress of the dry etching, the plurality of holes are connected with each other at least at their upper parts including their open ends to form the second hole having an opening area larger than an opening area of the first hole.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenichi Ide
  • Patent number: 8748314
    Abstract: There is provided a method of manufacturing a semiconductor device, which includes forming a TiN film as a hard mask directly on a second p-SiCOH film formed on a substrate, forming an opening passing through the TiN film and the second p-SiCOH film by photolithography and etching, cleaning the inside of the opening, removing the TiN film after cleaning the inside, and forming a second metal film filling the opening directly on the second p-SiCOH film after removing the TiN film.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuya Usami
  • Patent number: 8741768
    Abstract: A method is provided that includes forming conductive or semiconductive features above a first dielectric material, depositing a second dielectric material above the conductive or semiconductive features, etching a void in the second dielectric material, wherein the etch stops on the first dielectric material, and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: June 3, 2014
    Assignee: SanDisk 3D LLC
    Inventor: Christopher J. Petti
  • Patent number: 8741770
    Abstract: Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: June 3, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Robert Seidel, Juergen Boemmels, Thomas Foltyn
  • Patent number: 8735299
    Abstract: There is provided a semiconductor device manufacturing method for forming a step-shaped structure in a substrate by etching the substrate having thereon a multilayer film and a photoresist film on the multilayer film and serving as an etching mask. The multilayer film is formed by alternately layering a first film having a first permittivity and a second film having a second permittivity different from the first permittivity. The method includes a first process for plasma-etching the first film by using the photoresist film as a mask; a second process for exposing the photoresist film to hydrogen-containing plasma; a third process for trimming the photoresist film; and a fourth process for etching the second film by using the trimmed photoresist film and the plasma-etched first film as a mask. The step-shaped structure is formed in the multilayer film by repeatedly performing the first process to the fourth process in this sequence.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: May 27, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Seiichi Watanabe, Manabu Sato, Kazuki Narishige, Takanori Sato, Takayuki Katsunuma
  • Patent number: 8728932
    Abstract: A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such structures.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8691610
    Abstract: A method of manufacturing a semiconductor device including at least one of the following steps: (1) Forming a plurality of lower electrodes over a substrate. (2) Forming a first stop film over the lower electrodes. (3) Forming a filling layer over the first stop film. (4) Forming a second stop film over the filling layer. (5) Forming a first interlayer insulating layer over the second stop film. (6) Forming a plurality of upper electrodes over the first interlayer insulating layer. (7) Forming a second interlayer insulating layer over the upper electrodes. (8) Etching the second interlayer insulating layer and the first interlayer insulating layer to form a cavity. (9) Forming a contact ball in the cavity.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 8, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Seong Hun Jeong, Ki Jun Yun, Oh Jin Jung
  • Patent number: 8691686
    Abstract: A method of manufacturing a semiconductor device, includes: forming a first circuit substrate having a first interconnection; forming a second circuit substrate having a second interconnection; bonding the first circuit substrate to the top surface of the second circuit substrate so as to be stacked facing each other; and performing an etching process of simultaneously removing parts formed on the first interconnection and the second interconnection in a stacked body of the first circuit substrate and the second circuit substrate so as to form a first opening in the top surface of the first interconnection and to form a second opening in the top surface of the second interconnection. The forming of the first circuit substrate includes forming an etching stopper layer on the surface of the first interconnection out of a material having an etching rate lower than that of the first interconnection in the etching process.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: April 8, 2014
    Assignee: Sony Corporation
    Inventor: Ikue Mitsuhashi
  • Patent number: 8685852
    Abstract: A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: April 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin Gu Kim
  • Patent number: 8673749
    Abstract: In a semiconductor device manufacturing method, an insulating layer is formed on a front surface of a semiconductor substrate. Trenches are formed in the substrate by using the insulating layer as a mask so that a first portion of the insulating layer is located on the front surface between the trenches and that a second portion of the insulating layer is located on the front surface at a position other than between the trenches. The entire first portion is removed, and the second portion around an opening of each trench is removed. The trenches are filled with an epitaxial layer by epitaxially growing the epitaxial layer over the front surface side. The front surface side is polished by using the remaining second portion as a polishing stopper.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: March 18, 2014
    Assignee: DENSO CORPORATION
    Inventors: Kouji Eguchi, Youhei Oda, Shinichi Adachi
  • Publication number: 20140065813
    Abstract: A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.
    Type: Application
    Filed: November 1, 2013
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8664111
    Abstract: There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 4, 2014
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Ha-Jin Lim, Moon-Han Park, Eun-Gon Kim, Jin-Ho Do, Weon-Hong Kim, Moon-Kyun Song, Dae-Kwon Joo
  • Patent number: 8658531
    Abstract: The present invention provides a method of forming connection holes. The method utilizes two different gases to perform two etching processes for the interlayer dielectric layer so as to form connection holes. The etching rate of the interlayer dielectric layer in the first etching process using the first etching gas is proportional to the size of the openings which defines the connection hole while the etching rate of the interlayer dielectric layer in the second etching process using the second etching gas is inversely related with size of the openings. According to the present invention, the first etching gas and the second etching gas compensate for each other to eliminate the loading effect, thus the connection holes are formed with almost the same depth. Therefore the damage of the etching stopper layer due to the high etching rate in the larger connection holes can be avoided, which prevents the excessive variation of the connecting resistance and expands the process window.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: February 25, 2014
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Yushu Yang, Cheng Li, Yuwen Chen
  • Patent number: 8617979
    Abstract: According to one embodiment, a method can include dry etching an interlayer insulating layer provided on a foundation layer by using a mask having a plurality of first openings and a plurality of second openings arranged more closely than the first openings to form simultaneously a first hole reaching the foundation layer under each of the first openings and a second hole reaching the foundation layer under the second openings. The first hole reaches the foundation layer without contacting any other first holes. After starting of the dry etching, a plurality of holes are formed under each of the plurality of second openings, and with the progress of the dry etching, the plurality of holes are connected with each other at least at their upper parts including their open ends to form the second hole having an opening area larger than an opening area of the first hole.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: December 31, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenichi Ide
  • Patent number: 8617981
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: December 31, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Patent number: 8557613
    Abstract: A method for designing, fabricating, and predicting a desired structure in and/or on a host material through defining etch masks and etching the host material is provided. The desired structure can be micro- or nanoscale structures, such as suspended nanowires and corresponding supporting pillars, and can be defined one layer at a time. Arbitrary desired structures can also be defined and obtained through etching. Further, given the desired structure, a starting structure can be predicted where etching of the starting structure yields the desired structure.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: October 15, 2013
    Assignee: California Institute of Technology
    Inventors: Michael Shearn, Michael David Henry, Axel Scherer
  • Patent number: 8557612
    Abstract: A method to determine minimum etch mask dosage or thickness as a function of etch depth or maximum etch depth as a function of etch mask implantation dosage or thickness, for fabricating structures in or on a substrate through etch masking via addition or removal of a masking material and subsequent etching.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: October 15, 2013
    Assignee: California Institute of Technology
    Inventors: Michael David Henry, Michael Shearn, Axel Scherer
  • Patent number: 8497204
    Abstract: In a first aspect, a method is provided that includes: forming a plurality of conductive or semiconductive features above a first dielectric material; depositing a second dielectric material above the conductive or semiconductive features; etching a void in the second dielectric material, wherein the etch is selective between the first and the second dielectric material and the etch stops on the first dielectric material; and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: July 30, 2013
    Assignee: SanDisk 3D LLC
    Inventor: Christopher J. Petti
  • Patent number: 8492194
    Abstract: A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a dielectric layer on the bottom electrode, and forming a sacrificial layer on the dielectric layer. The method further includes selectively etching portions of the sacrificial layer and the dielectric layer to define a pore extending through the sacrificial layer and the dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Breitwisch, Chung H. Lam
  • Patent number: 8471353
    Abstract: A mesa photodiode which includes a mesa, the side wall of the mesa (a light-receiving region mesa) and at least a shoulder portion of the mesa in an upper face of the mesa are continuously covered with a semiconductor layer of a first conductivity type, a second conductivity type, a semi-insulating type, or an undoped type (an undoped InP layer, for example) that is grown on the side wall and the upper face of the mesa. In the semiconductor layer, a layer thickness D1 of a portion covering the side wall of the mesa is equal to or greater than 850 nm.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: June 25, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoaki Koi, Isao Watanabe, Takashi Matsumoto
  • Patent number: 8461049
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a first cap layer on a surface of the substrate and sidewall of the gate structure; forming a second cap layer on the first cap layer; forming a third cap layer on the second cap layer; performing an etching process to partially remove the third cap layer, the second cap layer, and the first cap layer to form a first spacer and a second spacer on the sidewall of the gate structure; and forming a contact etch stop layer (CESL) on the substrate to cover the second spacer, wherein the third cap layer and the CESL comprise same deposition condition.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: June 11, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chu-Chun Chang, Chun-Mao Chiou, Chiu-Te Lee
  • Patent number: 8455350
    Abstract: A method for manufacturing an integrated circuit system that includes: forming a substrate with an active region; depositing a material over the substrate to act as an etch stop and define a source and a drain; depositing a first dielectric over the substrate; processing the first dielectric to form features within the first dielectric including a shield; and depositing fill within the features to electrically connect the shield to the source of the active region by a single process step.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: June 4, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Xavier Seah Teo Leng
  • Patent number: 8445382
    Abstract: A dual damascene process for forming conductive interconnects on an integrated circuit die. The process includes providing a layer (16) of porous, ultra low-k (ULK) dielectric material in which a via opening (30) is subsequently formed. A thermally degradable polymeric (“porogen”) material (42) is applied to the side wall sidewalls of the opening (30) such that the porogen material penetrates deeply into the porous ULK dielectric material (thereby sealing the pores and increasing the density thereof). Once a conductive material (36) has been provided with the opening (30) and polished back by means of chemical mechanical polishing (CMP), the complete structure is subjected to a curing step to cause the porogen material (44) with the ULK dielectric layer (16) to decompose and evaporate, thereby restoring the porosity (and low-k value) of the dielectric layer (16). Attached are a marked-up copy of the originally filed specification and a clean substitute specification in accordance with 37 C.F.R. §§1.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: May 21, 2013
    Assignee: NXP B.V.
    Inventor: Willem Frederik Adrianus Besling
  • Patent number: 8431480
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 30, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwaskai, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Patent number: 8420947
    Abstract: A method of manufacturing an integrated circuit system includes: providing a etch stop layer; forming a layer stack over the etch stop layer with the layer stack having an anti-reflective coating layer over a low temperature oxide layer; forming a photoresist layer over the anti-reflective coating layer; forming a first resist line and a second resist line from the photoresist layer with the first resist line and the second resist line separated by a through line pitch on the anti-reflective coating layer; etching the anti-reflective coating layer using a low-pressure polymer burst with a non-oxidizing gas mixture to remove a portion of the anti-reflective coating layer; and forming a first polymer layer over the first resist line.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: April 16, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Ravi Prakash Srivastava
  • Patent number: 8389358
    Abstract: A non-volatile memory structure includes a substrate; a poly gate structure formed on the substrate; a contact etching stop layer formed over the poly gate structure and including at least a silicon nitride layer and a first silicon oxide layer overlying the silicon nitride layer; and an inter-layer dielectric layer formed on the first silicon oxide layer. The first silicon oxide layer has a density higher than that of the inter-layer dielectric layer.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: March 5, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Hung-Lin Shih, Chih-Ta Chen
  • Patent number: 8330275
    Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang