Abstract: An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.

Abstract: A polymer spacer material may increase the dimensions of the patterned photoresist that is used as a mask to etch the layers below the photoresist, which in turn translates into smaller dimensions etched into the underlying materials. This allows for the formation of integrated circuits having smaller features, smaller overall size, and greater density of features. In particular, the use of a polymer spacer material allows for the formation of contacts within flash memory cells having decreased dimensions so that higher density flash memory cells may be created without causing shorts between contacts or shorts due to misalignment of the contacts. Additionally, the use of the polymer spacer material extends the use of photolithography technologies that are used to form the patterns into the photoresists.

Abstract: Methods are provided for processing a substrate for depositing an adhesion layer between a conductive material and a dielectric layer. In one aspect, the invention provides a method for processing a substrate including positioning a substrate having a conductive material disposed thereon, introducing a reducing compound or a silicon based compound, exposing the conductive material to the reducing compound or the silicon based compound, and depositing a silicon carbide layer without breaking vacuum.

Abstract: The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a barrier layer deposited on the under-layer, and a conductive layer deposited in the feature, placing the wafer in an electrolyte, such that at least the barrier layer is immersed in the electrolyte, and applying an electrical potential between the electrode and the wafer.

Abstract: Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cavity and to expose a conductive feature in an existing interconnect structure, wherein etching the portion of the dielectric layer and etching the exposed portion of the etch-stop layer are performed concurrently with substantially no intervening processing steps therebetween.

Abstract: A method for forming a metallic interconnect in a semiconductor device is disclosed. An example method forms an IDL on a substrate including predetermined devices, forms a via hole in the IDL, depositing a first metal diffusion preventive layer and a metal layer to form a via plug on the IDL, and performs a planarization process using the first metal diffusion preventive layer using as an etching stop layer. In addition, the example method forms a metallic interconnect on the first metal diffusion preventive layer, deposits the other metal diffusion preventive layer on the metallic interconnect, and etches a predetermined part of first and second metal diffusion preventive layers and the metallic interconnect using a mask pattern.

Abstract: A method of fabricating dual damascene interconnections is provided. A dual damascene region is formed in a hybrid dielectric layer having a dielectric constant of 3.3 or less, and a carbon-free inorganic material is used as a via filler. The present invention improves electrical properties of dual damascene interconnections and minimizes defects.

Abstract: An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic low-k material layer, the stress redistribution layer, and the second organic low-k dielectric layer. The opening is then filled with a conductive material to form an interconnection structure. The stress redistribution layer has a heat expansion coefficient closer to that of the substrate, while such heat expansion coefficient differs more significantly from those of the first and second organic low-k material layers.

Abstract: A polymer dielectric material includes a sidewall passivating layer on the opposing sidewall surfaces of an opening in the dielectric layer for a via or trench. The sidewall passivating layer may be deposited on the sidewall surfaces, as well as the bottom surface of an opening having a first depth in the polymer dielectric layer. After the sidewall passivating layer is added, the depth of the opening may be increased to a second depth. The sidewall passivating layer provides a barrier to removal of the polymer dielectric from the sidewalls, preventing or reducing undercutting below a hard mask.

Abstract: An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

Abstract: A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.

Abstract: Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step is formed in the etch-stop layer by removing portions of the exposed etch-stop layer. And, the step is formed at a boundary between a recessed portion of the exposed etch-stop layer and a raised portion of the etch-stop layer covered with the interlayer dielectric layer. Portions of the interlayer dielectric layer are removed to expose portions of the raised portion of the etch-stop layer. And, the exposed recessed and raised portions are anisotropically etched to expose the lower conductive layer and to form the interconnection hole having the slopes, wherein the slopes are made of a residual etch-stop layer at the lower sides of the interconnection hole.

Abstract: A process for forming a void-free dielectric layer is disclosed in which adjoining gate film stacks are formed on a semiconductor substrate. Each gate film stack includes a silicide layer and a hard mask that overlies the silicide layer. A first selective etch is performed so as to reduce the width of the hard mask on each of the gate film stacks, exposing portions of the top surface of the silicide layer. A second selective etch is then performed to reduce the width of the silicide layer. Spacers are then formed on opposite sides of each of the gate film stacks, and a dielectric film is formed that extends over the gate film stacks. By reducing the width of the hard mask layer and the silicide layer, gate film stacks are obtained that have reduced width near the top of each gate film stack, preventing voids from forming in the dielectric film.

Abstract: Various methods are provided for forming metal interconnection layers of semiconductor devices.

Abstract: A chemical mechanical polishing stopper film comprising at least one organic polymer, said film having a dielectric constant of 4 or lower, and a chemical mechanical polishing method. The chemical mechanical polishing method comprises forming a chemical mechanical polishing stopper film comprising at least one organic polymer on an insulating film so that the stopper film is interposed between the insulating film and a metal film to be removed by chemical mechanical polishing, and then removing the metal film with a chemical mechanical polishing slurry.

Abstract: Methods are provided for depositing an oxygen-doped dielectric layer. The oxygen-doped dielectric layer may be used for a barrier layer or a hardmask. In one aspect, a method is provided for processing a substrate including positioning the substrate in a processing chamber, introducing a processing gas comprising an oxygen-containing organosilicon compound, carbon dioxide, or combinations thereof, and an oxygen-free organosilicon compound to the processing chamber, and reacting the processing gas to deposit an oxygen-doped dielectric material on the substrate, wherein the dielectric material has an oxygen content of about 15 atomic percent or less. The oxygen-doped dielectric material may be used as a barrier layer in damascene or dual damascene applications.

Abstract: A method for avoiding resist poisoning during a damascene process is disclosed. A semiconductor substrate is provided with a low-k dielectric layer (k?2.9) thereon, a SiC layer over the low-k dielectric layer, and a blocking layer over the SiC layer. The blocking layer is used to prevent unpolymerized precursors diffused out from the low-k dielectric layer from contacting an overlying resist. A bottom anti-reflection coating (BARC) layer is formed on the blocking layer. A resist layer is formed on the BARC layer, the resist layer having an opening to expose a portion of the BARC layer. A damascene structure is formed in the low-k dielectric layer by etching the BARC layer, the blocking layer, the SiC layer, and the low-k dielectric layer through the opening.

Abstract: A semiconductor device having a contact hole capable of maintaining contact resistance of a contact connecting multi-layered interconnections with each other and a method for manufacturing the same are provided. An interconnection layer, a capping layer, and an etching stopper are sequentially formed on a semiconductor substrate. An interlayer insulating layer is deposited over the resulting structure. The etching stopper is formed of a material having a high etching selectivity with respect to the interlayer insulating layer. Then a first contact hole is formed to expose the surface of the etching stopper by etching a predetermined portion of the interlayer insulating layer. Either the etching stopper exposed by the first contact hole or the etching stopper exposed by the first contact hole and part of the capping layer are etched to form a second contact hole.

Abstract: A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of: forming a thin nitride insulating layer on a gate structure and a diffusion region of the transistor; forming a first insulating layer, which is then planarized to expose the nitride insulating layer on the gate structure; etching through the first insulating layer to form a first part of a contact hole; forming a first part of a contact in said first part of the contact hole; forming a second insulating layer; etching through the second insulating layer to form a second part of the contact hole; and forming a second part of the contact in the second part of the contact hole. The two-stage etching process for forming a conductive contact effectively prevents over-etching and short-circuiting between a wordline and a bitline.

Abstract: A pixel cell is formed by locating a first passivation layer over the final layer of metal lines. Subsequently, the uneven, non-uniform passivation layer is subjected to a planarization process such as chemical mechanical polishing, mechanical abrasion, or etching. A spin-on-glass layer may be deposited over the non-uniform passivation layer prior to planarization. Once a uniform, flat first passivation layer is achieved over the final metal, a second passivation layer, a color filter array, or a lens forming layer with uniform thickness is formed over the first passivation layer. The passivation layers can be oxide, nitride, a combination of oxide and nitride, or other suitable materials. The color filter array layer may also undergo a planarization process prior to formation of the lens forming layer. The present invention is also applicable to other devices.

Abstract: An interlayer insulation film for multilayer interconnect of a semiconductor integrated circuit is formed by forming a first insulation film on a substrate by plasma CVD using a silicon-containing hydrocarbon gas; and continuously forming a second insulation film on the first insulation film at a thickness less than the first insulation film in situ by plasma CVD using a silicon-containing hydrocarbon gas and an oxidizing gas. The second insulation film has a hardness of 6 GPa or higher and is used as a polishing stop layer.

Abstract: A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method includes the steps of forming a first insulating layer that includes a nitride along a profile of a gate structure and a junction region, forming a temporary layer that has a doped oxide on the first insulting layer, removing a portion of the temporary layer by performing a selective etch of the oxide with a mask while leaving a plug portion of the temporary layer over the junction region, forming a second insulting layer that has an undoped oxide in a region where the portion of the temporary layer is removed, removing the plug portion by performing a selective etch of the undoped oxide to form a contact hole, removing a portion of the first insulating layer at a bottom of the contact hole, and forming a conductive contact ins the contact hole.

Abstract: A via hole is first formed, and an embedded material is embedded in the via hole. A height of the embedded material is adjusted so that a surface thereof is between an upper surface of an SiOC film and that of an SiC film. After this, an SiN film, a TEOS film, and the SiOC film are etched by using a resist mask as a mask. However, etching of the SiOC film is stopped when a bottom of a trench formed in the SiOC film is lower than an upper surface of the embedded material and higher than that of the SiC film. Then, the resist mask and the embedded material are removed. The SiOC film is etched again by using the SiN film as a mask, and the SiN film and an exposed part of the SiC film are removed.

Abstract: In a method of forming a metal wiring line, a first insulating film is formed directly or indirectly on a semiconductor substrate. A second insulating film is formed on the first insulating film. A wiring line groove is formed to pass through the second insulating film to an inside of the first insulating film. A conductive film is formed to fill the wiring line groove and to cover the second insulating film. The conductive film and the second insulating film are removed by a first CMP polishing process, using the first insulating film as a stopper film, until the first insulating film is exposed.

Abstract: An electrical interconnection for a highly integrated semiconductor device includes a first insulation layer having at least a first recessed portion on a substrate. The first recessed portion is filled with metal to form a first metal pattern. A diffusion barrier layer including aluminum oxide of high light transmittance is provided on the first insulation layer and the first metal pattern for preventing metal from diffusing. An insulating interlayer including a second recessed portion for exposing an upper surface of the first metal pattern is provided on the diffusion barrier layer. The second recessed portion is filled with metal to form a second metal pattern. The electrical interconnection may be used with an image sensor. The metal may be copper. High light transmittance of the diffusion barrier layer ensures external light reaches the photodetector. The aluminum oxide of the diffusion barrier layer reduces parasitic capacitance of the electrical interconnections.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate on which cell strings are formed and in which a plurality of conductive regions are formed; sequentially forming a first interlayer insulation film and a first etch barrier film on the semiconductor substrate; forming a plurality of contact holes by exposing the plurality of conductive regions formed in the semiconductor substrate, wherein an impurity concentration of the conductive regions is reduced due to the process for forming the contact holes; filling a metal material in the contact holes and forming a plurality of contact plugs; sequentially forming a second interlayer insulation film, a second etch barrier film and a third interlayer insulation film over a resulting structure including the contact plugs; forming a plurality of metal line patterns, wherein the metal line patterns pass through the third interlayer insulation film, the second etch barrier film a

Abstract: The present invention relates to a method of forming damascene pattern in a semiconductor device, and the method includes forming an insulating layer on a bottom wiring, forming via holes exposing a part of the bottom wiring by removing the insulating layer selectively, filling insides of the via holes to a prescribed thickness, forming an anti-reflection layer on the via holes and the insulating layer, forming a mask pattern for trench etching on the insulating layer on which the anti-reflection layer is formed, and forming a damascene pattern using the mask pattern for trench etching. CD uniformity is improved by minimizing change of the critical dimension of the damascene pattern, thereby increasing reliability of the semiconductor device.

Abstract: A heat treatment is performed to an insulating film composition, formed on a semiconductor substrate, at a temperature of 350° C. in an inert gas ambient to form a non-porous insulating film. Next, dry etching is performed using a resist pattern as a mask to form a trench in the non-porous insulating film, ashing is performed to remove the resist pattern, and the surface of the semiconductor substrate is cleaned. Thereafter, a second heat treatment is performed for the non-porous insulating film to form a porous insulating film. Since the second heat treatment is performed in an oxidizing-gas atmosphere, the pore-generating material can be removed at a temperature lower than the temperature of conventional methods to form an insulating film having a low dielectric constant.

Abstract: A method of forming copper interconnects for an integrated circuit is provided. An antireflective coating layer is formed over an insulating layer formed over a semiconductor substrate. An interconnect pattern is patterned and etched into said insulating layer. A diffusion barrier layer is then conformally deposited in a deposition chamber along the etched interconnect pattern, wherein the antireflective coating is removed in said chamber before deposition of the barrier layer. Copper interconnects are then formed in the interconnect pattern etched in the insulating layer.

Abstract: A method for forming a wire line by a damascene process includes forming a first insulating layer on a semiconductor substrate, etching the first insulating layer to form a contact hole, and forming a first conductive layer over the first insulating layer that fills the contact hole. The first conductive layer is patterned, and a storage node contact is formed that fills the contact hole and is electrically connected to the semiconductor substrate. A hard mask is formed over the storage node contact and the first insulating layer is etched using the hard mask as an etch mask to form a trench in the first insulating layer. A bit line is formed in the trench that is electrically connected to the semiconductor substrate. A second insulating layer is formed that covers the bit line. The second insulating layer and the hard mask are planarized and a storage node of a capacitor is formed on the storage node contact.

Abstract: The present invention provides a method for fabricating a semiconductor device capable of decreasing a parasitic capacitance to thereby increase a cell capacitance. To achieve this effect, the deposited third inter-layer insulation layer is planarized and is subjected to a wet etching process to make its height lower than that of the bit line. Afterwards, the nitride-based etch stop layer is formed on the etched third inter-layer insulation layer, and then, the contact hole for forming the storage node contact plug is formed in between the bit lines through the SAC process so that the etch stop layer does not remain at sidewalls of the bit line. From this structure, it is possible to decrease the parasitic capacitance, and this decrease further provides an effect of increasing the cell capacitance.

Abstract: In a manufacture of a semiconductor device, spacers are formed on sidewalls of structures including conductive patterns and insulation patterns. The insulation patterns are at least four times thinner than the conductive patterns. After gaps between the structures are filled with a first insulation film, etch stop film patterns having a width which is wider than that of the structures are formed on the structures. A second insulation film is formed to cover the resultant structures without voids between the structures.

Abstract: Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions between the gate patterns include first spaces having a first width and second spaces having a second width greater than the first width. Spacers are formed on sidewalls of the second spaces, and spacer layer patterns filling the first spaces are also formed together with the spacers. The spacers are selectively removed to expose the sidewalls of the first spaces. As a result, the semiconductor integrated circuit includes wide spaces enlarged by the removal of the spacers and narrow and deep spaces filled with the spacer layer patterns.

Abstract: A process of removing excess conductive material from the exposed surface of a dielectric layer, the process comprising the steps of forming a shield layer on the dielectric layer, forming a sacrificial layer on top of the shield layer, depositing the conductive material on top of the sacrificial layer so that the conductive material is positioned within cavities in the dielectric material, and then using chemical mechanical planarization to remove the excess conductive material and the sacrificial layer. The use of a sacrificial layer interposed between the shield layer and the excess conductive material allows for chemical mechanical planarization to fully remove the sacrificial layer to facilitate more uniform removal of excess conductive material.

Abstract: An apparatus including a contact point formed on a device layer of a circuit substrate or an interconnect layer on the substrate; a first dielectric material; and a different second polymerizable dielectric material on the substrate and separated from the device layer or the interconnect layer by the first dielectric material following polymerization, the second dielectric material comprising a glass transition temperature of at least 250° C. and a thermal decomposition temperature of at least 400° C. A method including depositing a dielectric material and thermally treating the dielectric material at a temperature greater than the thermal decomposition temperature.

Abstract: A method for forming a metal interconnection layer of a semiconductor device comprises forming a film including a material selective to a medium used in an ashing process on an interlayer insulating film. The method comprises transforming the film during the ashing process to form an interconnection pattern having a dual damascene structure. A dielectric material such as copper is deposited on the interconnection pattern, which is planarized through CMP, thereby forming a via contact having a single damascene structure without a recess therein.

Abstract: Disclosed in a method of forming a metal line in a semiconductor device. The method includes the steps of sequentially forming a first etch stop film, a second interlayer insulating film and a BARC film on a first interlayer insulating film into which a metal line is buried, forming a photoresist pattern defining a trench in a given region of the BARC film, performing an etch process up to the second interlayer insulating film using the photoresist pattern as an etch mask to form a trench, removing the photoresist pattern and the BARC film by means of a first wet etch process, etching the first etch stop film by means of a second wet etch process using the second interlayer insulating film an as etch mask, and cleaning the resulting entire surface by means of a third wet etch process.

Abstract: A low-k dielectric for use as an interlayer for an interconnect structure is provided. The dielectric of the present invention is an alkaline boron silicate glass which when formulated in certain compositional ranges can undergo spinodal decomposition when processed using certain thermal profiles. Spinodal decomposition is a chemical and physical separation of the silicate glass into a distinct interpenetrating microstructure which contains a substantially pure silicon dioxide network and a boron-rich network. The dimension (i.e., scale), and the amount of separation can be controlled through compositional and thermal control during the processing of the silicate glass.

Abstract: A method for forming a dual damascene interconnect structure provides an intermetal dielectric that includes a spin-on low-k dielectric material formed over a CVD low-k dielectric material. A via opening is formed by etching through the spin-on low-k dielectric material and the CVD low-k dielectric material and a plug material is introduced to fill the via opening. A highly selective trench etching operation etches a trench in the upper, spin-on low-k dielectric material and removes the plug material from the via without attacking the lower CVD low-k dielectric material to form the dual damascene opening which is then filled with a conductive interconnect material. The intermetal dielectric formed of multiple low-k dielectric layers provides advantageous electrical and mechanical properties.

Abstract: A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces.

Abstract: A structure applied to a photolithographic process is provided. The structure comprises at least a film layer, an optical isolation layer, an anti-reflection coating and a photoresist layer sequentially formed over a substrate. In the photolithographic process, the optical isolation layer stops light from penetrating down to the film layer. Since the optical isolation layer is set up underneath the photoresist layer, light emitted from a light source during photo-exposure is prevented from reflecting from the substrate surface after passing through the film layer. Thus, the critical dimensions of the photolithographic process are unaffected by any change in the thickness of the film layer.

Abstract: An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

Abstract: A process for defining a dual damascene opening in a stack of insulator layers to expose a portion of a top surface of an underlying conductive structure, has been developed. The process features a two step procedure for removal of insulator stop layers, wherein the stop layers are employed to allow selective dry etch procedures to be used for definition of both the via opening component and the trench shape component of the dual damascene opening. After definition of the via opening, terminating at the top surface of an underlying, first silicon nitride stop layer, a photoresist shape is used as an etch mask to allow a dry etch procedure to define a trench shape in a top portion of an insulator stack, with the dry etch procedure terminating at the top surface of an overlying second silicon nitride stop layer. The dry etch procedure also results in formation of a photoresist plug in the via hole, located on an underlying, first silicon nitride stop layer.

Abstract: Method and structure for integrating conductive and dielectric materials in a microelectronic structure having air gaps are disclosed. Certain embodiments of the invention comprise isolating dielectric layers from conductive layers using an etch stop layer to facilitate controlled removal of portions of the dielectric layers and formation of air gaps or voids. Capping and peripheral structural layers may be incorporated to increase the structural integrity of the integration subsequent to removal of sacrificial material.

Abstract: A method of making a semiconductor structure comprises forming a hole through a first dielectric layer; followed by forming a hole through an etch-stop layer, to expose a first conducting layer. The thickness of the etch-stop layer is at least one-half the smallest line width of the first conducting layer.

Abstract: A method for fabricating dielectric barrier layers in integrated circuit structures such as damascene structures is provided. In one embodiment, a low-k dielectric layer formed on a substrate is provided. The low-k dielectric layer has at least one opening exposing an underlying metal layer. A first silicon carbide barrier layer is formed to conformally cover the exposed surfaces of the opening. A portion of the first silicon carbide barrier layer above the low-k dielectric layer and over the bottom of the opening is converted with an oxidation treatment into a layer of silicon oxide. The silicon oxide layer is removed above the low-k dielectric layer and from the bottom of the opening. The opening is filled with a conductive layer in electrical contact with the underlying metal layer. The conductive layer is removed above the low-k dielectric layer to a predetermined depth below the low-k dielectric layer to define a recess therebelow.

Abstract: A structure for magnetically shielded transmission lines for use with high speed integrated circuits having an improved signal to noise ratio, and a method for forming the same are disclosed. At least one magnetic shield structure formed by atomic layer deposition (ALD) contains electrically induced magnetic fields generated around a number of transmission lines. The shield material is made of alternating layers of magnetic material and insulating material.

Abstract: The present invention provides a method for forming a low-k dielectric structure on a substrate 10 that includes depositing, upon the substrate, a dielectric layer 12. A multi-film cap layer 18 is deposited upon the dielectric layer. The multi-film cap layer includes first 181 and second 182 films, with the second film being disposed between the dielectric layer and the first film. The first film typically has a removal rate associated therewith that is less than the removal rate associated with the second film. A deposition layer 20 is deposited upon the multi-film cap layer and subsequently removed. The properties of the multi-film cap layer are selected so as to prevent the dielectric layer from being exposed/removed during removal of the deposition film. In this manner, a deposition layer, having variable rates of removal, such as copper, may be planarized without damaging the underlying dielectric layer.

Abstract: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

Abstract: A capacitor in a semiconductor device having a dual dielectric film structure and a fabrication method therefor are disclosed. The capacitor comprises: a lower electrode formed on a semiconductor substrate, a dielectric film of a dual dielectric film structure composed of an Si3N4 chloride-free thin film and a Ta2O5 thin film, which is formed on the lower electrode, and an upper electrode formed on the dielectric film. Meanwhile, the method for fabricating the capacitor comprises the steps of: forming a lower electrode on a semiconductor substrate, forming a dielectric film of a dual dielectric film structure composed of an Si3N4 thin film and a Ta2O5 thin film on the lower electrode, and forming an upper electrode on the dielectric film.