Abstract: The present invention provides a permanent protective hardmask which protects the dielectric properties of a main dielectric layer having a desirably low dielectric constant in a semiconductor device from undesirable increases in the dielectric constant, undesirable increases in current leakage, and low device yield from surface scratching during subsequent processing steps. The protective hardmask further includes a single layer or dual layer sacrificial hardmask particularly useful when interconnect structures such as via openings and/or lines are formed in the low dielectric material during the course of making the final product. The sacrificial hardmask layers and the permanent hardmask layer may be formed in a single step from a same precursor wherein process conditions are altered to provide films of differing dielectric constants.

Abstract: A method for etching contact/via openings in low-k dielectric layers is described The method introduces a carbon deficient ARL which is compatible with the acidic photoresists used by DUV photolithography. The carbon deficiency of the ARL permits the use of fluorocarbon plasma etching ambients to etch the openings in the low-k layers without excessive polymer formation, thereby eliminating polymer pinch-off during the etching of deep, high aspect ratio contacts and vias in sub-tenth micron integrated circuit technology. Vertical walled contact and via openings may be formed using a DUV photoresist mask and non-oxygen containing fluorocarbon etching plasmas. An additional hardmask is therefore not needed. For non-carbon containing low-k dielectric layers the openings may be etched in simple fluorocarbon plasmas without excessive polymer formation.

Abstract: Degradation of organic-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ on the organic-doped silica glass inter-layer dielectric. The in-situ formation of the capping/ARC layer provides a strongly adhered capping/ARC layer, formed with fewer processing steps than conventional capping and ARC layers.

Abstract: A method for fabricating a Mask ROM is described, in which an ONO composite layer and a plurality of gate structures are formed on a substrate. A plurality of bit-lines are formed in the substrate between the gate structures and a plurality of word-lines are formed over the substrate to electrically connect with the gate structures. A chemical vapor deposition anti-reflective coating (CVD-ARC) with coding windows therein and an inter-layer dielectric layer are formed over the substrate. A coding process is then performed by using UV light to form a plurality of charged coding regions in the charge trapping layer not covered by the CVD-ARC. A plurality of plugs are then formed in the coding windows.

Abstract: In a method of manufacturing a contact element, provision is made of a laminated body which has an insulating film, an electrically conductive layer stacked on the insulating film, and bump holes opened. A treatment is carried out so as to remove organic materials and the like from an interior of the bump holes and/or a surface of the insulating film before bumps are formed on the bump holes. The treatment may be a plasma treatment or an X-ray irradiation.

Abstract: The invention includes a semiconductor processing method in which a semiconductor substrate is exposed to reactive ion etching conditions. The reactive ion etching conditions comprise subjecting exposed surfaces of the substrate to a gas having components therein which are reactive with the exposed surfaces. A total concentration of the reactive components within the gas is less than 4.5%, by volume. In particular aspects, the total concentration of the reactive components can be less than 2% by volume, or less than 1% by volume. Exemplary reactive components are fluorine-containing components, such as NF3.

Abstract: A fabrication process for making a semiconductor device, which contains a dry etch plasma process that utilizes CO2 to etch a film. Furthermore, the dry etch plasma process may utilize CO2 in combination with NH3, H2, Ar, N2, He, or other inert gases during the etching process. The CO2 dry etch plasma process etches an anti-reflectant coating layer while enabling greater selectivity and control with regard to the underlying films.

Abstract: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

Abstract: After an etching stop layer and an interlayer dielectric film are formed on a semiconductor substrate including a contact formation portion, a polysilicon film and a anti-reflective layer are successively formed on the interlayer dielectric film. A second mask pattern exposing the polysilicon film is formed after etching the anti-reflective layer exposed through a first mask pattern. A third mask pattern is formed by attaching polymer on a sidewall of the second mask pattern. A contact hole exposing the contact formation portion is formed by etching the polysilicon film and the interlayer dielectric film using the third mask pattern as an etching mask. A conductive material is filled in the contact hole to form the contact. By attaching the polymer to the second mask pattern, a contact hole with a minute size can be formed.

Abstract: A multilayer electrically conductive stack is formed in a semiconductor device prior to one step of photolithography. In this multilayer electrically conductive stack, alternate layers of the stack contain materials that differ in their refractive indices. In one instance, the electrically conductive stack can serve as an anti-reflective coating in the photolithographical processing. As the electrically conductive stack has chemical and electrical properties similar to those of an underlying device structures, removal of the multilayer stack after the photolithographical step is not required. In one instance, the electrically conductive stack can be used to form a gate structure or an interconnect structure. In an embodiment of the invention, alternate layers consist of Si1−xGex and Si, respectively.

Abstract: A method for manufacturing a semiconductor device includes providing a dielectric layer over a substrate, providing a first photoresist layer over the dielectric layer, patterning and defining the first photoresist layer, etching the first photoresist layer and the dielectric layer to form a plurality of vertical openings, removing the first photoresist layer, depositing a second photoresist layer over the dielectric layer, wherein the second photoresist layer fills the plurality of vertical openings, removing only a portion of the second photoresist layer deposited over the dielectric layer, wherein the second photoresist layer has a first substantially uniform thickness over the dielectric layer, depositing an anti-reflection coating layer over the second photoresist layer, providing a third photoresist layer over the anti-reflection coating layer, patterning and defining the third photoresist layer, and etching the anti-reflection coating layer and the second photoresist layer to form a plurality of trench

Abstract: The present invention is directed to a silicon carbide anti-reflective coating (ARC) and a silicon oxycarbide ARC. Another embodiment is directed to a silicon oxycarbide ARC that is treated with oxygen plasma. The invention includes method embodiments for forming silicon carbide layers and silicon oxycarbide layers as ARC's on a semiconductor substrate surface. Particularly, the methods include introducing methyl silane materials into a process chamber where they are ignited as plasma and deposited onto the substrate surface as silicon carbide. Another method includes introducing methyl silane precursor materials with an inert carrier gas into the process chamber with oxygen. These materials are ignited into a plasma, and silicon oxycarbide material is deposited onto the substrate. By regulating the oxygen flow rate, the optical properties of the silicon oxycarbide layer can be adjusted. In another embodiment, the silicon oxycarbide layer can be treated with oxygen plasma.

Abstract: The invention relates to a method for producing an integrated circuit comprising the following steps: preparing a semi-conductor substract (1) with a contracting circuit area (SS); providing an insulating layer (IS) on the surface of the semi-conductor substrate (1): providing a contact hole (KL) in the insulating layer (IS) for making contacting the circuit area (SS); providing an insulating spacer area (10′) in at least the area above the contact hole (KL); providing at least three trenches (BG1; BG2; BG3), the first (BG1) of which is arranged next to the contact hole (KL), a second (BG2) is disposed across the contact hole (KL) and a third (BG3) is next to the contact hole (KL). The spacer area (10′) is placed between the first and second trench (BG1; BG2) and the second and the third trench (BG2; BG3); filling the trenches (BG1; BG2; BG3) with a conductive material: and chemical-mechanical polishing of conductive material for producing three seperated trenches (BL1; BL2; BL3).

Abstract: After a plurality of grooves are formed in an insulating film and in an anti-reflection film on the insulating film, a barrier metal film and a conductive film are deposited on the anti-reflection film such that each of the grooves is filled therewith. Subsequently, the portions of the conductive film outside the grooves are removed by polishing and then the portions of the barrier metal film outside the grooves are removed by polishing. Thereafter, respective foreign matters adhered to a polishing pad and to a surface to be polished during polishing are removed and then a surface of the anti-reflection film is polished.

Abstract: An anti-reflective coating material layer is provided that has a relatively high etch rate such that it can be removed simultaneously with the cleaning of a defined opening in a relatively short period of time without affecting the critical dimensions of the opening. A method of forming such a layer includes providing a substrate assembly surface and using a gas mixture of at least a silicon containing precursor, a nitrogen containing precursor, and an oxygen containing precursor. The layer is formed at a temperature in the range of about 50° C. to about 600° C. Generally, the anti-reflective coating material layer deposited is SixOyNz:H, where x is in the range of about 0.39 to about 0.65, y is in the range of about 0.02 to about 0.56, z is in the range of about 0.05 to about 0.33, and where the atomic percentage of hydrogen in the inorganic anti-reflective coating material layer is in the range of about 10 atomic percent to about 40 atomic percent.

Abstract: The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown from a seed layer to substantially fill openings in a two layer structure wherein the two layers are independently either dielectric or resist layers. According to one aspect of the invention, first and second resist layers are formed into a dual damascene structure. Copper is grown by plating from the copper seed layer to form copper features that fill the pattern gaps.

Abstract: A method for removing a dielectric anti-reflective coating (DARC) of silicon oxynitride material from a layer of insulative material which is formed over a substrate in a semiconductor device involves contacting the DARC material with a mixture of tetramethylammonium fluoride and at least one acid such as hydrofluoric acid, hydrochloric acid, nitric acid, phosphoric acid, acetic acid, citric acid, sulfuric acid, carbonic acid or ethylenediamine tetraacetic acid. Contact with the mixture is for a time period sufficient to remove substantially all of the DARC material. The mixture has a high etch rate selectivity such that the DARC coating can be removed with minimal effect on the underlying insulative layer.

Abstract: A method of fabricating an integrated circuit in and on a semiconductor substrate with deep implantations by applying a scattered ion capturing layer in the resist mask opening to capture any implanted ions scattered in the resist and deflected out of the resist into the mask opening to prevent these ions from reaching the semiconductor substrate and affecting the concentration of ions at the edge of the mask and thus the performance of the integrated circuit.

Abstract: An integrated circuit device, such as a merged device, is formed by forming a first gate oxide layer on a first region, such as a logic circuit region, of a substrate. A conductive layer is formed on the first gate oxide layer. A second gate oxide layer is formed on a second region, such as a cell array region, of the substrate. A first gate pattern is formed on the second gate oxide layer. The conductive layer and the first gate oxide layer are patterned to form a second gate pattern. A silicide layer is formed on the second gate pattern and in the substrate adjacent to the second gate pattern.

Abstract: A method of manufacturing for a MirrorBit® Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines in the semiconductor substrate. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited thereon. An anti-reflective coating (ARC) material is deposited on the hard mask material and a photoresist material is deposited on the ARC followed by processing the photoresist material and the ARC material to form a photomask of a patterned photoresist and a patterned ARC. The hard mask material is processed using the photomask to form a hard mask. The patterned photoresist is removed and then the patterned ARC without damaging the hard mask or the wordline material. The wordline material is processed using the hard mask to form a wordline and the hard mask is removed without damaging the wordline or the charge-trapping material.

Abstract: A method of forming a via-first type dual damascene structure in the absence of an etch stop layer and without via-edge erosion or via-bottom punch-through is described. The invention uses two organic films deposited within via hole prior to trench etching. A via bole over a lower level metal line is first etched in the dielectric film. Two, preferably organic, bottom antireflective coating (BARC) films, first one being the conformal type to coat the surfaces and the walls of the via and the second one being the planarizing type to at least partially fill the via, are then deposited. Using a mask aligned to via hole, a wiring trench of desired depth is etched in the top portion of the dielectric film. During trench etching, the conformal BARC-1 film protects the via-edges from eroding and the planarizing BARC-2 film prevents punch-through of the via-bottom. Desired metal such as aluminum or copper are deposited within said dual damascene pattern.

Abstract: During etching of a BARC film, etching gas is used in which O2, Cl2 and He are mixed in appropriate flow volume ratios, and an appropriate ion energy is set. Thus, a selectivity ratio with respect to an underlying film, which is a SiN film, can be sufficiently assured and a pattern is formed uniformly. During etching of a SiN film, etching gas is used in which HBr, CH4 and He are mixed in appropriate flow volume ratios, and an appropriate ion energy is set. Thus, the form of a pattern is consistent regardless of high- and low-density portions.

Abstract: An organic ARC film is formed on a semiconductor substrate. A resist is applied to the organic ARC film and exposure and development processes are carried out, thereby a predetermined resist pattern is formed. This resist pattern is used as a mask so as to carry out, on the exposed organic ARC film, a dry etching process for a period of time of approximately 15 seconds using a gas including, thereby the organic ARC film is removed so as to expose the surface of the semiconductor substrate. Next, predetermined impurity ions are implanted into the semiconductor substrate using the resist pattern and the organic ARC film located directly beneath this resist pattern as a mask, thereby an impurity region is formed in the surface of the exposed semiconductor substrate. Thereby, implantation treatment and wet etching treatment can be carried out without fail using the resist pattern as a mask.

Abstract: Precisely forming a fine resist pattern on a stopper film of silicon nitride, in a method of manufacturing a multi-layer interconnection structure which uses the stopper film. A silicon nitride film forming step is a step to select a thickness of a silicon nitride film to thereby reduce reflection light of an excimer laser which impinges upon a photoresist layer on the silicon nitride film from the back surface of the photoresist layer.

Abstract: The present invention generally provides a process for depositing silicon carbide using a silane-based material with certain process parameters that is useful for forming a suitable ARC for IC applications. The same material may also be used as a barrier layer and an etch stop, even in complex damascene structures and with high diffusion conductors such as copper as a conductive material. Under certain process parameters, a fixed thickness of the silicon carbide may be used on a variety of thicknesses of underlying layers. The thickness of the silicon carbide ARC is substantially independent of the thickness of the underlying layer for a given reflectivity, in contrast to the typical need for adjustments in the ARC thickness for each underlying layer thickness to obtain a given reflectivity.

Abstract: In accordance with the objectives of the invention a new processing sequence is provided for the creation of a layer of ARC. A first layer of ARC is deposited over a supporting surface, a blanket etch is performed to the surface of the first layer of ARC, leaving any openings that have been created in the supporting surface essentially filled with ARC material. A second layer of ARC is next applied over the surface of the etched first layer of ARC, this second layer of ARC provides a layer of ARC that is of uniform thickness over the supporting surface. Steps of baking may be applied to each of the layers of ARC after these layers have been deposited or after the first layer of ARC has been etched.

Abstract: A method of manufacturing a semiconductor device capable of preventing reduction of reliability when employing an anti-reflection coating for forming two stages of openings in an interlayer dielectric film is obtained. This method of manufacturing a semiconductor device comprises steps of forming a first resist pattern on a prescribed region of the anti-reflection coating, forming a first opening in the interlayer dielectric film through a mask of the first resist pattern, removing the first resist pattern while leaving the anti-reflection coating and thereafter forming a second resist pattern on a prescribed region of the anti-reflection coating and forming a second opening having a larger opening area than the first opening at least on an upper portion of the first opening through a mask of the second resist pattern.

Abstract: A system and apparatus is provided for preventing damage to gate oxide due to ultraviolet radiation associated with semiconductor processes. Included is a substrate and a gate formed on the substrate. The gate includes a gate material layer and a gate oxide layer stacked on the substrate. A pair of spacers are situated on opposite sides of the gate. Deposited over the gate and the spacers is an ultraviolet radiation blocking material for preventing the ultraviolet radiation from damaging the gate oxide layer of the gate. Finally, at least one metal and intermetal oxide layer is positioned over the ultraviolet radiation blocking material. In an alternate embodiment, instead of the ultraviolet radiation blocking material being deposited over the gate and the spacers, the spacers are constructed from an ultraviolet radiation blocking material for preventing the ultraviolet radiation from damaging the gate oxide layer of the gate.

Abstract: Antireflective structures according to the present invention comprise a metal silicon nitride composition in a layer that is superposed upon a layer to be patterned that would other wise cause destructive reflectivity during photoresist patterning. The antireflective structure has the ability to absorb light used during photoresist patterning. The antireflective structure also has the ability to scatter unabsorbed light into patterns and intensities that are ineffective to photoresist material exposed to the patterns and intensities. Preferred antireflective structures of the present invention comprise a semiconductor substrate having thereon at least one layer of a silicon-containing metal or silicon-containing metal nitride. The semiconductor substrate will preferably have thereon a feature size with width dimension less than about 0.5 microns, and more preferably less than about 0.25 microns.

Abstract: A process is disclosed for forming an integrated circuit structure characterized by formation of a combined dielectric layer and antireflective coating layer. The process comprises forming a layer of dielectric material over an integrated circuit structure, and treating the surface of the layer of dielectric material to form an antireflective coating (ARC) surface therein. When a layer of photoresist is then formed over the ARC surface, and the layer of photoresist is exposed to a pattern of radiation, the ARC surface improves the accuracy of the replication, in the photoresist layer, of the pattern of radiation. Preferably, the surface of the dielectric layer is treated with a plasma comprising ions of elements and/or compounds to form the ARC surface.

Abstract: A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. Another method of forming the stack includes forming a pad oxide layer on the semiconductor substrate assembly. A first oxidation diffusion barrier layer is then formed on the pad oxide layer, an inorganic antireflective material layer is formed on the first oxidation diffusion barrier layer, and a second oxidation diffusion barrier layer is formed on the inorganic antireflective material layer.

Abstract: Within a damascene method for forming a patterned conductor layer having formed interposed between its patterns a dielectric layer formed of a comparatively low dielectric constant dielectric material method, there is employed a hard mask layer formed upon the dielectric layer. The hard mask layer is formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency power of from about 100 to about 500 watts per square centimeter substrate area. The hard mask layer provides for attenuated abrasive damage to the dielectric layer.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.

Abstract: A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.

Abstract: A method of forming a stacked dielectric layer on a semiconductor substrate having metal patterns. A first dielectric layer is formed on the semiconductor substrate. Next, a second dielectric layer is formed on the first dielectric layer to generate a composite dielectric layer. The second dielectric layer has a dielectric constant (k) higher than that of the first dielectric layer, a hardness higher than that of the first dielectric layer, and a thickness less than that of the first dielectric layer. The steps of forming the first dielectric layer and second dielectric layer can be repeated at least 2 to 3 times to form a stacked dielectric layer.

Abstract: There is provided a method of making a dual inlaid via in a first layer. The first layer may be a polymer intermetal dielectric, such as HSQ, of a semiconductor device. The method includes forming a first opening, such as a via, in the first layer and forming a bilayer resist in the first opening. The bilayer resist includes an imaging layer above a bottom antireflective coating (BARC). The imaging layer is selectively exposed to radiation such that no radiation reaches the lower section of the BARC in the first opening through the upper section of the BARC. The bilayer resist is pattered, and a second opening, such as a trench, is formed in communication with the first opening using the patterned bilayer resist as a mask.

Abstract: An improved photolithography technique is provided whereby the beneficial effects of using an anti-reflective coating may be realized while maintaining critical dimensions in each subsequent step. This improvement is realized by the treatment of the anti-reflective coating with a gaseous plasma or a solution of sulfuric acid and hydrogen peroxide. By treating the anti-reflective coating with gaseous plasma or solution of sulfuric acid and hydrogen peroxide, no “footing” results and the critical dimensions as set by the photoresist mask are preserved to provide an accurately patterned mask for subsequent steps.

Abstract: The invention relates to a method of manufacturing a semiconductor device, comprising the provision of a substrate (1) having a dielectric layer (2) on this substrate (1), a conductive layer (3) on the dielectric layer (2), an inorganic anti-reflection coating (4) on the conductive layer (3), and a resist mask (6) on the inorganic anti-reflection coating (4). The method further comprises the following steps: patterning the inorganic anti-reflection coating (4) by means of the resist mask (6), patterning the conductive layer (3) by etching down to the dielectric layer (2), removing the resist mask (6), and removing the inorganic anti-reflection coating (4). According to the invention, the inorganic anti-reflection coating (4) is removed by means of a dry etch, using a polymerizing gas. It is achieved by this that no or hardly any changes in the critical dimension will occur.

Abstract: An interconnection pattern is formed over the surface of a silicon wafer in which both the vias and the trenches of the pattern are filled with copper. The process of filling the vias and trenches involves use of a silicon nitride film as an etch stop and the filling of the vias with an anti-reflection coating.

Abstract: The invention includes a semiconductor processing method in which a semiconductor substrate is exposed to reactive ion etching conditions. The reactive ion etching conditions comprise subjecting exposed surfaces of the substrate to a gas having components therein which are reactive with the exposed surfaces. A total concentration of the reactive components within the gas is less than 4.5%, by volume. In particular aspects, the total concentration of the reactive components can be less than 2% by volume, or less than 1% by volume. Exemplary reactive components are fluorine-containing components, such as NF3.

Abstract: A process of removing excess conductive material from the exposed surface of a dielectric layer, the process comprising the steps of forming a shield layer on the dielectric layer, forming a sacrificial layer on top of the shield layer, depositing the conductive material on top of the sacrificial layer so that the conductive material is positioned within cavities in the dielectric material, and then using chemical mechanical planarization to remove the excess conductive material and the sacrificial layer. The use of a sacrificial layer interposed between the shield layer and the excess conductive material allows for chemical mechanical planarization to fully remove the sacrificial layer to facilitate more uniform removal of excess conductive material.

Abstract: A new processing sequence is provided for the creation of a MIM capacitor. The process starts with the deposition of a first layer of metal. Next are deposited listed, a thin layer of metal, a layer of insulation, a second layer of metal and a layer of Anti Reflective Coating. An etch is then performed to form the second electrode of the MIM capacitor (using the etch stop layer to stop this etch), MIM spacers are formed on the sidewalls of the second electrode of the MIM capacitor (also using the etch stop layer to stop this etch). The dielectric and first electrode of the MIM capacitor are formed by etching through the second layer of insulation and the first layer of metal. This is followed by conventional processing to create contact points to the MIM capacitor.

Abstract: There is presented a semiconductor device including multiple levels of copper interconnects; wherein the surface of a copper interconnect corresponding to at least one underlying layer of another copper interconnect layer is turned into copper oxide to a thickness of 30 nm or more by oxidation conducted at the oxidation rate of 20 nm/min or less, and thereby the reflection of the exposure light from the lower-level copper interconnect is prevented, in forming by means of photolithography a trench to form a copper interconnect through damascening.

Abstract: A method and structure for fabricating a dual damascene copper interconnect which electrically contacts a damascene tungsten wiring level. The method forms a first layer on a semiconductor substrate, a silicon nitride layer on the first layer, and a silicon dioxide layer on the silicon nitride layer. The first layer includes damascene tungsten interconnect regions separated by insulative dielectric material. A continuous space is formed by etching two contact troughs through the silicon dioxide and silicon nitride layers to expose damascene tungsten interconnect regions, and by etching a top portion of the silicon dioxide layer between the two contact troughs. A reduced-height portion of the silicon dioxide layer remains between the two contact troughs. The continuous space is filled with damascene copper. The resulting dual damascene copper interconnect electrically contacts the exposed damascene tungsten interconnect regions.

Abstract: A method of forming an HDP CVD oxide layer over a metal line structure, comprising the following steps. A semiconductor structure having metal lines formed thereon to form a metal line structure is provided. The metal lines having exposed sidewalls. The metal line structure is treated with N2O to form a layer of Al2O3 on each of the metal line exposed sidewalls to form a N2O treated metal line structure. An HDP CVD oxide layer is formed over the N2O treated metal line structure to form a resulting metal line structure. Whereby the resulting metal line structure is free of metal voids.

Abstract: A light shield apparatus and formation method for preventing the transmission of incident light towards active devices of the display. In one embodiment, the present invention recites forming a plurality of metal pixels wherein adjacent ones of the plurality of metal pixels have a gap region disposed therebetween. The present embodiment then recites depositing a light absorbing antireflective coating material within the gap region to form a light shield such that transmission of incident light through the gap region towards underlying active devices is reduced. Hence, the present embodiments also reduce problems associated with Liquid Crystal alignment difficulty and passivation integrity (cracking of thin passivation). Next, the present embodiment deposits a thin composite passivation layer above the plurality of metal pixels and the antireflective coating material.

Abstract: Metal oxide is produced by heating a metal salt of a carboxylic acid to a predetermined temperature, which varies with a raw material, lower than 300° C. In the case of using zinc acetate as the raw material, when heated in dry helium gas, it is sublimated and decomposed to produce no zinc oxide. In contrast, when heated in a mixture gas of nitrogen gas and water vapor with a programming rate of 5° C./min, the weight loss begins around 110° C. and has been completed around 230° C., at a water vapor partial pressure of 17.9 kPa, to produce zinc oxide. If keeping the temperature approximately constant when the weight loss begins, zinc oxide is produced around 115° C. with a high degree of crystallinity. A metal may be any one of zinc, cadmium, indium and copper. A carboxylic acid may be any one of formic acid, acetic acid, propionic acid and 2-ethylhexanoic acid.

Abstract: With standard DUV lithography technology it is not easy to achieve MOS transistor gates in sub-100 nm range. With the method of trim-etching in HI/O2 plasmas there is an opportunity to use the current lithography tools, to reduce the dimensions of the resist feature, and to achieve sub-100 nm MOS transistor gates for advanced devices. The method of trim-etching in HI/O2 plasmas delivers another factor to control the critical dimension of the MOS devices very accurately. Therefore, this invention helps to significantly reduce the total cost for manufacturing small MOS devices with a critical dimension in the sub-100 nm range.

Abstract: A method for forming a line of a semiconductor device is provided, which improves the life span of the line and its reliability by improving resistance to electromigration (EM).

Abstract: A method for etching and removing an anti-reflective coating from a substrate. The method comprises providing a substrate supporting a conductive layer (a tungsten-silicide layer) having an anti-reflective coating (e.g., a dielectric anti-reflective coating) disposed thereon. The anti-reflective coating is etched with an etchant gas consisting of NF3 and Cl2 to break through and to remove at least a portion of the anti-reflective coating to expose at least part of the conductive layer. The conductive layer is subsequently etched with the etchant gas to produce an anti-reflective coating gate structure which is used in semiconductor integrated circuits containing transistors.