Abstract: A process for defining an aluminum based structure, on an underlying titanium nitride shape, via use of a two step dry etching procedure, has been developed. A first iteration of the two step dry etching process features initial definition of the aluminum based structure, on an underlying titanium nitride layer, using a photoresist shape as an etch mask, performed in a chlorine based environment, with the first dry etching step terminating at the appearance of the titanium nitride layer. A second dry etching step features the introduction of a fluorine based etchant, to the chlorine based environment, forming a protective aluminum fluoride layer on the exposed sides of the aluminum based structure during definition of the titanium nitride shape. A second iteration of the two step dry etching process features the removal of the masking photoresist shape after definition of the aluminum based structure, via the first dry etching step.

Abstract: Certain embodiments provide a method for fabricating a semiconductor device in which a conductive layer containing silicon can be etched in a predetermined shape without adversely affecting a gate insulating film. A method for fabricating a semiconductor device in accordance with the present invention includes forming an oxide film 24 on a p-type silicon substrate 10 and forming a polysilicon layer 26 on the oxide film 24. A stopper layer 28 is formed on the surface of the polysilicon layer 26 and an organic antireflection coating 30 is formed on the surface of the stopper layer 28. A resist layer R is formed on the surface of the organic antireflection coating 30. The method also includes etching the organic antireflection coating 30 using the resist layer R as a mask and etching the stopper layer 28. The polysilicon layer 26 is also etched in a predetermined pattern to form a gate electrode.

Abstract: A first interconnection is formed in a first interlayer insulating film. An etching stopper film is formed on the first interconnection. On the etching stopper film, a second interlayer insulating film and an anti-reflective coating are successively formed, and a via hole penetrating the second interlayer insulating film and the anti-reflective coating to reach the etching stopper film is formed. An organic film is formed in the via hole, and a trench reaching the organic film is formed in the second insulating film. By removing the anti-reflective coating and the etching stopper film at the bottom portion of the via hole, a portion of the surface of the first interconnection is exposed, and a second interconnection is formed in the trench and the via hole.

Abstract: An improved method for applying polymeric antireflective coatings to substrate surfaces and the resulting precursor structures are provided. Broadly, the methods comprise plasma enhanced chemical vapor depositing (PECVD) a polymer on the substrate surfaces. The most preferred starting monomers are 4-fluorostyrene, 2,3,4,5,6-pentafluorostyrene, and allylpentafluorobenzene. The PECVD processes comprise subjecting the monomers to sufficient electric current and pressure so as to cause the monomers to sublime to form a vapor which is then changed to the plasma state by application of an electric current. The vaporized monomers are subsequently polymerized onto a substrate surface in a deposition chamber. The inventive methods are useful for providing highly conformal antireflective coatings on large surface substrates having super submicron (0.25 &mgr;m or smaller) features.

Abstract: A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing “bumps” or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.

Abstract: A method of manufacturing a semiconductor device is capable of preventing a local delamination at the interface between an aluminum film and an anti-reflective layer formed thereon. After aluminum is deposited on a substrate, the aluminum film is slowly cooled. Then, the substrate is left as is for more than 3 minutes before a venting process takes place in which thermal energy is generated. Then, an anti-reflective layer is formed on the aluminum film. Thermal stress in the aluminum film is relieved by the slow cooling of the aluminum film and the delay before the venting process. Accordingly, when a thermal process is carried out after the anti-reflective layer is formed on the aluminum film, little shear stress is generated at the interface between the aluminum film and the anti-reflective layer.

Abstract: An image sensor system and methods of making such a system are described. The image sensor system includes a color filter array that is formed by a color filter process that incorporates a bottom antireflection coating. The bottom antireflection coating forms a protective layer that protects exposed areas of the active image sensing device structure during formation of the color filter array and, thereby, preserves the intrinsic transmission characteristics of the active image sensing device structure. The bottom antireflection coating also reduces degradation of metal structures (e.g., bonding pads) and pixel edges at the exposed surface of the active image sensing device structure. In addition, the bottom antireflection coating provides a reliable adhesive surface for the color filter array, substantially eliminating lifting of the color filter array resist structures.

Abstract: An anti-reflection structure formed on a gate electrode in a MOSFET device includes a first and second anti-reflection layers sandwiching therebetween a silicon nitride layer. Each of the anti-reflection layers has a two-layer structure including a silicon oxide nitride film and a protective silicon oxide film. The anti-reflection layer structure improves the accuracy of the pattern size for the gate electrode.

Abstract: An anti-reflection structure formed on a gate electrode in a MOSFET device includes a first and second anti-reflection layers sandwiching therebetween a silicon nitride layer. Each of the anti-reflection layers has a two-layer structure including a silicon oxide nitride film and a protective silicon oxide film. The anti-reflection layer structure improves the accuracy of the pattern size for the gate electrode.

Abstract: A method for manufacturing a multi-level interconnection structure in a semiconductor device includes the steps of consecutively forming an anti-diffusion film and an interlevel dielectric film on a first level Cu layer, forming first through third hard mask films on the interlevel dielectric film, etching the interlevel dielectric film by using the first hard mask to form first through-holes, etching the first and second hard mask films and a top portion of the interlevel dielectric film by using the third hard mask film to form trenches, and etching the anti-diffusion film to form through-holes. The first hard mask film protects the interlevel dielectric film during removal of the second and third hard mask films.

Abstract: An exemplary method of forming contact holes includes providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ARC features; forming spacers on lateral sides of the ARC features; and etching trench lines using the spacers and ARC features as hard mask to define portions of the layer of material which are etched.

Abstract: A method of manufacturing a semiconductor device is capable of preventing a local delamination at the interface between an aluminum film and an anti-reflective layer formed thereon. After aluminum is deposited on a substrate, the aluminum film is slowly cooled. Then, the substrate is left as is for more than 3 minutes before a venting process takes place in which thermal energy is generated. Then, an anti-reflective layer is formed on the aluminum film. Thermal stress in the aluminum film is relieved by the slow cooling of the aluminum film and the delay before the venting process. Accordingly, when a thermal process is carried out after the anti-reflective layer is formed on the aluminum film, little shear stress is generated at the interface between the aluminum film and the anti-reflective layer.

Abstract: After a wiring material layer (14) which is made of WSi2 or the like is formed on an insulation film covering a semiconductor substrate (10), a first antireflection coating film (18) which is made of TiON or TiN and a second antireflection coating film (18) which is made of an organic material are sequentially formed on the wiring material layer (14). Resist patterns (20a to 20c) are formed on the second antireflection coating film (18) by photolithography. The dry etching of the second antireflection coating film (18) is performed using the resist patterns (20a to 20c) as masks, after which the dry etching of the first antireflection coating film (16) is conducted using the resist patterns (20a to 20c) and patterns (18a to 18c) of the second antireflection coating film (18) as masks.

Abstract: A new processing sequence is provided for the creation of a MIM capacitor. The process starts with the deposition of a first layer of metal. Next are deposited listed, a thin layer of metal, a layer of insulation, a second layer of metal and a layer of Anti Reflective Coating. An etch is then performed to form the second electrode of the MIM capacitor (using the etch stop layer to stop this etch), MIM spacers are formed on the sidewalls of the second electrode of the MIM capacitor (also using the etch stop layer to stop this etch). The dielectric and first electrode of the MIM capacitor are formed by etching through the second layer of insulation and the first layer of metal. This is followed by conventional processing to create contact points to the MIM capacitor.

Abstract: A fine pattern forming method of a semiconductor device sequentially deposits an etch-target layer to be formed as the fine pattern, an anti-reflective layer and a photoresist film on a prepared semiconductor substrate and forms a photoresist pattern by performing photolithography for the photoresist film with an ArF exposure source. Then, two etching processes are performed to form the fine pattern. In one etching process, there are etched the anti-reflective layer and a portion of a non-pattern area of the etch-target layer at a first substrate temperature with fluorine-based gas and argon gas by using the photoresist pattern as an etching mask. In the other etching process, there is etched a remaining portion of the non-pattern area of the etch-target layer at a second substrate temperature higher than the first substrate temperature with fluorine-based gas and argon gas.

Abstract: Disclosed herein is a method comprised of forming a metal layer above a structure layer on a workpiece, measuring a thickness of the metal layer, determining, based upon the measured thickness of the metal layer, at least one parameter of an etching process to be performed on the metal layer, and performing the etching process comprised of the determined parameter on the metal layer. Also disclosed is a system comprised of a deposition tool for forming a metal layer above a structure layer on a workpiece, a metrology tool for measuring a thickness of the metal layer, a controller for determining, based upon the measured thickness of the metal layer, at least one parameter of an etch process to be performed on the metal layer, and an etch tool adapted to perform an etch process comprised of the determined parameter on the metal layer.

Abstract: Embodiments of the invention comprise a new device and technique to realize an improved throughput of a BARC layer furnace deposition device. This improvement is achieved by providing for a higher flow rate of NH3 during the BARC deposition process. Also, this improvement may be achieved by reducing the temperature gradient of the BARC layer furnace deposition device to approximately 715-750° C. For example, approximately a 1-10% blend of NH3 in at least one of Argon, Nitrogen, and Helium is utilized. By diluting the NH3, a higher flow rate may be utilized in the furnace deposition device, thus allowing for an increased load uniformity of the BARC layer thickness, refractive index, extinction coefficient, and reflectivity characteristics. Also, the NH3 depletion is reduced and preferably eliminated due to the higher flow rate of the diluted NH3.

Abstract: A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. The antireflective material layer may include a layer of material selected from the group of silicon nitride, silicon oxide, and silicon oxynitride and further may be a silicon-rich layer. The oxidation diffusion barrier stacks may be used for oxidation of field regions for isolation in an integration circuit. Further, the various oxidation diffusion barrier stacks are also described.

Abstract: In providing a bottom antireflective coating (BARC) in a semiconductor structure, a primer layer, for example, hexamethyldisilazane (HMDS), is provided on a substrate, and the BARC is formed on the primer. This results in a substantially defect free BARC layer, having a more uniform reflectivity which in turn leads to improve to photolithographic pattern resolution.

Abstract: A method of forming an anti-reflective coating is described. A film is formed on a substrate. A first layer of an anti-reflective coating layer Is deposited on the film by chemical vapor deposition using a canrier gas, an organic halide gas and a hydrogen halide gas as gas sources. A second layer of the anti-reflective coating layer is formed on the first layer of the anti-reflective coating layer by chemical vapor deposition using a carrier gas and an organic halide gas as gas sources. A photoresist layer is formed on the second layer of the anti-reflective coating layer.

Abstract: The present invention is a method for integrating an anti-reflection layer and a salicide block. The method comprises the following steps: A substrate is provided that is divided into at least a sensor area and a transistor area, wherein the sensor area comprises a doped region and the transistor area comprises a transistor that includes a gate, a source and a drain; forming a composite layer on the substrate, wherein the composite layer at least also covers both the sensor area and the transistor area, and the composite layer increases the refractive index of light that propagates from the doped region into the composite layer; performing an etching process and a photolithography process to remove part of the composite layer and to let top of the gate, the source and the drain are not covered by the composite layer; and performing a salicide process to let top of the gate, the source and the drain are covered by a silicate.

Abstract: A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. Another method of forming the stack includes forming a pad oxide layer on the semiconductor substrate assembly. A first oxidation diffusion barrier layer is then formed on the pad oxide layer, an inorganic antireflective material layer is formed on the first oxidation diffusion barrier layer, and a second oxidation diffusion barrier layer is formed on the inorganic antireflective material layer.

Abstract: Disclosed is a method for producing semiconductor elements including a metal layer (10) configured on a semiconductor substrate (5). The inventive method consists of the following steps: a silicon layer (15) is deposited on a metal layer (10); an etch mask is applied in order to structure the silicon layer (1%); the silicon layer is selectively etched (15) using the etch mask (25); and the metal layer (10) is structured in an etching process using a selectively etched silicon layer (15) as a hard mask.

Abstract: In a solid state image sensor comprising a plurality of photoelectric conversion regions and a plurality of transfer regions which are formed in a principal surface of a semiconductor substrate, and a plurality of transfer electrodes formed above the transfer regions, a first insulating film, an antireflection film and a second insulating film are formed in the named order on the photoelectric conversion regions. The antireflection film has a refractive index larger than that of the second insulating film but smaller than that of the semiconductor substrate. The stacked film composed of the first insulating film, the antireflection film and the second insulating film, is formed, in the transfer regions, to extend over the transfer electrode which is formed a third insulating film formed on the semiconductor substrate.

Abstract: A conducting line of a semiconductor device using an aluminum oxide layer as a hard mask, and a method of forming the conducting line. The conducting line, such as a gate line or a bit line of a semiconductor device, includes a conductive layer formed on a semiconductor substrate, a capping insulation layer formed on the conductive layer, and an aluminum oxide layer formed on the capping insulation layer, with the aluminum oxide layer being used as a hard mask.

Abstract: The dimensional accuracy of trenches and, hence, the width of metal lines, in damascene interconnection structures is improved by employing silicon carbide as a capping layer/BARC on an underlying metal feature, e.g., Cu. Embodiments include via first-trench last dual damascene techniques employing a silicon carbide capping layer/BARC having an extinction coefficient (k) of about −0.2 to about −0.5, without the need for a middle etch stop layer, thereby improving efficiency by reducing the number of processing steps.

Abstract: A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a dielectric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.

Abstract: The dimensional accuracy of trench formation and, hence, metal line width, in damascene technology is improved by employing a low Si—SiON etch stop layer/ARC with reduced etch selectivity with respect to the overlying dielectric material but having a reduced extinction coefficient (k). Embodiments include via first-trench last dual damascene techniques employing a low Si—SiON middle etch stop layer/ARC having an extinction coefficient of about −0.3 to about −0.6, e.g., about −0.35, with reduced silicon and increased oxygen vis-à-vis a SiON etch stop layer having an extinction coefficient of about −1.1. Embodiments also include removing about 60% to about 90% of the low Si—SiON etch stop layer/ARC during trench formation, thereby reducing capacitance.

Abstract: One aspect of the present invention relates to a method of processing a semiconductor structure, involving the steps of providing a substrate having an insulation layer thereover; forming a first antireflection coating over the insulation layer; patterning a first resist over the antireflection coating; forming a plurality of vias in the insulation layer and the first antireflection coating, the vias having a first width; filling the via with a second antireflection coating, the second antireflection coating comprising a dye and a film forming material; patterning a second resist over the structure and removing the second antireflection coating from the via; forming a trench over the plurality of vias in the insulation layer, the trench having a width that is larger than the average width of the vias; and filling the trench and vias with a conductive material.

Abstract: A method for manufacturing a semiconductor device can form a thick lower electrode made of Pt. The method begins with the preparation of an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs. Thereafter, a seed layer is formed on top of the active matrix and a dummy oxide layer is formed on top of the seed layer. Then, the dummy oxide layer is patterned into a predetermined configuration, thereby exposing portions of the seed layer which are located on top of the conductive plugs. The exposed portions are filled with a conductive material to a predetermined thickness. The dummy oxide layer and portions of the seed layer which are not covered with the conductive material are removed, thereby obtaining lower electrodes. A capacitor dielectric layer is on the lower electrodes. Finally, an upper electrode layer is formed on the capacitor dielectric layer.

Abstract: For fabricating a field effect transistor within an active device area of a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate. A layer of gate electrode material is deposited on the layer of gate dielectric material, and the gate electrode material is a semiconductor material. At least one of an N-type dopant or a P-type dopant or a neutral dopant is implanted into the layer of gate electrode material such that the at least one of an N-type dopant or a P-type dopant or a neutral dopant has a dopant concentration in the layer of gate electrode material. A layer of photo-resist material, a layer of BARC (bottom anti-reflective coating) material, and the layer of gate electrode material are patterned to form a gate structure of the field effect transistor. The gate structure is comprised of the remaining gate electrode material, and the BARC (bottom anti-reflective coating) material remains on the gate structure.

Abstract: In forming an interconnection having a structure in which an Al interconnection is covered with an interlayer insulating film, for the purpose of preventing voids to be created in the Al interconnection layer, together with suppressing the current leakage owing to the generation of etching residues, a multi-layered structure including a barrier layer (4), an Al interconnection metal layer (5), a Ti layer (2b) and an anti-reflection layer (6) is formed on a semiconductor substrate having an insulating surface, and thereafter layers of said multi-layered structure are patterned, at least, down to the Ti layer (2b) into the shape of structure is heated so as to turn the Ti layer (2b) into an AlTi alloy layer and, then, the steps of growing an interlayer insulating film to bury said patterned interconnection planarizing the interlayer insulating film and carrying out another heat treatment to degas the interlayer insulating film are performed.

Abstract: An antireflection coating has two-layer structure including lower and upper silicon nitride films (p-SiN films) formed by plasma CVD. For the lower p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.9 nor more than 2.5, the imaginary part is set in the range of not less than 0.9 nor more than 1.7, and the film thickness is set in the range of not less than 20 nm nor more than 60 nm. For the upper p-SiN film, the real part of its complex index of refraction is set in the range not less than 1.7 nor more than 2.4, the imaginary part is set in the range of not less than 0.15 nor more than 0.75, and the film thickness is set in the range of not less than 10 nm nor more than 40 nm.

Abstract: After a contact hole is filled with an antireflection film and a resist film, the resist film is patterned such that the resist film of an area larger than the opening of the portion where the contact hole is to be formed is left above the contact hole. The antireflection film is removed with the patterned resist film used as a mask, followed by forming a second interlayer film on the entire surface. The second interlayer film is planarized so as to expose at least the upper surface of the resist film to the outside. Then, the resist film and the antireflection film are removed so as to form a contact hole and a groove.

Abstract: A method of manufacturing a semiconductor device includes sequential steps of forming a gate insulating layer, a first conductive layer, an etch stop layer, a hard mask layer, and an anti-reflective layer on a semiconductor substrate. The anti-reflective layer, hard mask layer, and etch stop layer are then partially etched according to a pattern to create an anti-reflective layer pattern, hard mask layer pattern, and etch stop layer pattern. The anti-reflective layer can be formed of a porous plasma silicon oxinitride layer to keep irregular reflections to a minimum. The anti-reflective layer pattern is then etched, followed by an etching of the first conductive layer to form a gate electrode under the etch stop layer pattern. A conformal spacer insulating layer is formed on the whole surface of the semiconductor substrate, and an interlayer insulating layer is formed on the spacer insulating layer so as to fill openings between the gate electrodes.

Abstract: A method is provided for manufacturing Cu interconnects without sputtering freed Cu onto dielectric material and without additional costly process steps. Embodiments include forming a nitride layer cap layer on an underlying conductive feature, such as a Cu feature, forming a dielectric insulating layer, such as a silicon dioxide layer, on the nitride cap layer, and etching in a conventional manner to form a through hole exposing the cap layer above the Cu feature. A metal barrier layer is formed on the sidewalls of the through hole, as by physical vapor deposition (PVD), and the nitride cap layer is etched along with the barrier layer, as by anisotropic etching, to expose the Cu feature. A metal, such as Cu, is then plated, as by electroplating or electroless plating, on the exposed Cu feature and on the barrier layer and filling the through hole.

Abstract: A method for forming the storage node of a capacitor which simplifies its process, and improves the electrical characteristics of semiconductor products by forming the storage node of a capacitor with no stepped portion between cell regions and peripheral circuit regions necessary for memory storage of semiconductor products of the next generation to which a fine line width is applied, and, at the same time, forming a guard ring for dividing the cell regions and the peripheral circuit regions.

Abstract: A silicon carbide via mask/ARC is formed in implementing trench first-via last dual damascene techniques with an attendant improvement in dimensional accuracy and increased efficiency. Embodiments include forming a silicon carbide mask having an extinction coefficient (k) of about −0.2 to about −0.5 on a first dielectric layer overlying a metal feature, depositing a second dielectric layer, etching a trench in the second dielectric layer stopping on the silicon carbide via mask and then etching a via in the first dielectric layer. Embodiments further include Cu and Cu alloy dual damascene methodology.

Abstract: An interconnect structure and method of forming the same in which a diffusion barrier/etch stop layer is deposited over a conductive layer. An organic low k dielectric material is deposited over the diffusin barrier/etch stop layer to form a first dielectric layer. The first dielectric layer is etched to form a slot via in the first dielectric layer. An inorganic low k dielectric material is deposited within the slot via and over the first dielectric layer to form a second dielectric layer over the slot via and the first dielectric layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. The trench extends in a direction that is normal to the length of the slot via. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.

Abstract: Precisely forming a fine resist pattern on a stopper film of silicon nitride, in a method of manufacturing a multi-layer interconnection structure which uses the stopper film.

Abstract: A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. Another method of forming the stack includes forming a pad oxide layer on the semiconductor substrate assembly. A first oxidation diffusion barrier layer is then formed on the pad oxide layer, an inorganic antireflective material layer is formed on the first oxidation diffusion barrier layer, and a second oxidation diffusion barrier layer is formed on the inorganic antireflective material layer.

Abstract: A method and system for providing a semiconductor device is disclosed. The method and system include depositing an antireflective coating (ARC) layer having antireflective properties. The method and system also include depositing a capping layer on the ARC layer. The capping layer reduces a susceptibility of the ARC layer to removal while allowing the ARC layer to substantially retain the antireflective properties.

Abstract: A method for forming a line of a semiconductor device is provided, which improves the life span of the line and its reliability by improving resistance to electromigration (EM).

Abstract: A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.

Abstract: Silicon oxynitride layers are deposited by plasma enhanced chemical vapor deposition with significantly reduced defects, such as nodules, employing a ramp down step at the end of the deposition cycle. Embodiments include depositing a SION ARC at a first power, discontinuing the flow of SiH4 and ramping down to a second power while continuing the flow of N2O and N2, and ramping down to a third power while continuing the flow of N20 and N2 before pumping down. The resulting relatively defect free silicon oxynitride layers can be advantageously employed as an ARC, particularly when patterning contact holes in manufacturing flash memory devices.

Abstract: A semiconductor devices includes an anti-reflective structure for use in patterning metal layers in semiconductor devices. The anti-reflective structure is made, at least in part, using indium tin oxide. The anti-reflective structure is especially useful for patterning the metal layers with light having a wavelength of 190-300 nm. The anti-reflective structure may be a single indium tin oxide layer or may include a titanium nitride layer formed over the metal layer and an indium tin oxide layer formed over the titanium nitride layer. For many applications, the anti-reflective structure, in the presence of a photoresist layer, has a reflectivity of about 3% or less for light having a wavelength of 190-300 nm.

Abstract: In a method of manufacturing a contact element, provision is made of a laminated body which has an insulating film, an electrically conductive layer stacked on the insulating film, and bump holes opened. A treatment is carried out so as to removen organic materials and the like from an interior of the bump holes and/or a surface of the insulating film before bumps are formed on the bump holes. The treatment may be a plasma treatment or an X-ray irradiation.

Abstract: A method is described for forming a patterned polysilicon, amorphous, or single crystal silicon layer. The method comprises forming a consumable mask (50, 60) that is simultaneously removed while etching the underlying film (30).

Abstract: This marking method is carried out with an object to form a mark of high visibility on a surface of a metallic layer of such as a cover plate of a semiconductor device or the like without generating metallic debris or the like. According to this method, on a marking area of a metallic layer with a matte surface (Rmax: 0.5 to 5 &mgr;m), a laser beam is illuminated, thereby the metallic layer is melted, then re-solidified, thereby minute unevenness on the surface of the metallic layer is averaged and erased to be smooth. Thus formed marking portion reflects light specularly and is different in light reflectivity from an underlying portion which scatters light (diffuse reflection). Due to the difference of reflectivity, the marking portion can be visually discerned with excellency.

Abstract: A method for forming a resist pattern includes the steps of: forming an underlayer transparent film on a semiconductor substrate; forming a resist film on the transparent film to a thickness set to be m·&lgr;/2n2, where &lgr; is an exposure wavelength, n2 is a refractive index of the resist film, and m is an integer from 5 to 30; applying a water-soluble antireflection film on the resist film to a thickness set to be &lgr;/4n1, where n1 is a refractive index of the antireflection film; and exposing the resist film from above the antireflection film by a beam having a wavelength &lgr; and developing the resist film as well as removing the antireflection film.