Selective Deposition Patents (Class 438/641)
  • Patent number: 9209072
    Abstract: Methods of fabricating a semiconductor device are described. The method includes forming a patterned oxide layer having a plurality of openings over a substrate, depositing a metal layer in the openings to form metal plugs, depositing a global transformable (GT) layer on the oxide layer and the metal plugs, and depositing a capping layer directly on the GT layer without exposing the GT layer to ambient air. The GT layer on the oxide layer transforms into a dielectric oxide and the GT layer on the metal plugs remains conductive during deposition of the capping layer.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ya-Lien Lee
  • Publication number: 20150084201
    Abstract: A method of making a multi-level micro-wire structure includes imprinting first micro-channels in a curable first layer over a substrate, curing the first layer, and locating and curing a curable conductive ink in the first micro-channels to form first micro-wires. Multi-level second micro-channels are imprinted in a curable second layer in contact with the first layer with a multi-level stamp, the second layer is cured, and a curable conductive ink is located and cured in the multi-level second micro-channels to form multi-level second micro-wires. At least one of the multi-level second micro-channels contacts at least one first micro-wire. A multi-level second micro-wire in at least one of the multi-level second micro-channels is in electrical contact with at least one first micro-wire.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Inventor: RONALD STEVEN COK
  • Publication number: 20150084200
    Abstract: A method of making a multi-level micro-wire structure includes imprinting first micro-channels in a curable first layer over a substrate with a first stamp, curing the first layer, and locating and curing a curable conductive ink in the first micro-channels to form first micro-wires. Second micro-channels are imprinted in a curable second layer in contact with the first layer with a second stamp, the second layer is cured, and a curable conductive ink is located and cured in the second micro-channels to form second micro-wires. At least one of the second micro-channels contacts at least one first micro-wire and a second micro-wire in at least one of the second micro-channels is in electrical contact with at least one first micro-wire.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Inventor: RONALD STEVEN COK
  • Publication number: 20150087146
    Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.
    Type: Application
    Filed: December 1, 2014
    Publication date: March 26, 2015
    Inventors: Chang Myung Ryu, Kimitaka Endo, Belgacem Haba, Yoichi Kubota
  • Patent number: 8987133
    Abstract: A vertical stack including a dielectric hard mask layer and a titanium nitride layer is formed over an interconnect-level dielectric material layer such as an organosilicate glass layer. The titanium nitride layer may be partially or fully converted into a titanium oxynitride layer, which is subsequently patterned with a first pattern. Alternately, the titanium nitride layer, with or without a titanium oxynitride layer thereupon, may be patterned with a line pattern, and physically exposed surface portions of the titanium nitride layer may be converted into titanium oxynitride. Titanium oxynitride provides etch resistance during transfer of a combined first and second pattern, but can be readily removed by a wet etch without causing surface damages to copper surfaces. A chamfer may be formed in the interconnect-level dielectric material layer by an anisotropic etch that employs any remnant portion of titanium nitride as an etch mask.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Son V. Nguyen, Tuan A. Vo, Christopher J. Waskiewicz
  • Patent number: 8975180
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: March 10, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Thomas R. Boussie, David E. Lazovsky, Sandra G. Malhotra
  • Publication number: 20150044866
    Abstract: Method for producing a microelectronic device formed from a stack of supports (W) each provided with one or more electronic components (C) and comprising a conductive structure (170, 470) formed from a first blind conductive via (171b, 472) and a second blind conductive via (171a, 473) with a greater height, the first via and the second via being connected together.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 12, 2015
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Christophe BOUVIER, Gabriel PARES
  • Patent number: 8951814
    Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: February 10, 2015
    Assignee: NVIDIA Corporation
    Inventors: Brian S. Schieck, Howard Lee Marks
  • Patent number: 8951900
    Abstract: The present disclosure is directed to, among other things, an illustrative method that includes forming an opening in a dielectric material of a contact level of a semiconductor device, and selectively depositing a conductive material in the opening to form a contact element therein, the contact element extending to a contact area of a circuit element and having a laterally restricted excess portion formed outside of the opening and above the dielectric material. The disclosed method further includes forming a sacrificial material layer above the dielectric material and the contact element, the sacrificial material layer surrounding the laterally restricted excess portion. Additionally, the method includes planarizing a surface topography of the contact level in the presence of the sacrificial material so as to remove the laterally restricted excess portion from above the dielectric material.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: February 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Axel Preusse, Norbert Schroeder, Uwe Stoeckgen
  • Patent number: 8940633
    Abstract: One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable material on the exposed gate structure, converting at least a portion of the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to the source/drain region. A novel transistor device disclosed herein includes an oxide material positioned between a conductive contact and a gate structure of the transistor, wherein the oxide material contacts the conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiuyu Cai, Ruilong Xie, John A. Iacoponi
  • Publication number: 20150004782
    Abstract: A semiconductor device in which misalignment does not cause short-circuiting and inter-wiring capacitance is decreased. Plural wirings are provided in a first interlayer insulating layer. An air gap is made between at least one pair of wirings in the layer. A second interlayer insulating layer lies over the wirings and first interlayer insulating layer. The first bottom face of the second interlayer insulating layer is exposed to the air gap. When a pair of adjacent wirings whose distance is shortest are first wirings, the upper ends of the first interlayer insulating layer between the first wirings are in contact with the first wirings' side faces. The first bottom face is below the first wirings' upper faces. b/a?0.5 holds where a represents the distance between the first wirings and b represents the width of the portion of the first interlayer insulating layer in contact with the first bottom face.
    Type: Application
    Filed: September 18, 2014
    Publication date: January 1, 2015
    Applicant: Renesas Electronics Corporatiom
    Inventor: Daisuke OSHIDA
  • Publication number: 20140332963
    Abstract: An electronic interconnect structure having a hybridized metal structure near regions of high operating temperature on an integrated circuit, and methods of making the same. The hybridized metal structure features at least two different metals in a single metallization level. The first metal is in a region of high operating temperature and the second region is in a region of normal operating temperatures. In a preferred embodiment the first metal includes aluminum and is in a first level metallization over an active area of the device while the second metal includes copper. In some embodiments, the first and second metals are not in direct physical contact. In other embodiments the first and second metals physically contact each other. In a preferred embodiment, a top surface of the first metal is not co-planar with a top surface of the second metal, despite being in the same metallization level.
    Type: Application
    Filed: May 9, 2013
    Publication date: November 13, 2014
    Applicant: International Business Machines Corporation
    Inventors: Ronald G. Filippi, Erdem Kaltalioglu, Ping-Chuan Wang, Lijuan Zhang
  • Patent number: 8828863
    Abstract: A method for providing metal filled features in a layer is provided. A nonconformal metal seed layer is deposited on tops, sidewalls, and bottoms of the features, wherein more seed layer is deposited on tops and bottoms of features than sidewalls. The metal seed layer are etched back on tops, sidewalls, and bottoms of the features, wherein some metal seed layer remains on tops and bottoms of the features. Deposition on the seed layer on tops of the features is suppressed. An electroless “bottom up” deposition of metal is provided to fill the features.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: September 9, 2014
    Assignee: Lam Research Corporation
    Inventors: William T. Lee, Xiaomin Bin
  • Patent number: 8772155
    Abstract: High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to close off the trench at the top during filling may be reduced in some embodiments. Material that encourages the growth of metal may be formed in the trench at the bottom, while leaving the region of the trench near the top free of such material to encourage growth upwardly from the bottom.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Shai Haimson, Avi Rozenblat, Dror Horvitz, Maor Rotlain, Rotem Drori
  • Patent number: 8709943
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: April 29, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Thomas R. Boussie, David E. Lazovsky, Sandra G. Malhotra
  • Publication number: 20140080258
    Abstract: A method of making a package for a semiconductor device having electrical terminals. At least one semiconductor device is located on a substrate. A first dielectric layer is printed on at least a portion of the semiconductor device to include first recesses aligned with a plurality of the electrical terminals. A conductive material is deposited in the first recesses forming contact members. A second dielectric layer is printed on at least a portion of the first dielectric layer to include second recesses aligned with a plurality of the first recesses. A conductive material is deposited in at least a portion of the second recesses to include a circuit geometry and a plurality of exposed terminals. A compliant material is deposited in recesses in one or more of the first and second dielectric layers adjacent to a plurality of the exposed terminals.
    Type: Application
    Filed: November 21, 2013
    Publication date: March 20, 2014
    Applicant: HSIO TECHNOLOGIES, LLC
    Inventor: JAMES RATHBURN
  • Publication number: 20140080300
    Abstract: An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.
    Type: Application
    Filed: November 15, 2013
    Publication date: March 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sungjun Chun, Anand Haridass, Roger D. Weekly
  • Patent number: 8647982
    Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: February 11, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, James M. Wark, William M. Hiatt
  • Patent number: 8592312
    Abstract: In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The applied voltage increases the selectivity of the deposition process used, thereby preventing the conductive capping layer from causing a short between the metal lines. The conductive capping layer may be deposited through electroplating, electrolessly, by atomic layer deposition (ALD), or by chemical vapor deposition (CVD), for example. In one embodiment, the present method is utilized to fabricate a semiconductor wafer. In one embodiment, the metal lines comprise copper lines, while the conductive capping layer may comprise tantalum or cobalt. The present method enables deposition of a capping layer having high electromigration resistance.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: November 26, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: E. Todd Ryan, John A. Iacoponi
  • Patent number: 8586471
    Abstract: A method is disclosed for depositing multiple seed layers for metallic interconnects over a substrate, the substrate includes a patterned insulating layer which comprises an opening surrounded by a field, said opening has sidewalls and top corners, and the method including: depositing a continuous seed layer over the sidewalls, using a first set of deposition parameters; and depositing another seed layer over the substrate, including inside the opening and over a portion of said field, using a second set of deposition parameters, wherein: the second set of deposition parameters includes one deposition parameter which is different from any parameters in the first set, or whose value is different in the first and second sets; the continuous seed layer has a thickness in a range from about 20 ? to not more than 250 ? over the field; and the combined seed layers leave sufficient room for electroplating inside the opening.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: November 19, 2013
    Inventor: Uri Cohen
  • Patent number: 8492273
    Abstract: A method is disclosed comprising providing a substrate comprising an insulating material and a second semiconductor material and pre-treating the substrate with a plasma produced from a gas selected from the group consisting of a carbon-containing gas, a halogen-containing gas, and a carbon-and-halogen containing gas. The method further comprises depositing a first semiconductor material on the pre-treated substrate by chemical vapor deposition, where the first semiconductor material is selectively deposited on the second semiconductor material. The method may be used to manufacture a semiconducting device, such as a microelectromechanical system device, or to manufacture a semiconducting device feature, such as an interconnect.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: July 23, 2013
    Assignee: IMEC
    Inventors: George Bryce, Simone Severi, Peter Verheyen
  • Patent number: 8481417
    Abstract: Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 8461044
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: June 11, 2013
    Assignee: Intermolecular, Inc.
    Inventors: David E. Lazovsky, Sandra G. Malhotra, Thomas R. Boussie
  • Patent number: 8450197
    Abstract: Contact elements in the contact level of a semiconductor device may be formed on the basis of a selective deposition technique, such as electroless plating, wherein an efficient planarization of the contact level is achieved without subjecting the contact elements to undue mechanical stress. In some illustrative embodiments, an overfilling of the contact openings may be reliably avoided and the planarization of the surface topography is accomplished on the basis of a non-critical polishing process. In other cases, electrochemical etch techniques are applied in combination with a conductive sacrificial current distribution layer in order to remove any excess material of the contact elements without inducing undue mechanical stress.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: May 28, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Axel Preusse, Norbert Schroeder, Uwe Stoeckgen
  • Patent number: 8404582
    Abstract: Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: March 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: David V Horak, Takeshi Nogami, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8389401
    Abstract: When forming contact levels of sophisticated semiconductor devices, a superior bottom to top fill behavior may be accomplished by applying an activation material selectively in the lower part of the contact openings and using a selective deposition technique. Consequently, deposition-related irregularities, such as voids, may be efficiently suppressed even for high aspect ratio contact openings.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: March 5, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Robert Seidel, Markus Nopper, Axel Preusse
  • Patent number: 8344513
    Abstract: A system and a method for protecting through-silicon vias (TSVs) is disclosed. An embodiment comprises forming an opening in a substrate. A liner is formed in the opening and a barrier layer comprising carbon or fluorine is formed along the sidewalls and bottom of the opening. A seed layer is formed over the barrier layer, and the TSV opening is filled with a conductive filler. Another embodiment includes a barrier layer formed using atomic layer deposition.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: January 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
  • Patent number: 8330275
    Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Patent number: 8318553
    Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: November 27, 2012
    Assignee: Infineon Technologies AG
    Inventors: Christian Russ, Christian Pacha, Snezana Jenei, Klaus Schruefer
  • Patent number: 8293647
    Abstract: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. One embodiment provides a method provides a method for processing a substrate comprising forming a seed layer over a substrate having trench or via structures formed therein, coating a portion of the seed layer with an organic passivation film, and immersing the trench or via structures in a plating solution to deposit a conductive material over the seed layer not covered by the organic passivation film.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: October 23, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Jenn-Yue Wang, Hua Chung, Rong Tao, Hong Zhang
  • Patent number: 8236691
    Abstract: A method of plug fill for high aspect ratio plugs wherein a nucleation layer is formed at a bottom of a via and not on the sidewalls. The plug fill is in the direction from bottom to top of the via and not inwards from the sidewalls. The resulting plug is voidless and seamless.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: August 7, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Yakov Shor, Semeon Altshuler, Maor Rotlain, Yigal Alon, Dror Horvitz
  • Patent number: 8211794
    Abstract: In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of fabricating a diffusion barrier can include providing a dielectric layer, forming a first silicon enriched layer over the dielectric layer by exposing the dielectric layer to a silicon-containing ambient, and forming a barrier layer over the first silicon enriched layer.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: July 3, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Valli Arunachalam, Satyavolu Srinivas Papa Rao, Sanjeev Aggarwal, Stephan Grunow
  • Patent number: 8207044
    Abstract: Methods of fabricating an oxide layer on a semiconductor substrate are provided herein. The oxide layer may be formed over an entire structure disposed on the substrate, or selectively formed on a non-metal containing layer with little or no oxidation of an exposed metal-containing layer. The methods disclosed herein may be performed in a variety of process chambers, including but not limited to decoupled plasma oxidation chambers, rapid and/or remote plasma oxidation chambers, and/or plasma immersion ion implantation chambers. In some embodiments, a method may include providing a substrate comprising a metal-containing layer and non-metal containing layer; and forming an oxide layer on an exposed surface of the non-metal containing layer by exposing the substrate to a plasma formed from a process gas comprising a hydrogen-containing gas, an oxygen-containing gas, and at least one of a supplemental oxygen-containing gas or a nitrogen-containing gas.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: June 26, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Rajesh Mani, Norman Tam, Timothy W. Weidman, Yoshitaka Yokota
  • Patent number: 8193090
    Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: June 5, 2012
    Assignee: Intermolecular, Inc.
    Inventors: David E. Lazovsky, Sandra G. Malhotra, Thomas R. Boussie
  • Publication number: 20120126409
    Abstract: A method is disclosed for depositing multiple seed layers for metallic interconnects over a substrate, the substrate includes a patterned insulating layer which comprises an opening surrounded by a field, said opening has sidewalls and top corners, and the method including: depositing a continuous seed layer over the sidewalls, using a first set of deposition parameters; and depositing another seed layer over the substrate, including inside the at least one opening and over a portion of said field, using a second set of deposition parameters, wherein: the second set of deposition parameters includes one deposition parameter which is different from any parameters in the first set, or whose value is different in the first and second sets; the continuous seed layer has a thickness in a range from about 20 ? to not more than 250 ? over the field; and the combined seed layers leave sufficient room for electroplating inside the opening.
    Type: Application
    Filed: January 17, 2012
    Publication date: May 24, 2012
    Applicant: SEED LAYERS TECHNOLOGY, LLC
    Inventor: URI COHEN
  • Patent number: 8178439
    Abstract: A method is provided for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a planarized patterned substrate containing metal surfaces and dielectric layer surfaces with a residue formed thereon, removing the residue from the planarized patterned substrate, and depositing metal-containing cap layers selectively on the metal surfaces by exposing the dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor. The removing includes treating the planarized patterned substrate containing the residue with a reactant gas containing a hydrophobic functional group, and exposing the treated planarized patterned substrate to a reducing gas.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: May 15, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhito Tohnoe, Frank M. Cerio, Jr.
  • Patent number: 8119525
    Abstract: Methods of controlling deposition of metal on field regions of a substrate in an electroplating process are provided. In one aspect, a dielectric layer is deposited under plasma on the field region of a patterned substrate, leaving a conductive surface exposed in the openings. Electroplating on the field region is reduced or eliminated, resulting in void-free features and minimal excess plating. In another aspect, a resistive layer, which may be a metal, is used in place of the dielectric. In a further aspect, the surface of the conductive field region is modified to change its chemical potential relative to the sidewalls and bottoms of the openings.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: February 21, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Jick M. Yu, Wei D. Wang, Rongjun Wang, Hua Chung
  • Publication number: 20110284996
    Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 2N or more interconnects are successively arrayed so that correlation coefficients of line edge roughness (LER) between both side surfaces of the respective interconnects are positive, where N is an integer of 4 or more.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 24, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi Kurusu, Takashi Izumida, Hiroyoshi Tanimoto, Nobutoshi Aoki
  • Patent number: 8053356
    Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: November 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Patent number: 8039966
    Abstract: A structure, tool and method for forming in-situ metallic/dielectric caps for interconnects. The method includes forming wire embedded in a dielectric layer on a semiconductor substrate, the wire comprising a copper core and an electrically conductive liner on sidewalls and a bottom of the copper core, a top surface of the wire coplanar with a top surface of the dielectric layer; forming a metal cap on an entire top surface of the copper core; without exposing the substrate to oxygen, forming a dielectric cap over the metal cap, any exposed portions of the liner, and the dielectric layer; and wherein the dielectric cap is an oxygen diffusion barrier and contains no oxygen atoms.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Chao-Kun Hu
  • Patent number: 8012875
    Abstract: In some embodiments, a workpiece-surface-influencing device preferentially contacts the top surface of the workpiece, to chemically modify the surface at desired field areas of the workpiece without affecting the surfaces of cavities or recesses in the field areas. The device includes a substance which is chemically reactive with material forming the workpiece surface. The substance can be in the form of a thin film or coating which contacts the surface of the workpiece to chemically modify that surface. The workpiece-surface-influencing device can be in the form of a solid state applicator such as a roller or a semi-permeable membrane. In some other embodiments, the cavities are filled with material that prevents surface modification of the cavity surfaces while allowing modification of the field areas, or which encourages surface modification of the cavity surfaces while preventing modification of the field areas. The modified surface facilitates selective deposition of materials on the workpiece.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: September 6, 2011
    Assignee: IPGRIP, LLC
    Inventor: Vladislav Vasilev
  • Patent number: 8004087
    Abstract: A multilayered wiring is formed in a prescribed area in an insulating film that is formed on a semiconductor substrate. Dual damascene wiring that is positioned on at least one layer of the multilayered wiring is composed of an alloy having copper as a principal component. The concentration of at least one metallic element contained in the alloy as an added component in vias of the dual damascene wiring is determined according to the differences in the width of the wiring of an upper layer where the vias are connected. Specifically, a larger wiring width in the upper layer corresponds to a higher concentration of at least one metallic element within the connected vias. Accordingly, increases in the resistance of the wiring are minimized, the incidence of stress-induced voids is reduced, and reliability can be improved.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: August 23, 2011
    Assignee: NEC Corporation
    Inventors: Mari Amano, Munehiro Tada, Naoya Furutake, Yoshihiro Hayashi
  • Patent number: 7989342
    Abstract: The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: August 2, 2011
    Inventors: Joaquin Torres, Laurent Gosset, Sonarith Chhun, Vincent Arnal
  • Patent number: 7989362
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The hafnium lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a hafnium lanthanide oxynitride film.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: August 2, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Patent number: 7960274
    Abstract: A reliable and mechanical strong interconnect structure is provided that does not include gouging features in the bottom of the an opening, particularly at a via bottom. Instead, the interconnect structures of the present invention utilize a Co-containing buffer layer that is selectively deposited on exposed surfaces of the conductive features that are located in a lower interconnect level. The selective deposition is performed through at least one opening that is present in a dielectric material of an upper interconnect level. The selective deposition is performed by electroplating or electroless plating. The Co-containing buffer layer comprises Co and at least one of P and B. W may optionally be also present in the Co-containing buffer layer.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Oscar Van Der Straten
  • Patent number: 7955883
    Abstract: Interdigitated electrode arrays are very promising devices for multi-parameter (bio)sensing, for example the label-free detection of nucleic acid hybridization for diagnostic applications. The current disclosure provides an innovative method for the affordable manufacturing of polymer-based arrays of interdigitated electrodes with ?m-dimensions. The method is based on a combination of an appropriate three-dimensional structure and a single and directional deposition of conductive material. The three-dimensional structure can be realized in a polymer material using a molding step, for which the molds are manufactured by electroplating as a reverse copy of a silicon master structure. In order to ensure sufficient electrical isolation and individual, but convenient, accessibility of the sensors in the array, the interdigitated electrode regions need to be complemented with specific features on the three-dimensional structure. Combined with the use of e.g.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: June 7, 2011
    Assignees: IMEC, Innogenetics
    Inventors: Wim Laureyn, Jan Suls, Paul Jacobs
  • Patent number: 7884018
    Abstract: A method of forming a noble metal cap on a conductive material embedded in a dielectric material in an interconnect structure. The method includes the step of contacting (i) a conductive material having a bare upper surface partially embedded in a dielectric material and (ii) vapor of a noble metal containing compound, in the presence of carbon monoxide and a carrier gas. The contacting step is carried out at a temperature, pressure and for a length of time sufficient to produce a noble metal cap disposed directly on the upper surface of the conductive material without substantially extending into upper surface of the dielectric material or leaving a noble metal residue onto the dielectric material.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: February 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Fenton R. McFeely, Chih-Chao Yang
  • Patent number: 7867886
    Abstract: A method, in a complementary metal oxide semiconductor fabrication process, of creating a layered housing containing a micro-electromechanical system device, the method comprising the steps of providing a cavity in at least one layer of the housing, the cavity being accessible through via holes in a layer of insulating material deposited thereon, and the layer of insulating material being covered by a thin film layer of conductive material. The method further comprises the step of hydrophobically treating at least a portion of the inner surface of the cavity. Finally the method comprises the steps of submerging the wafer in an electroplating solution and electroplating a conductive layer onto the thin film layer of conductive material such that the cavity remains free of electroplating solution.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: January 11, 2011
    Assignee: Cavendish Kinetics, Ltd
    Inventors: Charles Gordon Smith, Robertus P. Van Kampen
  • Patent number: 7863183
    Abstract: The present invention relates to a method for fabricating a semiconductor device with a last level copper-to-C4 connection that is essentially free of aluminum. Specifically, the last level copper-to-C4 connection comprises an interfacial cap structure containing CoWP, NiMoP, NiMoB, NiReP, NiWP, and combinations thereof. Preferably, the interfacial cap structure comprises at least one CoWP layer. Such a CoWP layer can be readily formed over a last level copper interconnect by a selective electroless plating process.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, William F. Landers, Donna S. Zupanski-Nielsen
  • Patent number: 7834458
    Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: November 16, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang