Abstract: A via hole 18 is opened in an interlayer insulating film 17, which covers a lower layer interconnect 12, a protective film 19 is embedded on the base portion of the via hole 18, and a soluble resin 20, which dissolves in a resist developing fluid under unexposed conditions, is further embedded thereupon. On this basis, a photoresist 21 is applied, and this photoresist 21 is subjected to an exposure and a development process so as to form a resist pattern 21a, which has an aperture window in a region including the via hole. Upon formation of an interconnective trench in the interlayer insulating film 17 utilizing the resist pattern 21a, a dual damascene structure is formed by embedding a metallic material into the vial hole and interconnective trench.

Abstract: A method of manufacturing a semiconductor device comprising the steps of forming an insulating layer on a silicon substrate, forming a contact hole on the insulating layer, forming a silicon layer on the surface of the contact hole, and forming a selective conductive plug in the contact hole having the silicon layer.

Abstract: The present invention provides a semiconductor manufacturing apparatus capable of shortening TAT by completing a plurality of processes including plating, annealing, and CMP-in-twice or the like in copper wiring process in a single manufacturing apparatus, and is also capable of suppressing costs for consumable materials by replacing the CMP step with other step. The apparatus of the present invention comprises an electrolytic plating chamber (11) for performing electrolytic plating of a substrate (91), an electrolytic polishing chamber (21) for performing electrolytic polishing of the substrate, and a conveying chamber (81) having installed therein a conveying instrument (83) responsible for loading/unloading of the substrate to or from the electrolytic plating chamber, and to or from he electrolytic polishing chamber, and is connected respectively to the electrolytic plating chamber and the electrolytic polishing chamber.

Abstract: A method for forming a metallization layer. A first layer is formed outwardly from a semiconductor substrate. Contact vias are formed through the first layer to the semiconductor substrate. A second layer is formed outwardly from the first layer. Portions of the second layer are selectively removed such that the remaining portion of the second layer defines the layout of the metallization layer and the contact vias. The first and second layers are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer. Further, metal ions deposited on the first layer during a positive duty cycle are removed from the first layer during a negative duty cycle. Finally, exposed portions of the first layer are selectively removed.

Abstract: The present invention relates to a method for forming a landing plug capable of securing a low resistance by employing a selective epitaxial growth technique to meet demands of high-integration and high-speed in a semiconductor device. The method includes the steps of: forming an inter-layer insulation layer on a substrate; forming a contact hole by etching the inter-layer insulation layer until exposing a partial portion of the substrate; forming a first conductive layer with a predetermined thickness inside of the contact hole, the first conductive layer being made of a silicon layer; forming a second conductive layer on the inter-layer insulation layer in such a manner of being buried into the contact hole in which the silicon layer is formed; and performing a blanket etch process to the second conductive layer until exposing surfaces of the inter-layer insulation layer and the hard mask so that a landing plug is formed.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flows include alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.

Abstract: Adjacent metal lines of an interconnect metallization layer exhibit reduced variation in parasitic capacitance due to the presence of an intervening third metal line. The third metal line is electrically linked to one of the adjacent metal lines and is designed to project into the space between the adjacent metal lines, thereby elevating parasitic capacitance while reducing the range of variation of parasitic capacitance over a known range of critical dimensions. Thickness of the interlayer dielectric formed over the adjacent metal lines can be tailored to trigger penetration of the third metal line within a known range of critical dimensions.

Abstract: This invention includes a step of forming the first substrate which has a semiconductor region and an insulating region on its surface and a step of coating the first substrate with a single-crystal semiconductor layer. In the coating step, a single-crystal semiconductor is longitudinally grown in the semiconductor region and then laterally grown to manufacture a substrate.

Abstract: An electroplating system is described which provides for the formation of a conductive layer on a workpiece. The current used to electroplate the workpiece is controlled by a controller. The rotation of the workpiece within a solution containing conductive material is controlled by a rotation controller. The current level and/or rotation of the workpiece is controlled in such a way that the non-uniform growth of large grains within the conductive film is minimized.

Abstract: An aluminum wiring is selectively formed within a contact hole or groove of a substrate. An intermediate layer which includes nitrogen is formed over the main surface of a substrate and over the interior surface of the contact hole or groove. A first surface portion of the intermediate layer which is located over the main surface of the substrate is treated with a plasma to form a passivity layer at the first surface portion of the intermediate layer. Then, without an intervening vacuum break, an aluminum film is CAD deposited only over a second surface portion of the intermediate layer which is located over the interior surface of the contact hole or recess. The plasma treatment of the first surface portion of the intermediate layer prevents the CAD deposition of the aluminum film over the first surface portion of the intermediate layer.

Abstract: The present invention relates to a method of forming a multi-layer conductive line in a semiconductor device. A portion of a contact of a lower conductive line is selectively etched by a given thickness. A sacrificial barrier layer is then formed on the etched portion of the lower conductive line. With this structure, oxidization of the lower conductive line or diffusion of the lower conductive line material can be prevented in a subsequent insulating film process. Also, sidewall diffusion of a lower conductive line generating in a process of cleaning a contact region is prevented by the sacrificial barrier layer. Therefore, the leakage current occurring between upper and lower conductive lines can be reduced.

Abstract: A process of providing a semiconductor device with electrical interconnection capability wherein a sacrificial material is introduced into topographical features of the semiconductor device prior to chemical mechanical polishing so that debris formed during chemical mechanical polishing is incapable of falling into topographical features present on the semiconductor device. The sacrificial material is thereupon removed by liquid or supercritical carbon dioxide.

Abstract: High aspect ratio vias formed in a first insulating layer covering a semiconductor substrate (body) are filled with conductors in a manner that both reduces the number of processing steps and allows an alignment tool (stepper) to align to alignment and overlay marks. Sidewalls and a bottom of each via are coated with a composite layer of titanium, titanium nitride, and a chemical vapor deposited seed layer of aluminum. A physical vapor deposited layer of aluminum is then formed while the structure is heated to about 400 degrees C. to completly fill the vias and to overfill same to form a blanket layer of aluminum above the first insulating layer (34). The blanket layer of aluminum is then patterned and portions not covered by the pattern are removed to result in columns of aluminum. A second insulating layer is then formed around the columns of aluminum. The ends of the columns at a top of the second insulating layer lie in a relatively common plane to which steppers can relatively easily align patterns.

Abstract: Introducing at least one metal such as cobalt, molybdenum, metal carbonyl, tungsten, platinum, or other suitable metal to a focused ion beam. Introducing the focused ion beam to a substrate within a processing chamber. Forming at least one layer over a substrate. Applying heat to the layer by, for example, a laser.

Abstract: The present invention is to provide a method for fabricating semiconductor devices capable of eliminating a height difference on a base member caused by a residual plating seed layer remained in a portion where an electrode comes into contact and is thus prevented from contacting with an electrolytic polishing fluid, where such height difference has been a problem in introducing the electrolytic polishing process into wafer process. The method comprises the steps of forming a plating seed layer on the base member; forming by the plating process a plated film on the plating seed layer in an area excluding the outer peripheral portion of the base member; polishing the plated film together with the plating seed layer by the electrolytic polishing process; and selectively removing the plating seed layer remaining on the outer peripheral portion of the base member.

Abstract: A semiconductor chip assembly includes a semiconductor chip, a conductive trace, a connection joint, an insulative adhesive and an encapsulant. The conductive trace includes a routing line and a pillar. The routing line extends within and outside a periphery of the chip, and the pillar is disposed outside the periphery of the chip and extends away from the chip. The connection joint contacts and electrically connects the routing line and the pad. The adhesive is sandwiched between the routing line and the chip and contacts a surface of the routing line that faces away from the chip, thereby interlocking the routing line to the assembly. The encapsulant extends into a channel in the pillar, thereby interlocking the pillar to the assembly.

Abstract: A method for making 0.25 micron semiconductor chips includes using TEOS as the high density plasma (HDP) inter-layer dielectric (ILD). More specifically, after establishing a predetermined aluminum line pattern on a substrate, TEOS is deposited and simultaneously with the TEOS deposition, excess TEOS is etched away, thereby avoiding hydrogen embrittlement of and subsequent void formation in the aluminum lines that could otherwise occur if silane were used as the HDP ILD.

Abstract: A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.

Abstract: A method of manufacturing a semiconductor device comprising the steps of forming an insulating layer on a silicon substrate, forming a contact hole on the insulating layer, forming a silicon layer on the surface of the contact hole, and forming a selective conductive plug in the contact hole having the silicon layer.

Abstract: A method for forming an electronic device, comprising: forming a first conductive or semiconductive layer; forming a sequence of at least on insulating layer and at least one semiconducting layer over the first conductive or semiconductive layer; locally depositing solvents at a localised region of the insulating layer so as to dissolve the sequence of insulating and semiconducting layers in the region to leave a void extending through the sequence of layer; and depositing conductive or semiconductive material in the void.

Abstract: The invention provides a method for fabricating bitlines, including the following steps: providing a semiconductor substrate having a contact opening, which opening exposed a diffusion region in the substrate or a polysilicon layer of a wordline; forming a polysilicon layer to cover the opening and contacting the exposed surface of the diffusion region or the polysilicon layer of the wordline; forming a tungsten silicide layer to cover the polysilicon layer; performing a ion implantation step with high energy and high dosage to damage a contact surface between the bitline and the wordline or a contact surface between the bitline and the diffusion region; forming a better contact surface between the bitline and the wordline or a better contact surface between the bitline and the diffusion region using thermal annealing in the subsequent steps, thereby reducing contact resistance between the bitline and the wordline or between the bitline and the diffusion region.

Abstract: A method of fabricating a semiconductor device having the steps of forming an insulating layer on a silicon substrate; forming a contact hole in the insulating layer so that a portion of the silicon substrate is exposed in the contact hole; performing an interface treatment process to the exposed portion of the silicon substrate, wherein the interface treatment process includes at least a dry cleaning and a hydrogen heat treatment; and forming a selective silicon plug including single crystalline and polycrystalline silicon structures on the exposed portion of the silicon substrate.

Abstract: A method is provided for selectively depositing a silicided metal nitride diffusion barrier layer in a semiconductor structure including providing at least one anisotropically etched opening extending through at least one insulating layer and in closed communication with a metallic underlayer; conformally depositing a metal nitride layer over the at least one anisotropically etched opening under conditions such that the metal nitride layer has a relatively higher deposition rate onto the sidewalls of the at least one anisotropically etched opening for a period of time compared to a deposition rate over the metallic underlayer; and, exposing the metal nitride layer to a silicon containing gaseous ambient under conditions such that silicon is incorporated into the metal nitride layer to form a silicided metal nitride layer.

Abstract: There is disclosed a method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon (SEG) process. The method includes forming a nitride film at a predetermined in a semiconductor substrate region except for the region in which a contact plug will be formed, forming an USG film on the entire surface of the substrate in which the nitride film is formed by chemical enhanced vapor deposition method or a plasma method, etching the USG film by reactive ion etch method to expose the surface of silicon in the structure, and forming a contact plug by performing in-situ process while performing selective epitaxial growth method for the silicon film exposed through the contact hole in the structure.

Abstract: In a copper plating process, a seed layer is uniformly deposited over a surface, including lining a high aspect ratio trench defined by that surface. A mask layer is provided using a process that fails to deposit in the trench. In one exemplary embodiment, the failure is due to the decrease in the isotropic flux of neutrals toward the bottom of the trench. Copper is subsequently electroplated. Because the seed layer is exposed only within the trench, copper deposits only therein. The self-aligned mask prevents plating outside of the trench. A chemical-mechanical planarization step removes the mask and the seed layer extending beyond the trench, leaving a copper structure within the trench. The structure may serve as a conductive line, an interconnect, or a capacitor plate.

Abstract: In but one aspect of the invention, a method of depositing polysilicon comprises providing a substrate within a chemical vapor deposition reactor, with the substrate having an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the crystalline region and not the amorphous region. In another aspect a method of fabricating a field effect transistor on a substrate comprises forming a gate dielectric layer and a gate over semiconductive material. Doped source/drain regions are formed within semiconductive material laterally proximate the gate. Substantially amorphous insulating material is formed over and laterally proximate the gate. The substrate is provided within a chemical vapor deposition reactor.

Abstract: Introducing at least one metal such as cobalt, molybdenum, metal carbonyl, tungsten, platinum, or other suitable metal to a focused ion beam. Introducing the focused ion beam to a substrate within a processing chamber. Forming at least one layer over a substrate. Applying heat to the layer by, for example, a laser.

Abstract: The present invention provides a semiconductor memory device and a method of preventing the contact between a dielectric layer of a capacitor and a diffusion barrier. The plug to be contacted to an electrode of a capacitor, comprises a diffusion barrier layer and a conducting layer. The conducting layer is formed with a material capable of flowing current when the conducting layer is oxidized. Accordingly, it is possible to prevent the dielectric layer being contacted with the diffusion barrier, there by the leakage current may be reduced, and the capacitance of the capacitor may be increased.

Abstract: Disclosed is a method of forming a metal plug which selectively forms the metal plug within a contact hole or a via hole in a simple manner. The method of the invention comprises the following steps of: (a) forming an insulation film having a contact hole on a lower structure, the contact hole exposing the lower structure; (b) forming a diffusion barrier with a uniform thickness on the whole surface of the resultant structure of the (a) step; (c) exposing the resultant structure having the diffusion barrier to an oxygen plasma atmosphere or an ozone plasma atmosphere to form a nucleation-preventing film made of an oxide on the surface of the diffusion barrier outside the contact hole; and (d) depositing a metal only inside the contact hole via a CVD to form the metal plug. According to the present invention, the manufacturing yield is improved whereas the manufacturing cost thereof is saved.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed over a semiconductor substrate and having a conductive feature comprised of tungsten, the method comprising the steps of: forming a nucleation layer over the semiconductor substrate by introducing a combination of WF6, H2 and a plasma; and forming a tungsten layer on the nucleation layer by means of chemical vapor deposition. In an alternative embodiment, an insulating layer is formed on the substrate and situated between the nucleation layer and the substrate. Preferably, this embodiment additionally includes the step of forming a nitrogen-containing layer under the nucleation layer by introducing a combination of WF6, N2, H2, and a plasma. The conductive feature is, preferably, a conductive gate structure, and the insulating layer is, preferably, comprised of: an oxide, a nitride, an insulating material with a dielectric constant substantially higher than that of an oxide, and any combination thereof.

Abstract: Within a method for fabricating a microelectronic fabrication, and a microelectronic fabrication fabricated employing the method, there is first provided a substrate. Within the method, there is then formed over the substrate a patterned bond pad layer. There is also formed over the substrate a patterned passivation layer which passivates a series of edges of the patterned bond pad layer while leaving exposed a central portion of the patterned bond pad layer, where the patterned passivation layer has a series of protrusions within the patterned passivation layer over the series of edges of the patterned bond pad layer. There is then formed over the central portion of the patterned bond pad layer and bridging over the series of protrusions of the patterned passivation layer a first terminal electrode layer having an upper surface which is concave. Finally, there is then formed over the first terminal electrode layer a second terminal electrode layer having an upper surface which is other than concave.

Abstract: A semiconductor processing method of forming an electrically conductive interconnect line having an electrical conductive covering predominately coextensive therewith, includes, a) providing an conductive interconnect line over a first electrically insulating material, the line having a top and sidewalls; b) selectively depositing a second electrically insulating material layer over the interconnect line and the first insulating material in a manner which deposits a greater thickness of the second insulating material atop the interconnect line than a thickness of the second insulating material over the first insulating material; c) anisotropically etching the second insulating material layer inwardly to at least the first insulating material yet leaving second insulating material over the top and the side walls of the interconnect line; and d) providing an electrically conductive layer over the anisotropically etched second insulating layer to form a conductive layer (which is predominately coextensive with t

Abstract: The present invention is directed to a simplified, CVD-less method of forming a barrier layer for a metal layer which prevents metal contamination in an integrated circuit. The invention utilizes a sacrificial multilayer dielectric structure and selective etching to form the top barrier layer. An opening is etched in the structure and a plating layer is deposited in the opening. A first unneeded portion of the structure along with an unneeded portion of the plating layer is removed utilizing an etchant that is selective for the first unneeded structural portion. A Cu layer is deposited and implanted with barrier material to form the top barrier layer. A second unneeded portion of the structure along with an unneeded portion of the top barrier layer is removed utilizing an etchant that is selective for the second unneeded structural portion. The resulting structure is a metal interconnect structure having an overlying top barrier layer which is produced without using CVD techniques.

Abstract: The reliability of in-laid metallization patterns, e.g., of copper or copper alloy, is significantly enhanced by voidlessly filling recesses in a substrate by an electroplating process, wherein “pinching-off” of the recess opening due to formation of overhanging metal deposits as a result of increased rate of electrodeposition thereat is prevented. Embodiments include preliminarily selectively rendering the recess opening surface non-conductive. The inventive method also enables a reduction in electrodeposition over non-recessed areas, thereby reducing the time required for planarization, as by CMP.

Abstract: A processing line includes a deposition tool, a metrology tool, an etch tool, and a process controller. The deposition tool is adapted to form a process layer on a plurality of wafers. The metrology tool is adapted to measure the thickness of the process layer for a sample of the wafers. The etch tool is adapted to etch the process layer in accordance with an operating recipe. The process controller is adapted to store a thickness profile model of the deposition tool, generate predicted process layer thicknesses for the wafers not measured by the metrology tool based on the process layer thickness measurements of the wafers in the sample and the thickness profile model, and modify the operating recipe of the etch tool based on the predicted process layer thicknesses.

Abstract: A method of manufacturing a metal wiring in a semiconductor device is disclosed. The method comprises forming a photosensitive film so that an underlying metal wiring can be exposed, adhering an chemical enhancer only to the underlying metal wiring, depositing a metal layer by CECVD method so that the metal layer is selectively deposited at the portion in which the chemical enhancer is formed, removing the photosensitive film and chemical enhancer, and forming a diffusion barrier layer spacer at the sidewall of the metal layer to form an upper metal wiring. Therefore, the disclosed method can solve poor contact with an underlying metal wiring due to shortage of processional margin in the process of forming an upper metal wiring in a high integration semiconductor device.

Abstract: A film formation method for manufacture of a semiconductor device includes the steps of forming a first metal film as a continuous film on a substrate, forming a second metal film as discontinuous films on the substrate formed with the first metal film, and forming a third metal film by plating on the substrate formed with the first and second metal films.

Abstract: A multiple dielectric device and its method of manufacture overlaying a semiconductor material, comprising a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening, wherein a portion of the opening not filled with the first dielectric layer has an aspect ratio of not greater than about two, and a second dielectric layer over said first dielectric layer. The deposition rates of the first and second dielectric layers may be achieved through changes in process settings, such as temperature, reactor chamber pressure, dopant concentration, flow rate, and a spacing between the shower head and the assembly. The dielectric layer of present invention provides a first layer dielectric having a low deposition rate as a first step, and an efficiently formed second dielectric layer as a second completing step.

Abstract: The present invention is directed to a method for forming semiconductor devices and semiconductor device precursors having gradual slope contacts. The method for forming a semiconductor precursor includes the steps of: forming a layer of conductive material in a first layer; forming a layer of a hard mask material onto at least a portion of the first layer; etching the layer of hard mask material to expose a portion of the first layer; forming facets on the layer of hard mask material; and forming a via in the first layer such that the via extends through the first layer to expose at least a portion of the layer of conductive material.

Abstract: A self-aligned via between interconnect layers in an integrated circuit, and a process for forming such a via which allows a less precise masking alignment to be used to fabricate an integrated circuit with increased packing density.

Abstract: A method is provided for forming conductive layers in semiconductor device channels and vias by using forward current and periodic pulse reverses for filling inward from the sidewalls of the channels and vias. The pulse reversals and inward filling reduce recrystallization rate to improve electromigration resistance and reduce the stress in the conductive layers to eliminate voids.

Abstract: A method for forming conductor members includes a step of coating an organic solvent on a conductive film to form an organic solvent layer, a step of coating a resist material on the organic solvent layer to form a resist layer, a step of patterning the resist layer to form a patterned resist layer, and a step of plating a conductive material using the patterned resist layer to form the conductor members.

Abstract: A method fabricating an interconnect. A sacrificial layer is formed on a substrate. The sacrificial is patterned for form an opening, followed by filling the opening with a metal interconnect. The sacrificial layer is removed, and a barrier layer is formed to cover the metal interconnect and the substrate. The barrier layer is conformal to the surface profile of the substrate having a metal interconnect thereon. A dielectric layer is formed on the barrier layer.

Abstract: A method of manufacturing an interconnection layer for a semiconductor device comprising the steps of forming a conductive pattern near a surface of a semiconductor substrate or on the surface of the semiconductor substrate, forming an insulation layer on a surface of the conductive pattern, forming grooves in the insulation layer exposing portions of the conductive pattern, forming a first barrier layer pattern on an upper surface of the insulation layer and on sidewalls and bottoms of each of the grooves, selectively forming a seed layer on portions of the first barrier layer pattern, selectively forming a copper interconnection layer on the first barrier layer pattern and the seed layer, and forming a second barrier layer on an upper surface and sides of the copper interconnection layer.

Abstract: A method of manufacturing a semiconductor device utilizing a multi-chamber apparatus comprises the steps of forming a metal film on an insulating layer under the lower pressure within a film forming apparatus and reflowing the metal film on the insulating film, after transferring the semiconductor substrate to a reflow apparatus from the film forming apparatus under the vacuum atmosphere of 1.3×10−6 Pa or less, by simultaneously heating a plurality of semiconductor substrates under the vacuum atmosphere of 1.3×10−6 Pa or less.

Abstract: A method for connecting metal structures with self-aligned metal caps, in accordance with the invention, includes providing a metal structure in a first dielectric layer. The metal structure and the first dielectric layer share a substantially planar surface. A cap metal is selectively depositing on the metal structure such that the cap metal is deposited only on the metal structure. A second dielectric layer is formed over the cap metal. The second dielectric layer is opened to form a via terminating in the cap metal. A conductive material is deposited in the via to provide a contact to the metal structure through the cap metal.

Abstract: A process for plating metal in submicron structures. A seedlayer is deposited on surfaces of submicron structures. The seedlayer is annealed at a temperature of about 80° C. to about 130° C. Metal is plated on the seedlayer.

Abstract: A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.

Abstract: A new method of metallization using a three-dimensional aluminum reservoir to increase the electromigration lifetime of a tungsten plug in the fabrication of integrated circuits is achieved. An insulating layer is provided covering semiconductor device structures in and on a semiconductor substrate. Aluminum lines are formed over the insulating layer. An intermetal dielectric layer is deposited overlying the aluminum lines. Via openings are made through the intermetal dielectric layer to the aluminum lines. Aluminum is selectively deposited into the via openings to form aluminum reservoirs in the bottom of the via openings wherein the aluminum does not completely fill the via openings.

Abstract: With a semiconductor device manufacturing method, a lower-layer interconnection is formed on a circuit board on which a plurality of semiconductor chips are mounted. Using a screen plate with openings corresponding to desired positions on the lower-layer interconnection, screen printing of a metal paste is effected, and the printed metal paste is dried and calcined by heat treatment to form a metal pillar on the lower-layer interconnection. An insulating film covering the lower-layer interconnection and the metal pillar is formed so that the tip of the metal pillar may be exposed. An upper-layer interconnection is formed on the insulating film so that this layer may contact with the exposed tip of the metal pillar.