Abstract: In one aspect of the present invention, a method of fabricating a semiconductor device may include forming a sacrificial film on a substrate, forming an insulating film on the sacrificial film, forming a plurality of first openings in the sacrificial film and the insulating film in a first region and a second region, depositing a conductive material in the plurality of the first openings, forming a second opening in the insulating film in the second region so as to expose the sacrificial film, and removing the sacrificial film in the first region via the second opening in the second region.

Abstract: A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.

Abstract: A device isolation film in a semiconductor device and a method for forming the same are provided. The method includes etching a middle portion of a device isolation film having a deposition structure including a Spin-On-Dielectric (SOD) oxide film and a High Density Plasma (HDP) oxide film to form a hole and filling an upper portion of the hole with an oxide film having poor step coverage characteristics to form a second hole extending along the middle portion of the device isolation film. The second hole serves as a buffer for stress generated at the interface between an oxide film, which can be a device isolation film, and a silicon layer, which can be a semiconductor substrate, thereby increasing the operating current of a transistor and improving the electrical characteristics of the resulting device.

Abstract: A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line.

Abstract: According to an aspect of the invention, there is provided a polishing liquid for polishing a barrier metal material on an interlayer insulation material, the polishing liquid having a pH of from 2.0 to 6.0 and including an aqueous solution containing a compound represented by the following formula (1), and polishing particles containing silicon oxide and dispersed in the aqueous solution: R1—(CH2)m—(CHR2)n—COOH (1) wherein m+n?4; R1 represents a hydrogen atom, a methyl group, an ethyl group or a hydroxyl group; R2 represents a methyl group, an ethyl group, a benzene ring or a hydroxyl group; and when a plurality of R2s are present in the formula (1), they are the same or different from one another.

Abstract: By forming a large metal pad and removing any excess material thereof, a pronounced recessed surface topography may be obtained, which may also affect the further formation of a metallization layer of a semiconductor device, thereby increasing the probability of maintaining metal residues above the recessed surface topography. Consequently, by providing test metal lines in the area of the recessed surface topography, the performance of a respective CMP process may be estimated with increased efficiency.

Abstract: A method of forming a metal line in a semiconductor device is disclosed. The method of forming a metal line in a semiconductor device includes forming an interlayer insulating film over a substrate. A via hole may be formed by selectively patterning the interlayer insulating film. A metal film may be formed over a surface of the interlayer insulating film including an inner portion of the via hole. The inner portion of the via hole may be filled with copper. A copper layer exposed over the surface of the interlayer insulating film may be deplated using reverse current to form a copper metal line and a recess region over the copper metal line. An upper insulating film may be formed over the surface of the interlayer insulating film including the recess region by deposition. An insulating cap layer may be selectively formed over only the recess region on the copper metal line by etching the upper insulating film.

Abstract: By introducing an additional heat treatment prior to and/or after contacting a sensitive dielectric material with wet chemical agents, such as an electrolyte solution, enhanced performance with respect to leakage currents or dielectric strength may be accomplished during the fabrication of advanced semiconductor devices. For example, metal cap layers for metal lines may be provided on the basis of electroless deposition techniques, wherein the additional heat treatment(s) may provide the required electrical performance.

Abstract: The instant invention is a process for planarizing a microelectronic substrate with a cross-linked polymer dielectric layer, comprising the steps of: (a) heating such a substrate coated with a layer comprising an uncured cross-linkable polymer and a glass transition suppression modifier to a temperature greater than the glass transition temperature of the layer, the temperature being less than the curing temperature of the uncured cross-linkable polymer to form a substrate coated with a heat flowed layer; and (b) heating the substrate coated with the heat flowed layer to a curing temperature of the uncured cross-linkable polymer of the heated layer to cure the uncured cross-linkable polymer to form a planarized substrate wherein the percent planarization at 100 micrometers is greater than fifty percent. The instant invention is a microelectronic device made using the above-described process.

Abstract: Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 ? to about 50 ? and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water.

Abstract: A fabrication process, including forming one or more layers on at least a sidewall of a topographical feature of a substantially planar substrate, the sidewall being substantially orthogonal to the substrate; and planarizing respective portions of the one or more layers to form a planar surface substantially parallel to the substrate, wherein the planar surface includes respective co-planar surfaces of the one or more layers, at least one of the surfaces having a dimension determined by a thickness of the corresponding layer.

Abstract: A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.

Abstract: The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to be reliably dissipated, and for dendrite formation to be prevented, by a discharge doping region formed in the first and second doping regions.

Abstract: A metal barrier is realized on top of a metal portion of a semiconductor product, by forming a metal layer on the surface of the metal portion, with this metal layer comprising a cobalt-based metal material. Then, after an optional deoxidation step, a silicidation step and a nitridation step of the cobalt-based metal material of the metal layer are performed. The antidiffusion properties of copper atoms (for example) and the antioxidation properties of the metal barrier are improved.

Abstract: A method of fabricating a phase change RAM (PRAM) having a fullerene layer is provided. The method of fabricating the PRAM may include forming a bottom electrode, forming an interlayer dielectric film covering the bottom electrode, and forming a bottom electrode contact hole exposing a portion of the bottom electrode in the interlayer dielectric film, forming a bottom electrode contact plug by filling the bottom electrode contact hole with a plug material, forming a fullerene layer on a region including at least an upper surface of the bottom electrode contact plug and sequentially stacking a phase change layer and an upper electrode on the fullerene layer. The method may further include forming a switching device on a substrate and a bottom electrode connected to the switching device, forming an interlayer dielectric film covering the bottom electrode and forming a bottom electrode contact hole exposing a portion of the bottom electrode in the interlayer dielectric film.

Abstract: In a method of forming a metal line of a semiconductor device, a dielectric film is formed on a semiconductor substrate. A plurality of parallel photoresist patterns are formed over the entire structure including the dielectric film. A spacer is formed on sidewalls of the photoresist patterns. The dielectric film is exposed by removing the photoresist patterns. Damascene patterns are formed by etching the exposed dielectric film. The spacer is removed. Metal material is formed over the entire structure including the damascene patterns and polishing the metal material, thereby forming a metal line.

Abstract: A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily chemical, formed on a conformal tungsten layer. During subsequent CMP to pattern the tungsten layer, upper topological regions of the protective barrier layer (such as those overlying interlevel dielectric regions) are removed first, exposing the tungsten under those regions to removal, while protective barrier layer regions over lower topological regions (such as openings within the interlevel dielectric) remain to prevent chemical attack of underlying tungsten. CMP patterned tungsten is thus substantially planar with the interlevel dielectric without dishing, even in large area tungsten structures such as MOS capacitor structures.

Abstract: An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the overlying line opening, nor does it introduce damages caused by Ar sputtering into the dielectric material including the via and line openings. In accordance with the present invention, such an interconnect structure contains a diffusion barrier layer only within the via opening, but not in the overlying line opening. This feature enhances both mechanical strength and diffusion property around the via opening areas without decreasing volume fraction of conductor inside the line openings.

Abstract: Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further includes (a) a dielectric structure having a plurality of openings with sidewalls projecting from corresponding bond-pads, and (b) a plurality of caps over corresponding bond-pads. The individual caps can include a discrete portion of a barrier layer attached to the bond-pads and the sidewalls of the openings, and a discrete portion of a cap layer on the barrier layer. The caps are electrically isolated from each other and self-aligned with corresponding bond-pads without forming a mask layer over the cap layer.

Abstract: A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises the steps of depositing and patterning a disposable layer, depositing a first barrier layer on top of the patterned disposable layer, depositing a metal layer, planarizing the metal layer, depositing a second barrier layer, planarizing the second barrier layer until substantially no barrier layer material is present on top of the disposable layer, depositing a permeable layer, removing the disposable layer through the permeable layer to form air gaps.

Abstract: A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is conformally deposited over the contact points, and a second material layer is deposited. A photoresist layer is applied and patterned to leave remaining portions. The remaining portions are trimmed to produce trimmed remaining portions which overlie eventual contact holes to the contact points. Using the trimmed remaining portions as an etch mask, exposed portions the second material layer are etched away to leave sacrificial plugs. The sacrificial plugs are etched away to form contact holes that reach portions the first material layers. Another etching step is performed to extend the contact holes to produce final contact holes that extend to the contact points.

Abstract: A method of creating metal caps on copper lines within an inter-line dielectric (ILD) deposits a thin (e.g., 5 nm) metal blanket film (e.g., Ta/TaN) on top the copper lines and dielectric, after the wafer has been planarized. Further a thin dielectric cap is formed over the metal blanket film. A photoresist coating is deposited over the thin dielectric cap and a lithographic exposure process is performed, but without a lithographic mask. A mask is not needed in this situation, because due to the reflectivity difference between copper and the ILD lying under the two thin layers, a mask pattern is automatically formed for etching away the Ta/TaN metal cap between copper lines. Thus, this mask pattern is self-aligned above the copper lines.

Abstract: A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is performed thereon. An intermetallic dielectric layer is applied on the metal line pattern. The first B metal thin layer is removed by a chemical mechanical planarization process to form a first stage metal line. A second aluminum layer and a second metal thin layer are sequentially applied. Photoresist is applied, a photolithography process is performed to form a metal line pattern, and etching is performed to form a second stage metal line. An intermetallic dielectric layer is applied on the second stage metal line. A chemical mechanical planarization process is performed on the second intermetallic dielectric layer.

Abstract: A polishing composition of the present invention, to be used in polishing for forming wiring in a semiconductor device, includes: a specific surfactant; a silicon oxide; at least one selected from the group consisting of carboxylic acid and alpha-amino acid; a corrosion inhibitor; an oxidant; and water. This polishing composition is capable of suppressing the occurrence of the dishing.

Abstract: An interconnect trench is formed on a dielectric layer 12 and a first HSQ layer 14 formed on a semiconductor substrate, and a tantalum family barrier metal layer 24a is formed all over the substrate. Then a seed copper-containing metal layer 60 and a plated copper layer 62 are formed so as to fill a part of the interconnect trench. After that, a bias-sputtered copper-containing metal layer 64 is formed on the plated copper layer 62 so as to fill the remaining portion of the interconnect trench and then heat treatment is performed. As a result, a dissimilar metal contained in the bias-sputtered copper-containing metal layer 64 diffuses uniformly into the plated copper layer 62.

Abstract: In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.

Abstract: Methods of manufacturing semiconductors are disclosed. One example method includes forming a trench through a dual damascene process, depositing a barrier metal layer on the overall surface, and depositing copper in the trench to form a copper line. The example method may also include performing a wet etching process to remove the top portion of the copper line, depositing a barrier layer on the etched copper line, and performing a planarization process to flatten the barrier layer.

Abstract: A silicon-on-insulator (SOI) structure is provided for forming through vias in a silicon wafer carrier structure without backside lithography. The SOI structure includes the silicon wafer carrier structure bonded to a silicon substrate structure with a layer of buried oxide and a layer of nitride lo separating these silicon structures. Vias are formed in the silicon carrier structure and through the oxide layer to the nitride layer and the walls of the via are passivated. The vias are filled with a filler material of either polysilicon or a conductive material. The substrate structure is then etched back to the nitride layer and the nitride layer is etched back to the filler material. Where the filler material is polysilicon, the polysilicon is etched away forming an open via to the top surface of the carrier wafer structure. The via is then backfilled with conductive material.

Abstract: A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed.

Abstract: An integrated circuit and methods for forming the same are provided. The method includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; forming an opening extending from a top surface of the low-k dielectric layer into the low-k dielectric layer; forming a diffusion barrier layer in the opening, wherein the diffusion barrier layer has a top edge substantially level with a top surface of the low-k dielectric layer; filling a metal line in the opening; recessing a top surface of the metal line below a top edge of the diffusion barrier layer to form a recess; and forming a metal cap on the metal line, wherein the metal cap is substantially within the recess.

Abstract: A method for manufacturing a semiconductor device that comprises implanting a first dopant type in a well region of a substrate to form implanted sub-regions that are separated by non-implanted areas of the well region. The method also comprises forming an oxide layer over the well region, such that an oxide-converted first thickness of the implanted sub-regions is greater than an oxide-converted second thickness of the non-implanted areas. The method further comprises removing the oxide layer to form a topography feature on the well region. The topography feature comprises a surface pattern of higher and lower portions. The higher portions correspond to locations of the non-implanted areas and the lower portions correspond to the implanted sub-regions.

Abstract: A method for producing an oxide confined semiconductor laser uses a dual platform to synchronously produce a light emitting active area and a wire bonding area on a semiconductor material and use a metal protective material, an electrically conductive metal material, and a dielectric material together with an etching process, an oxide confined technology, and plating technology to produce the dual platform, an oxide layer, a dielectric layer, a protective layer, and a metal layer. The light emitting active area platform and the wire bonding area platform are independent, and the wire bonding area platform is produced on the semiconductor structure, such that an ion implant process can adjust the capacitance and provide a higher wire bonding strength. Since the electric layer is filled on the external sides of the dual platforms, the wire connected metal capacitance is lowered, and the planarization facilitates the production of the metal layer.

Abstract: A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench formed in the first interlayer insulation film and having a sidewall surface and a bottom surface covered with a first barrier metal film, a via-hole formed in the second interlayer insulation film and having a sidewall surface and a bottom surface covered with a second barrier metal film, an interconnection pattern filling the interconnection trench, and a via-plug filling the via-hole, wherein the via-plug makes a contact with a surface of the interconnection pattern, the interconnection pattern has projections and depressions on the surface, the interconnection pattern containing therein oxygen atoms along a crystal grain boundary extending from the surface toward an interior of the interconnection pattern with a concentration higher than a concentration at the surface.

Abstract: An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

Abstract: A semiconductor device. A dielectric layer is disposed on a substrate having a first region and a second region. A first metal layer and a second layer are embedded in the dielectric layer in the first and second regions, respectively, wherein the first and second metal layers are located at the same level and have different thicknesses. A method for fabricating a semiconductor device is also disclosed.

Abstract: A method of forming a metal line in a semiconductor device includes: forming a lower insulation layer for insulation from the lower substrate; forming a first metal line at a certain region on the lower insulation layer; sequentially forming a first oxide layer, an FSG (Fluorine-doped Silicate Glass) layer, and a second oxide layer on the lower insulation layer and the first metal line; removing the first oxide layer, the FSG layer, and the second oxide layer so as to expose the first metal line; forming an upper insulation layer on the lower insulation layer and the first metal line; forming a contact hole by etching the upper insulation layer to a degree that the first metal line is exposed; and forming a second metal line by depositing a metal material in the contact hole.

Abstract: First material (106) is situated on the surface of a substructure (100 and 102) and in an opening (104), such as a Wench, that extends partway through the substructure. Second material (108) is situated on the first material in the opening. A physical sputter etch is performed on the structure while it is in a sputter etch module (206) to remove the parts of the first material overlying the substructure's surface and situated above the opening and to remove part of the second material overlying the first material in the opening so that remaining parts of the first and second materials are situated in the opening. The so-modified structure is transferred from the sputter etch module under a substantial vacuum, normally via a transfer module (202), to a deposition module (203, 204, or 205) where a layer of third material is deposited over the substructure's surface and over the parts of the first and second materials in the opening.

Abstract: Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a polishing pressures of about 2 psi or less and at platen rotational speeds of about 200 cps or greater. The polishing process may use an abrasive-containing polishing composition having up to about 1 wt. % of abrasives. The polishing process may be integrated into a multi-step polishing process.

Abstract: In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the etching, a circuit component is formed in the first circuitry area and a circuit component is formed in the second circuitry area. Dielectric material is formed over the first and second circuitry areas. The dielectric material comprises a conductive contact extending outwardly from the circuit component in the first circuitry area. The dielectric material has a first outermost surface. A portion of the dielectric material and a portion of the conductive contact are removed to form a second outermost surface of the dielectric material which has greater degree of planarity than did the first outermost surface. Other aspects are contemplated.

Abstract: A method of forming a metal line in a semiconductor device is disclosed. The method of forming a metal line in a semiconductor device includes forming an interlayer insulating film over a substrate. A via hole may be formed by selectively patterning the interlayer insulating film. A metal film may be formed over a surface of the interlayer insulating film including an inner portion of the via hole. The inner portion of the via hole may be filled with copper. A copper layer exposed over the surface of the interlayer insulating film may be deplated using reverse current to form a copper metal line and a recess region over the copper metal line. An upper insulating film may be formed over the surface of the interlayer insulating film including the recess region by deposition. An insulating cap layer may be selectively formed over only the recess region on the copper metal line by etching the upper insulating film.

Abstract: A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the etch rate for the conductive oxide, resulting in improving etch selectivity. The disclosed selective etch process is well suited for ferroelectric memory device fabrication using conductive oxide/ferroelectric interface having silicon nitride as the encapsulated material for the ferroelectric.

Abstract: A system for low dielectric constant insulators is provided. One aspect of this disclosure relates to a method for forming an insulator. According to an embodiment of the method, a first structural material is applied as one or more layers of insulation to an integrated circuit surface, a damascene pattern is etched into the first structural material, a first barrier layer and a seed layer are deposited upon the insulation layer, a conductor layer is deposited upon the seed layer, at least a portion of the conductor layer is planarized and at least a portion of the first structural material is removed, a top barrier layer is deposited upon the conductor layer, and a final structural material is applied to replace at least a portion of the first structural material, the final structural material having a lower dielectric constant than the first structural material. Other aspects and embodiments are provided.

Abstract: A system and method is disclosed for manufacturing thin film resistors using a trench and chemical mechanical polishing. A trench is etched in a layer of dielectric material and a thin film resistor layer is deposited so that the thin film resistor layer lines the trench. A thin film resistor protection layer is then deposited to fill the trench. Then a chemical mechanical polishing process removes excess portions of the thin film resistor layer and the thin film resistor protection layer. An interconnect metal is then deposited and patterned to create an opening over the trench. A central portion of the thin film resistor protection material is removed down to the thin film resistor layer at the bottom of the trench. The resulting structure is immune to the effects of topography on the critical dimensions (CDs) of the thin film resistor.

Abstract: A high pressure chamber comprises a chamber housing, a platen, and a mechanical drive mechanism. The chamber housing comprises a first sealing surface. The platen comprises a region for holding the semiconductor substrate and a second sealing surface. The mechanical drive mechanism couples the platen to the chamber housing. In operation, the mechanical drive mechanism separates the platen from the chamber housing for loading of the semiconductor substrate. In further operation, the mechanical drive mechanism causes the second sealing surface of the platen and the first sealing surface of the chamber housing to form a high pressure processing chamber around the semiconductor substrate.

Abstract: Provided is a method for forming a metal wiring through a damascene process in a semiconductor device. The method includes: forming a metal diffusion barrier on a semiconductor substrate having a via hole and a trench therein; depositing a metal on the metal diffusion barrier, and filling the via hole and trench with the metal; performing a CMP process until an insulating layer is exposed, thereby forming the metal wiring from the metal; etching the exposed insulating layer by predetermined amount; and forming a passivation layer on the entire surface of the semiconductor substrate.

Abstract: Methods for fabricating a copper interconnect of a semiconductor device are disclosed. An example method for fabricating a copper interconnect of a semiconductor device deposits a first insulating layer on a substrate having at least one predetermined structure, forms a trench and via hole through the first insulating layer by using a dual damascene process, and deposits a barrier layer along the bottom and the sidewalls of the trench and via hole.

Abstract: When chemical mechanical planarization (CMP) is used to planarize a surface coexposing patterned features and dielectric fill, where patterned features and the fill are formed of materials having very different CMP removal rates or characteristics, the planarized surface may have excessively rough, dishing or recessing may take place, or one or more or the materials may be damaged. In structures in which planarity is important, these problems can be prevented by forming a capping layer on the patterned features, wherein the CMP removal rate of the material forming the capping layer is similar to the CMP removal rate of the dielectric fill.

Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

Abstract: Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the surface of the silicon oxide film and Cu interconnections is treated by a reducing plasma (ammonia plasma). Subsequently, a continuous cap film (silicon nitride film) is formed without vacuum break.

Abstract: Methods of forming electrical interconnects include the steps of forming a first electrically conductive layer on a semiconductor substrate and then forming a first electrically insulating layer on the first electrically conductive layer. A second electrically insulating layer is then formed on the first electrically insulating layer. The second electrically insulating layer is then etched to expose the first electrically insulating layer and then a third electrically insulating layer is formed on the first electrically insulating layer. The first and third electrically insulating layers are then etched to define a contact hole therein which exposes a portion of the first electrically conductive layer. A barrier metal layer is then formed. The barrier metal layer is preferably formed to extend on the third electrically insulating layer and on the exposed portion of the first electrically conductive layer.