Having Electrically Conductive Polysilicon Component Patents (Class 438/647)
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Patent number: 11121134Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.Type: GrantFiled: April 28, 2020Date of Patent: September 14, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Ho Lee, Eun A Kim, Ki Seok Lee, Jay-Bok Choi, Keun Nam Kim, Yong Seok Ahn, Jin-Hwan Chun, Sang Yeon Han, Sung Hee Han, Seung Uk Han, Yoo Sang Hwang
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Patent number: 11011520Abstract: This invention discloses a DRAM cell includes an asymmetric transistor coupled to a capacitor. The asymmetric transistor includes a drain region extending upward from an isolator region; a gate region extends upward from a gate dielectric or the isolator; a source region of asymmetric transistor extends upward from a first portion of an isolating layer. The upward extending directions of the drain region, the gate region, and the source region are perpendicular or substantially perpendicular to an original silicon surface. Moreover, the capacitor is partially formed in a concave and the isolating layer is positioned in the concave. The capacitor extends upward from a second portion of the isolating layer. The upward extending directions of the upright portion of the capacitor electrode, the third portion of the insulating layer and the counter electrode are perpendicular or substantially perpendicular to the original silicon surface.Type: GrantFiled: April 26, 2019Date of Patent: May 18, 2021Assignees: Etron Technology, Inc., Invention And Collaboration Laboratory Pte. Ltd.Inventor: Chao-Chun Lu
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Patent number: 9236253Abstract: A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region.Type: GrantFiled: January 28, 2014Date of Patent: January 12, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Hsien Chen, Ting-Chu Ko, Chih-Hao Chang, Chih-Sheng Chang, Shou-Zen Chang, Clement Hsingjen Wann
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Patent number: 9174835Abstract: A method of manufacturing microstructures, such as MEMS or NEMS devices, including forming a protective layer on a surface of a moveable component of the microstructure. For example, a silicide layer may be formed on one or more surfaces of a poly-silicon mass that is moveable with respect to a substrate of the microstructure. The process may be self-aligning.Type: GrantFiled: December 27, 2010Date of Patent: November 3, 2015Assignee: STMicroelectronics, Inc.Inventor: Ming Fang
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Patent number: 9006016Abstract: The present invention provides a method and apparatus for fabricating piezoresistive polysilicon on a substrate by low-temperature metal induced crystallization by: (1) providing the substrate having a passivation layer; (2) performing, at or near room temperature in a chamber without breaking a vacuum or near-vacuum within the chamber, the steps of: (a) creating a metal layer on the passivation layer, and (b) creating an amorphous silicon layer on the metal layer, wherein the metal layer and the amorphous silicon layer have approximately the same thickness; (3) annealing the substrate, the passivation layer, the metal layer and the amorphous silicon layer at a temperature equal to or less than 600° C. and a period of time equal to or less than three hours to form a doped polysilicon layer below a residual metal layer; and (4) removing the residual metal layer to expose the doped polysilicon layer.Type: GrantFiled: June 24, 2013Date of Patent: April 14, 2015Assignee: Board of Regents, The University of Texas SystemInventors: Zeynep Celik-Butler, Suraj K. Patil, Donald Philip Butler
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Patent number: 8956961Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.Type: GrantFiled: March 9, 2012Date of Patent: February 17, 2015Assignee: Rexchip Electronics CorporationInventors: Kazuaki Takesako, Wen-Kuei Hsu, Yoshinori Tanaka, Yukihiro Nagai, Chih-Wei Hsiung, Hirotake Fujita, Tomohiro Kadoya, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang
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Patent number: 8778796Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.Type: GrantFiled: October 10, 2012Date of Patent: July 15, 2014Assignee: Macronix International Co., Ltd.Inventor: Lo Yueh Lin
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Patent number: 8741772Abstract: A resistive memory device having an in-situ nitride initiation layer is disclosed. The nitride initiation layer is formed above the first electrode, and the metal oxide switching layer is formed above the nitride initiation layer to prevent oxidation of the first electrode. The nitride initiation layer may be a metal nitride layer that is formed by atomic layer deposition in the same chamber in which the metal oxide switching layer is formed. The nitride initiation layer and metal oxide switching layer may alternatively be formed in a chemical vapor deposition (CVD) chamber or a physical vapor deposition (PVD) chamber.Type: GrantFiled: February 16, 2012Date of Patent: June 3, 2014Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLCInventor: Albert Lee
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Patent number: 8697570Abstract: A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.Type: GrantFiled: November 8, 2010Date of Patent: April 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Taek-soo Jeon, Bong-hyun Kim, Won-seok Yoo, Jae-hong Seo, Ho-kyun An, Dae-hyun Kim
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Patent number: 8492238Abstract: The present invention provides a method and apparatus for fabricating piezoresistive polysilicon on a substrate by low-temperature metal induced crystallization by: (1) providing the substrate having a passivation layer; (2) performing, at or near room temperature in a chamber without breaking a vacuum or near-vacuum within the chamber, the steps of: (a) creating a metal layer on the passivation layer, and (b) creating an amorphous silicon layer on the metal layer, wherein the metal layer and the amorphous silicon layer have approximately the same thickness; (3) annealing the substrate, the passivation layer, the metal layer and the amorphous silicon layer at a temperature equal to or less than 600° C. and a period of time equal to or less than three hours to form a doped polysilicon layer below a residual metal layer; and (4) removing the residual metal layer to expose the doped polysilicon layer.Type: GrantFiled: August 14, 2009Date of Patent: July 23, 2013Assignee: Board of Regents, The University of Texas SystemInventors: Zeynep Celik-Butler, Suraj K. Patil, Donald Philip Butler
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Patent number: 8455360Abstract: A method for fabricating a storage node of a semiconductor device includes forming a sacrificial dielectric pattern with a storage node hole on a substrate, forming a support layer on the sacrificial dielectric pattern, forming a storage node, supported by the support layer, in the storage node hole, performing a full dip-out process to expose the outer wall of the storage node, and performing a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer.Type: GrantFiled: March 28, 2011Date of Patent: June 4, 2013Assignee: SK Hynix Inc.Inventors: Hyo Geun Yoon, Ji Yong Park, Sun Jin Lee
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Patent number: 8409989Abstract: A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.Type: GrantFiled: November 11, 2010Date of Patent: April 2, 2013Assignee: International Business Machines CorporationInventors: Chengwen Pei, Roger Allen Booth, Jr., Kangguo Cheng, Joseph Ervin, Ravi M. Todi, Geng Wang
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Publication number: 20120196436Abstract: A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench formed therein, forming a firs conductive layer on the substrate blanketly, forming a patterned photoresist having a surface lower than an opening of the trench in the trench, removing the first conductive layer not covered by the patterned photoresist to form a second conductive layer having a top lower than an opening of the trench in the trench, removing the patterned photoresist, performing a dry etching process to remove the second conductive layer from the bottom of the trench to form a third conductive layer on the sidewalls of the trench, performing a selective metal chemical vapor deposition to form a metal layer having a surface lower than a surface of the substrate, and forming a protecting layer filling the trench on the metal layer.Type: ApplicationFiled: April 9, 2012Publication date: August 2, 2012Inventors: Le-Tien Jung, Tai-Sheng Feng
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Patent number: 8105946Abstract: A method of forming the conductive lines of a semiconductor memory device comprises forming a first polysilicon layer over an underlying layer, forming first polysilicon patterns by patterning the first polysilicon layer, filling the space between the first polysilicon patterns with an insulating layer, etching a top portion of the first polysilicon patterns to form recess regions, forming spacers on the sidewalls of the recess regions, filling the recess regions with a second polysilicon layer to form second polysilicon patterns, and performing a metal silicidation process to convert the second polysilicon patterns to metal silicide patterns.Type: GrantFiled: December 17, 2010Date of Patent: January 31, 2012Assignee: Hynix Semiconductor Inc.Inventor: Won Sic Woo
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Publication number: 20120015515Abstract: A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench therein, forming a conductive layer having a top lower than an opening of the trench in the trench, performing a selective metal chemical vapor deposition (CVD) to form a metal layer having a top lower than the substrate in the trench, and forming a protecting layer filling the trench on the metal layer.Type: ApplicationFiled: December 29, 2010Publication date: January 19, 2012Inventors: Tai-Sheng Feng, Le-Tien Jung
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Patent number: 8063442Abstract: A field effect transistor includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and the resistive element is configured to induce a portion of the avalanche current to flow through the termination region and a remaining portion of the avalanche current to flow through the active region.Type: GrantFiled: December 30, 2010Date of Patent: November 22, 2011Assignee: Fairchild Semiconductor CorporationInventors: Hamza Yilmaz, Daniel Calafut
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Patent number: 8057857Abstract: Novel phase-separation behavior by a mixture, including binary mixture, of patterning compounds, including alkanethiols, when deposited onto a surface, including a gold surface, using micro and nano-deposition tools such as tip and stamp methods like micro-contact printing (?CP), and Dip-Pen Nanolithography (DPN). This behavior is significantly different than that observed in the bulk. This behavior was demonstrated using three examples of compounds: 16-mercaptohexadecanoic acid (MHA), 1-octadecanethiol (ODT), and CF3(CF2)11(CH2)2SH (PFT). The identity of the resulting segregated structure was confirmed by lateral force microscopy (LFM), and by selective metal-organic coordination chemistry. This phenomenon is exploited to print sub-100 nm wide alkanethiol features via conventional ?CP and to form sub-15 nm features using DPN printing, which is below the ultimate resolution of both these techniques. These nano-patterned materials also can serve as templates for constructing more complex architectures.Type: GrantFiled: July 5, 2006Date of Patent: November 15, 2011Assignee: Northwestern UniversityInventors: Chad A. Mirkin, Khalid Salaita
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Patent number: 8048739Abstract: According to yet another embodiment, a method for forming a non-volatile memory device includes etching a substrate to form first and second trenches. The first and second trenches are filled with an insulating material to form first and second isolation structures. A conductive layer is formed over the first and second isolation structures and between the first and second isolation structures to form a floating gate. The conductive layer and the first isolation structure are etched to form a third trench having an upper portion and a lower portion, the upper portion having vertical sidewalls and the lower portion having sloping sidewalls. The third trench is filled with a conductive material to form a control gate.Type: GrantFiled: June 30, 2006Date of Patent: November 1, 2011Assignee: Hynix Semiconductor Inc.Inventor: Chan Sun Hyun
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Patent number: 8039358Abstract: A method of manufacturing a semiconductor device includes the steps of forming a trench on a semiconductor substrate to define a first and a second element regions; burying a first oxide film in the trench; forming a second oxide film on surfaces of the first and second element regions; performing a first ion doping using a first mask which is exposing a first region containing the first element region and a part of the first oxide; performing a second ion doping using a second mask which is exposing a second region containing the second element region and a part of the first oxide film; and removing the second oxide film formed in the first element region and the second element region by etching, and the first oxide film is selectively thinned using the first or second mask after performing the first or second ion doping.Type: GrantFiled: March 21, 2008Date of Patent: October 18, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Masanori Terahara, Masaki Nakagawa
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Patent number: 7981482Abstract: Methods for forming doped silane and/or semiconductor thin films, doped liquid phase silane compositions useful in such methods, and doped semiconductor thin films and structures. The composition is generally liquid at ambient temperatures and includes a Group IVA atom source and a dopant source. By irradiating a doped liquid silane during at least part of its deposition, a thin, substantially uniform doped oligomerized/polymerized silane film may be formed on a substrate. Such irradiation is believed to convert the doped silane film into a relatively high-molecular weight species with relatively high viscosity and relatively low volatility, typically by cross-linking, isomerization, oligomerization and/or polymerization. A film formed by the irradiation of doped liquid silanes can later be converted (generally by heating and annealing/recrystallization) into a doped, hydrogenated, amorphous silicon film or a doped, at least partially polycrystalline silicon film suitable for electronic devices.Type: GrantFiled: June 19, 2006Date of Patent: July 19, 2011Assignee: Kovio, Inc.Inventors: Fabio Zürcher, Wenzhuo Guo, Joerg Rockenberger, Vladimir K. Dioumaev, Brent Ridley, Klaus Kunze, James Montague Cleeves
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Patent number: 7939434Abstract: A method of directly depositing a polysilicon film at a low temperature is disclosed. The method comprises providing a substrate and performing a sequential deposition process. The sequential deposition process comprises first and second deposition steps. In the first deposition step, a first bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a first polysilicon sub-layer on the substrate. In the second deposition step, a second bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a second polysilicon sub-layer on the first sub-layer. The first and second sub-layers constitute the polysilicon film, and the first bias voltage differs from the second bias voltage.Type: GrantFiled: May 6, 2008Date of Patent: May 10, 2011Assignee: Industrial Technology Research InstituteInventors: Chih-Yuan Tseng, I Hsuan Peng, Yung-Hui Yeh, Jung-Jie Huang, Cheng-Ju Tsai
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Publication number: 20110089488Abstract: A field effect transistor includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and the resistive element is configured to induce a portion of the avalanche current to flow through the termination region and a remaining portion of the avalanche current to flow through the active region.Type: ApplicationFiled: December 30, 2010Publication date: April 21, 2011Inventors: Hamza Yilmaz, Daniel Calafut
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Patent number: 7928008Abstract: A fabricating method of a polysilicon layer is disclosed which can be applied for fabricating a semiconductor device such as a SRAM and so on. The method for fabricating the semiconductor device includes the steps of: forming a transistor included in the semiconductor device on a semi conductor substrate forming an insulating layer on the transistor; forming contact holes, through which a region of the transistor is exposed, by selectively removing the insulating layer forming a silicon layer in the contact holes forming a metal layer on the insulating layer and the silicon layer; forming a metal suicide layer through heat treatment of the silicon layer and the metal layer; removing the metal layer; forming an amorphous silicon layer on the insulating layer and the metal suicide layer; and forming a polysilicon layer through heat treatment of the amorphous silicon layer.Type: GrantFiled: January 18, 2008Date of Patent: April 19, 2011Assignee: Terasemicon CorporationInventors: Taek-Yong Jang, Byung-Il Lee, Young-Ho Lee, Seok-Pil Jang
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Patent number: 7910481Abstract: A method for fabricating a semiconductor device includes forming an interlayer dielectric layer having a plurality of contact holes over a substrate, forming a conductive layer by filling the contact holes to cover the interlayer dielectric layer, performing a first main etch process to partially etch the conductive layer to form a first conductive layer, performing a second main etch process to etch the first conductive layer using an etch gas having a slower etch rate with respect to the first conductive layer than an etch gas used in the first main etch process until an upper surface of the interlayer dielectric layer is exposed to form a second conductive layer, and performing an over-etch process to etch a certain portion of the second conductive layer, and at the same time, to etch a certain portion of the interlayer dielectric layer to form a landing plug.Type: GrantFiled: December 17, 2009Date of Patent: March 22, 2011Assignee: Hynix Semiconductor Inc.Inventors: Sang-Soo Park, Seung-In Shin
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Patent number: 7855143Abstract: The present invention relates to an interconnect capping layer and a method of fabricating a capping layer for an interconnect. In particular, but not exclusively, the invention relates to a capping layer for a copper interconnect used to interconnect elements in an integrated circuit. Embodiments of the invention provide a method of fabricating a capping layer for an interconnect in an integrated circuit, comprising the steps of: forming an interconnect comprising upper and lower lateral surfaces; forming a lateral diffusion stop layer between said lateral surfaces; and forming a capping layer.Type: GrantFiled: December 22, 2006Date of Patent: December 21, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Huang Liu, Bangun Indajang, Wei Lu
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Patent number: 7833902Abstract: In a semiconductor device and a method of fabricating the same, the semiconductor device includes a contact pad in a first interlayer insulating layer on a semiconductor substrate, a contact hole in a second interlayer insulating layer on the first interlayer insulating layer, selectively exposing the contact pad, a contact spacer on internal walls of the contact hole, a first contact plug connected to the contact pad exposed by the contact hole having the contact spacer on the internal walls thereof, the first contact plug partially filling the contact hole, a metal silicide layer on a surface of the first contact plug, and a second contact plug on the metal silicide layer and partially filling the remaining portion of the contact hole.Type: GrantFiled: September 24, 2007Date of Patent: November 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Jin-won Lee
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Patent number: 7749778Abstract: A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.Type: GrantFiled: January 3, 2007Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Kaushik Chanda, Lawrence Clevenger, Timothy J. Dalton, Louis L. C. Hsu, Chih-Chao Yang
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Publication number: 20100105169Abstract: A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.Type: ApplicationFiled: August 18, 2009Publication date: April 29, 2010Inventors: Ho-jin Lee, Hyun-soo Chung, Chang-seong Jeon, Sang-sick Park, Jae-hyun Phee
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Patent number: 7701058Abstract: Defect density of a polysilicon metal silicide wiring is reduced by employing a block of undoped polysilicon metal silicide in locations in which dopants are not needed in the underlying polysilicon. Furthermore, detection of presence of defects in the polysilicon metal wiring that adversely impacts device performance at high frequency is facilitated by employing a block of undoped polysilicon metal silicide since defects in undoped polysilicon metal silicide is more readily detectable than defects in doped polysilicon metal silicide. Locations wherein undoped polysilicon metal silicide wiring is employed include areas over shallow trench isolation.Type: GrantFiled: January 26, 2007Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Patent number: 7595521Abstract: A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addressed can cause device failure.Type: GrantFiled: November 20, 2008Date of Patent: September 29, 2009Assignee: Micron Technology, Inc.Inventors: Robert J. Hanson, Alex Schrinsky, Terry McDaniel
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Publication number: 20090166872Abstract: A memory device with improved word line structure is disclosed. The memory device includes a plurality of polysilicon strips substantially parallel to each other on the substrate, the plurality of polysilicon strips arranged in two interleaved groups of a first group and a second group. The memory device further includes a first layer of conductive strips forming a plurality of bit lines and a second layer of meal strips, the second layer of conductive strips overlying the polysilicon strips and coupled to the first group of polysilicon strips. In addition, the memory device includes a third layer of conductive strips forming one or more power line, and a fourth layer of metal strips, the fourth layer of conductive strips overlying the second layer of conductive strips and coupled to the second group of polysilicon strips to form a new word line structure having a low resistance.Type: ApplicationFiled: April 10, 2008Publication date: July 2, 2009Inventors: Shine Chung, Cheng-Hsien Hung
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Patent number: 7531451Abstract: A System In Package (SIP) semiconductor device and a method for manufacturing a SIP device. A TiSiN film may be used as a diffusion barrier film for metal wiring in a SIP semiconductor device. A TiSiN film may provide relatively good step coverage in a relatively easy formation process, which may maximize reliability of a semiconductor device.Type: GrantFiled: July 23, 2007Date of Patent: May 12, 2009Assignee: Dongbu HiTek Co., Ltd.Inventor: Han-Choon Lee
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Patent number: 7524757Abstract: A method for manufacturing a multi-level transistor on a substrate. The method includes forming a first transistor on a first active region, forming a first selective epitaxial growth (SEG) layer on the substrate, and forming a preliminary second SEG layer and a dummy layer, wherein the preliminary second SEG layer is formed directly on only the first SEG layer and a portion of the first insulating layer formed on the cell region of the substrate, and wherein the dummy layer is formed on the peripheral region of the substrate. The method further includes planarizing the preliminary second SEG layer using the dummy layer as a stop layer to form a second SEG layer, forming a second active region from the second SEG layer formed on a first insulating layer, and forming a second transistor on the second active region.Type: GrantFiled: July 13, 2006Date of Patent: April 28, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-jun Kim, Chang-ki Hong, Bo-un Yoon, Jae-kwang Choi
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Publication number: 20090093092Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.Type: ApplicationFiled: October 8, 2007Publication date: April 9, 2009Inventors: DINH DANG, Thai Doan, Jessica Anne Levy, Max Gerald Levy, Alan Frederick Norris, James Albert Slinkman
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Publication number: 20080277792Abstract: Overlapping dummy patterns for a semiconductor device are disclosed. According to an embodiment, a first dummy pattern is formed on a substrate; a second dummy pattern is formed to be overlapped with the first dummy pattern; and a third dummy pattern is formed to provide an electrical connection between the first dummy pattern and the second dummy pattern.Type: ApplicationFiled: May 8, 2008Publication date: November 13, 2008Inventors: SANG HEE LEE, Gab Hwan Cho
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Patent number: 7442319Abstract: The use of an ammonium hydroxide spike to a hot tetra methyl ammonium hydroxide (TMAH) solution to form an insitu poly oxide decapping step in a polysilicon (poly) etch process, results in a single step rapid poly etch process having uniform etch initiation and a high etch selectivity, that may be used in manufacturing a variety of electronic devices such as integrated circuits (ICs) and micro electro-mechanical (MEM) devices. The etching solution is formed by adding 35% ammonium hydroxide solution to a hot 12.5% TMAH solution at about 70° C. at a rate of 1% by volume, every hour. Such an etch solution and method provides a simple, inexpensive, single step self initiating poly etch that has etch stop ratios of over 200 to 1 over underlying insulator layers and TiN layers.Type: GrantFiled: June 28, 2005Date of Patent: October 28, 2008Assignee: Micron Technology, Inc.Inventor: Kevin Shea
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Patent number: 7427543Abstract: The present invention provides source/drain electrode 100 for a transistor 105. The source/drain electrode 100 comprises a plurality of polysilicon grains 100 located over a source/drain region 115. A metal salicide layer 120 conformally coats the plurality of polysilicon grains. The present invention also includes a method of fabricating the above described source/drain electrode 200, and integrated circuit 800 have includes a semiconductor device 805 having the described source/drain electrodes 810.Type: GrantFiled: August 7, 2006Date of Patent: September 23, 2008Assignee: Texas Instruments IncorporatedInventors: Majid M. Mansoori, Christoph A. Wasshuber
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Publication number: 20080093741Abstract: In a semiconductor device and a method of fabricating the same, the semiconductor device includes a contact pad in a first interlayer insulating layer on a semiconductor substrate, a contact hole in a second interlayer insulating layer on the first interlayer insulating layer, selectively exposing the contact pad, a contact spacer on internal walls of the contact hole, a first contact plug connected to the contact pad exposed by the contact hole having the contact spacer on the internal walls thereof, the first contact plug partially filling the contact hole, a metal silicide layer on a surface of the first contact plug, and a second contact plug on the metal silicide layer and partially filling the remaining portion of the contact hole.Type: ApplicationFiled: September 24, 2007Publication date: April 24, 2008Applicant: Samsung Electronics Co., Ltd.Inventor: Jin-won Lee
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Patent number: 7351654Abstract: A method for producing a semiconductor device includes the steps of forming silicon crystal nuclei on a substrate, depositing first amorphous silicon, depositing second amorphous silicon, and crystallizing the first amorphous silicon and the second amorphous silicon by allowing the crystal nuclei to grow in the solid phase.Type: GrantFiled: May 19, 2005Date of Patent: April 1, 2008Assignee: Elpida Memory, Inc.Inventors: Norishiro Komatsu, Fumiki Aiso, Toshiyuki Hirota
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Patent number: 7291527Abstract: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.Type: GrantFiled: September 7, 2005Date of Patent: November 6, 2007Assignee: Texas Instruments IncorporatedInventors: James Joseph Chambers, Mark Robert Visokay, Luigi Colombo, Antonio Luis Pacheco Rotondaro
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Patent number: 7265038Abstract: A copper filled damascene structure and method for forming the same the method including providing a substrate comprising a semiconductor substrate; forming an insulator layer on the substrate; forming a damascene opening through a thickness portion of the insulator layer; forming a diffusion barrier layer to line the damascene opening; forming a first seed layer overlying the diffusion barrier; plasma treating the first seed layer in-situ with a first treatment plasma comprising plasma source gases selected from the group consisting of argon, nitrogen, hydrogen, and NH3; forming a second seed layer overlying the first seed layer; forming a copper layer overlying the second seed layer according to an electro-chemical plating (ECP) process to fill the damascene opening; and, planarizing the copper layer to form a metal interconnect structure.Type: GrantFiled: November 25, 2003Date of Patent: September 4, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ping-Kun Wu, Horng-Huei Tseng, Chine-Gie Lo, Chao-Hsiung Wang, Shau-Lin Shue
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Patent number: 7245015Abstract: In a display apparatus, a display panel receives a driving signal from a driving chip through a pad and displays an image in response to the driving signal. The driving chip includes a terminal outputting the driving signal. The driving chip is mounted on the display panel using the anisotropic conductive film and electrically connected to the display panel. A lubricant layer is formed on a surface of the anisotropic conductive film to prevent an electrical defect in the connection between the driving chip and the display panel. Thus, the display apparatus may have improved yield.Type: GrantFiled: August 11, 2005Date of Patent: July 17, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Yong Hwang, Weon-Sik Oh
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Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device
Patent number: 7195995Abstract: A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making is described. The multilayered doped conductor creates a high dopant concentration in the active area close to the channel region. The rich dopant layer created by the multilayered doped conductor is less susceptible to depletion from trapped charges in the oxide. This improves device reliability at burn-in and lowers junction leakage, thereby providing a longer period between refresh cycles.Type: GrantFiled: November 16, 2004Date of Patent: March 27, 2007Assignee: Micron Technology, Inc.Inventor: Chandra V. Mouli -
Patent number: 7189641Abstract: A method forming a tungsten contact can include forming a contact hole in an interlayer dielectric layer to expose a portion of an underlying silicon based substrate and to form a side wall of the contact hole. A tungsten silicide layer can be formed on at least on the exposed portion of the substrate. A tungsten nitride layer can be conformally formed on a surface of the interlayer dielectric layer, on the tungsten silicide layer and on the side wall. A contact tungsten layer can be formed on the tungsten nitride layer to fill the contact hole. Related apparatus and contacts are also disclosed.Type: GrantFiled: August 18, 2004Date of Patent: March 13, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Woo Lee, Gil-Heyun Choi, Jong-Myeong Lee, Kyung-In Choi
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Patent number: 7169696Abstract: A system and method for selecting nanometer-scaled devices. The method includes a plurality of semiconductor wires. Two adjacent semiconductor wires of the plurality of semiconductor wires are associated with a separation smaller than or equal to 100 nm. Additionally, the system includes a plurality of address lines. Each of the plurality of address lines includes a gate region and an inactive region and intersects the plurality of semiconductor wires at a plurality of intersections. The plurality of intersections includes a first intersection and second intersection. The first intersection is associated with the gate region, and the second intersection is associated with the inactive region.Type: GrantFiled: June 22, 2004Date of Patent: January 30, 2007Assignee: California Institute of TechnologyInventors: James R. Heath, Yi Luo, Rob Beckman
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Patent number: 7162796Abstract: A method of making an interposer having an array of contact structures for making temporary electrical contact with the leads of a chip package. The contact structures may make contact with the leads substantially as close as desired to the body of the chip package. Moreover, the contact structures can be adapted for making contact with leads having a very fine pitch. In a first embodiment, the contact structures include raised members formed over a body of the interposer. A conductive layer is formed over each of the raised members to provide a contact surface for engaging the leads of the chip package. In another embodiment, the raised members are replaced with depressions formed into the interposer. A conductive layer is formed on an inside surface of each depression to provide a contact surface for engaging the leads of the chip package. Moreover, any combination of raised members and depressions may be used.Type: GrantFiled: October 1, 2004Date of Patent: January 16, 2007Assignee: Micron Technology, Inc.Inventors: James M. Wark, Salman Akram
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Patent number: 7160801Abstract: A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.Type: GrantFiled: December 21, 2000Date of Patent: January 9, 2007Assignee: Micron Technology, Inc.Inventors: Martin C. Roberts, Sanh D. Tang
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Patent number: 7144807Abstract: Low resistivity, C54-phase TiSi2 is formed in narrow lines on heavily doped polysilicon by depositing a bi-layer silicon film. A thin, undoped amorphous layer is deposited on top of a heavily doped layer. The thickness of the undoped amorphous Si is about 2.4 times the thickness of the subsequently deposited Ti film. Upon thermal annealing above 750° C., the undoped amorphous Si is consumed by the reaction of Ti+Si to form TiSi2, forming a low-resistivity, C54-phase TiSi2 film on top of heavily doped polysilicon. The annealing temperature required to form C54 phase TiSi2 is reduced by consuming undoped amorphous Si in the reaction of Ti and Si, as compared with heavily doped polysilicon. Narrow lines (<0.3 ?m) of low-resistivity, C54-phase TiSi2 films on heavily doped polysilicon are thus achieved.Type: GrantFiled: September 18, 2002Date of Patent: December 5, 2006Assignee: SanDisk 3D LLCInventors: Scott Brad Herner, Michael A. Vyvoda
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Patent number: 7067391Abstract: A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.Type: GrantFiled: February 17, 2004Date of Patent: June 27, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bor-Wen Chan, Chih-Hao Wang, Lawrance Hsu, Hun-Jan Tao
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Patent number: 7026232Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that mitigate leakage and apply strain to channel regions of transistor devices. A semiconductor device having gate structures, channel regions, and active regions is provided (102). Extension regions of a first type of conductivity are formed within the active regions (104). Recesses are then formed within a portion of the active regions (106). Second type recess structures are formed (108) within the recesses, wherein the second type recess structures have a second type of conductivity opposite the first type and are comprised of a strain inducing material. Then, first type recess structures are formed (110) within the recesses and on the second type recess structures, wherein the first type recess structures have the first type of conductivity and are comprised of a strain inducing material.Type: GrantFiled: December 23, 2004Date of Patent: April 11, 2006Assignee: Texas Instruments IncorporatedInventors: Elisabeth Marley Koontz, Antonio Luis Pacheco Rotondaro