Abstract: Formed in a second interlayer dielectric are a first contact hole and a second contact hole. The first and second contact holes each extend to a first-level interconnect line. Tungsten is formed on the entirety of a substrate to form a first plug, a second plug, and a tungsten layer. A silicon oxide layer is formed. Thereafter, a patterning process is carried out to form a second-level interconnect line which is connected with the first plug and a top protective layer, and the top of the second plug remains exposed. A sidewall is formed on the side surfaces of the second-level interconnect line and the top protective layer. Subsequently, a third-level interconnect line, which is connected with the exposed second plug, is formed. Such arrangement not only reduces the number of contact hole formation masks, it also cuts down the number of fabrication steps. Further, the aspect ratio of the second contact hole becomes lower thereby achieving highly reliable semiconductor devices.

Abstract: A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher for emitter dopants than in single crystal semiconductor material. Separate base and emitter poly layers are formed undoped. Then, the emitter poly of one device and the edges of the base poly of the other device are exposed through a dopant mask and simultaneously doped. The emitter dopant goes directly into the surface of the emitter poly where it lies over and is in contact with the base. The base contact dopant goes into the edges of the base poly, including the layer of material having the high diffusion coefficient, rapidly diffuses laterally throughout that layer, and then diffuses down into the collector material (e.g. island) surface, to form the extrinsic base.

Abstract: The invention provides a method of fabricating a semiconductor device, including the steps of (a) forming an impurity region at a surface of a silicon substrate, (b) depositing an insulative film over the silicon substrate, (c) forming a contact hole through the insulative film to expose the impurity region of the silicon substrate, (d) forming an electrode wiring over the contact hole, the electrode wiring comprising a refractory metal silicide film and a silicon film overlying on the metal silicide film, the metal silicide film overlying the exposed impurity region, (e) depositing a second insulative film over a resultant, (f) depositing a polysilicon film on the second insulative film, (g) patterning the polysilicon film to form an element, and (h) heat-treating a resultant at high temperature in oxidizing atmosphere. The step (h) is to be carried out at any time after the step (f) has been completed.

Abstract: A process for fabricating a protective shield for polysilicon loads in SRAM devices is disclosed. The protective shield enables to protect the polyloads from resistance characteristics degradation during the subsequent plasma-based processing steps in the fabrication of the memory device after the polyloads are formed. The polyloads are formed in a photolithography procedure by utilizing a photomask defining the resistive and conductive portions of the polyloads. The process comprises the steps of forming a shield silicon oxide layer over the surface of the memory device in process, including the polyloads, and forming a shield silicon nitride layer on the top of the shield silicon oxide layer. The protective shield is then formed by etching in the shield silicon oxide and nitride layers utilizing a protective photomask. The protective photomask is the same photomask utilized in the formation of the polyloads in the previous photolithography procedural step of the fabrication of the memory device.

Abstract: A semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening includes, a) providing a node location and a plug molding layer outwardly thereof; b) providing a contact opening through the plug molding layer to the node location; c) providing a first layer of semiconductive material over the molding layer to within the contact opening, the first layer thickness being less than one-half the contact opening width to leave a first remaining opening, the first layer having an average conductivity enhancing dopant concentration from 0 atoms/cm.sup.3 to about 5.times.10.sup.18 atoms/cm.sup.3 ; d) after providing the first layer, increasing the average conductivity enhancing dopant concentration of the first layer to greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.

Abstract: A method is disclosed for providing a self-aligned silicide strap for connecting thin polysilicon layers (poly-1 and poly-2, etc.) separated by non-conducting gaps. A butting contact opening to the layers is formed in an overlying insulating layer. The contact exposes the poly-1 and poly-2 layers. A thin polysilicon layer (poly-3) is then deposited over the insulating layer and into the contact. This is followed by deposition of a refractory metal layer. The poly-3 layer should be thin enough that, alone, it cannot supply enough silicon to support full silicidation of the refractory metal layer. The structure is next sintered so that a silicide strap is formed in the contact opening and across exposed portions of the poly-1 and poly-2 layers. The ratio of silicon to titanium in regions over the insulating layer is lower than that in the strap, such that these more metallic regions may be selectively removed.

Abstract: A process for creating a MOSFET device, using a polysilicon contact stud, in a sub-micron diameter contact hole, used to interconnect an underlying active device region, in a semiconductor substrate, and an overlying metal structure, has been developed. The process features depositing a polysilicon layer, to fill a sub-micron diameter contact hole, followed by an oxygen ion implantation procedure, into regions of polysilicon that are not used for the contact stud. A subsequent anneal procedure converts the oxygen implanted regions of the polysilicon layer to a silicon oxide layer. Removal of the silicon oxide layer leaves a polysilicon contact stud, in the sub-micron diameter contact hole.

Abstract: Disclosed is a method and an apparatus for making devices with low barrier height. In fabricating an n-channel and p-channel devices, hemisphere grains, silicon crystal grains and metal silicide crystal grains are formed on a contact-hole or a gate electrode on an insulating film in each semiconductor element, so that it becomes possible to control the work function, to reduce the contact resistance, and to control the threshold voltage V.sub.th.

Abstract: A polysilicon resistor (40) includes a field oxide layer (12) and a polysilicon layer (20) that covers a portion of field oxide layer (12). The polysilicon layer (20) possesses a predetermined electrical resistance value. Nitride/oxide stack (42) covers a predetermined portion of the polysilicon layer (20) and forms at least one exposed location of polysilicon layer (20) on which not to implant a dopant to achieve a predetermined resistance value. Silicide layer (34) covers exposed location.

Abstract: A method of semiconductor fabrication having applicability to forming contacts to sources and drains especially in SRAM applications is disclosed. A dielectric and an overlying polysilicon conductor are formed and patterned thereby exposing a semiconductor substrate. A silicide layer is deposited, thereby contacting the polysilicon layer and the substrate. Subsequent patterning of the silicide layer using an oxide hard mask provides electrical contact between the polysilicon layer and the substrate without the risk of trenching into the substrate.

Abstract: A silicon layer in a lower layer and an interconnection layer arranged in an upper layer are electrically connected through an opening for contact. A silicon plug layer having the same conductivity type as that of the silicon layer is embedded in the opening. The silicon plug layer is embedded in the opening by an etch back method after deposited using a CVD method. The interconnection layer in the upper layer has conductivity type different from that of the silicon plug layer. A refractory metal silicide layer is formed between the upper interconnection layer and the silicon plug layer. The refractory metal silicide layer prevents pn junction from being formed between the upper interconnection layer and the silicon plug layer.

Abstract: An interconnect between a conductor and a transistor body above a gate electrode is established by forming a conductor separated and alongside a gate electrode. Both the conductor and the gate electrode are coated with a dielectric material such as silicon dioxide. The silicon dioxide layer is subsequently coated with a thin layer of polysilicon and a contact hole is photolithographically etched through the polysilicon layer and through the silicon dioxide layer to establish a contact hole to said conductor. The polysilicon layer protects the silicon dioxide layer from impurities in the photolithography process. After the photolithographic mask is removed, a second layer of polysilicon is deposited on the first layer of polysilicon, coating the polysilicon layer and partially filling the contact hole, establishing a contact between the combined polysilicon layers and the conductor.

Abstract: A polysilicon sensor is described which can be incorporated onto a silicon wafer containing integrated circuits for the purpose of detecting and monitoring electromigration(EM) in metal test stripes representative of the interconnection metallurgy used by the integrated circuits. The sensor capitalizes on the property of silicon whereby a small increase in temperature causes a large increase in carrier concentration. In this regard, the local temperature rise of an adjacent metal line undergoing EM failure manifests itself as a decrease in resistance of the sensor. The sensor is particularly suited for testing multi-level metallurgies such as those having an aluminum alloy sandwiched between metallic layers such as those used for diffusion barriers and anti-reflective coatings. Its fabrication is compatible with conventional MOSFET processes which use a self-aligned polysilicon gate.

Abstract: A method for producing an interconnect on a semiconductor device has silicon containing conductive surfaces and dielectric surfaces. The process includes forming separate regions of a blanket first refractory metal silicide on the silicon containing conductive surfaces, the first refractory metal silicide being composed of a first refractory metal and silicon from the surfaces, forming a blanket second refractory metal layer over the device, forming a blanket .alpha.-Si layer over the second refractory metal layer, forming a mask over the device to pattern an interconnect between the separate regions, then etching away the unwanted portions of the refractory metal layers and the .alpha.-Si layer, performing a rapid thermal annealing process on the device forming a low resistance refractory metal silicide between the .alpha.-Si layer and the second refractory metal layer, and then etching away the unwanted portions of the refractory metal layers that are not covered by the refractory metal silicide.