Abstract: The present invention provides a method for controlling dopant density of a plug-shaped doped polysilicon layer formed within a plug-shaped recess to prevent the dopant contained in the plug-shaped doped polysilicon layer from diffusing into a conductive layer under the plug-shaped recess through a bottom side of the plug-shaped recess, the plug-shaped recess being formed within a dielectric layer which is positioned above the conductive layer, the method comprising: (1) forming an undoped silicon layer on the surface of the plug-shaped recess; (2) forming a doped polysilicon layer on top of the undoped silicon layer to fill the plug-shaped recess; and (3) performing a thermal treatment to the semiconductor wafer so as to make the doped poly-silicon layer interact with the undoped silicon layer inside the plug-shaped recess which forms a completely doped polysilicon layer within the plug-shaped recess.

Abstract: A memory array region and a periphery circuit region are defined on a silicon substrate of a semiconductor wafer. A plurality of gates is formed on the silicon substrate in both the memory array region and the periphery circuit region. A barrier layer and a dielectric layer are formed, respectively, on the semiconductor wafer. Therein, the barrier layer covers the gates and the barrier layer fills a space between two gates. Following that, the dielectric layer atop each gate is removed and the dielectric layer remaining in the space between two gates is aligned to the surface of the gates. A photoresist layer is formed to cover the memory array region followed by an etching process to remove the dielectric layer and the barrier layer down to the surface of the silicon substrate. The photoresist layer and the barrier layer atop the gate in the memory array region are removed. Finally, a salicide process is performed.

Abstract: A film formation method for manufacture of a semiconductor device includes the steps of forming a first metal film as a continuous film on a substrate, forming a second metal film as discontinuous films on the substrate formed with the first metal film, and forming a third metal film by plating on the substrate formed with the first and second metal films.

Abstract: A semiconductor device comprises a SOI substrate formed of a semiconductor substrate, an insulation layer provided above the semiconductor substrate, and a SOI layer provided above the insulation layer. An impurity layer is provided in the semiconductor substrate. The impurity layer is electrically connected to a wiring layer provided above the SOI layer. The impurity layer can function as either a wiring layer or a resistance layer. This semiconductor device makes it possible to utilize the region above the semiconductor layer efficiently.

Abstract: A method of manufacturing a contact plug in a semiconductor device is disclosed. In-situ thermal doping of an impurity such as phosphorous (P) during the process by which polysilicon for a contact plug is formed by selective growth method and after in-situ doping after the growth process is employed in order to increase the concentration of the impurity in the contact plug. As a result, the disclosed method can reduce the interfacial resistance at the plug to improve the electrical characteristics of a device of more than 1 G bits.

Abstract: A method of forming a contact structure in a semiconductor device is provided. In this method, a semiconductor layer, an ohmic metal layer, and a barrier metal layer are formed on the surface of a semiconductor substrate on which a metal contact hole has been formed. A compound material layer having a uniform thickness is formed on the bottom, sidewalls and lower corners of the contact hole by thermally reacting the semiconductor layer with the ohmic metal layer. Accordingly, when the contact hole exposes an impurity layer and portions of an isolation layer adjacent to the impurity layer, the junction leakage current characteristics of the impurity layer and a contact resistance are improved.

Abstract: A self-aligned via between interconnect layers in an integrated circuit, and a process for forming such a via which allows a less precise masking alignment to be used to fabricate an integrated circuit with increased packing density.

Abstract: A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

Abstract: The invention comprises methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry. In one implementation, a method of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry includes forming a conductive metal interconnect layer over a substrate. An insulating dielectric mass is provided about the conductive metal interconnect layer. The insulating dielectric mass has a first dielectric constant. At least a majority of the insulating dielectric mass is etched away from the substrate. After the etching, an interlevel dielectric layer is deposited to replace at least some of the etched insulating dielectric material. The interlevel dielectric layer has a second dielectric constant which is less than the first dielectric constant.

Abstract: A method of forming self aligned contacts in silicon integrated circuit wafers which has a reduced contact resistance is described. A contact hole formed in a layer of dielectric is filled with polysilicon using a split polysilicon process. A first polysilicon layer is deposited after the contact hole is opened. The first polysilicon is preferably, but not necessarily, high temperature film doped polysilicon. The first polysilicon is then treated using C2F6/O2. A second polysilicon layer, preferably furnace doped polysilicon, is then deposited to completely fill the contact hole. The wafer is then planarized, using chemical mechanical polishing or back etching, leaving polysilicon completely filling the contact hole and forming a low resistance contact.

Abstract: A method for making a multi-layer polysilicon plug forms a plurality of undoped polysilicon thin layers alternating with a plurality of doped polysilicon thin layers on a substrate having a concavity until the polysilicon layers fill the concavity. Thus, a multi-layer polysilicon layer is formed. The multi-layer polysilicon layer is patterned and etched to form a multi-layer polysilicon plug in the concavity.

Abstract: An embodiment of the present invention teaches a method used in a semiconductor fabrication process to form a memory cell in a semiconductor device comprising the steps of: subjecting a layered structure comprising a silicon gate insulating layer, a conductively doped polysilicon gate layer and a refractory metal silicide gate film to a thermal processing step; forming a sheet resistance capping layer directly on the refractory metal silicide film during at least a period of time of the thermal processing step, the sheet resistance capping layer forming a substantially uniform surface on the refractory metal silicide film; patterning and etching the layered structure to form the transistor gate; forming source and drain regions aligned to apposing sides of the transistor gate and formed into an underlying silicon substrate; and forming a storage capacitor (such as a stacked capacitor or a container cell) connecting to one of the source and drain regions.

Abstract: This invention is a process for forming an effective titanium nitride barrier layer between the upper surface of a polysilicon plug formed in a thick dielectric layer and a platinum lower capacitor plate in a dynamic random access memory which is being fabricated on a silicon wafer.

Abstract: A self-aligned contact hole is formed in a cell area of a semiconductor device, and then a polysilicon layer is formed on both the cell area and a peripheral circuit area. A first etch back process is performed using a reactant etching gas, such as Cl2 gas, having a high etching rate with respect to the polysilicon layer. This first etch back process on the polysilicon layer is stopped before exposing the top surface of a capping layer in the peripheral circuit area, thereby leaving a thin polysilicon film on the capping layer. A second etch back process is then performed to form a polysilicon node filling the self-aligned contact hole in the cell area. In the second etch back process, an etching reactant gas, such as HBr gas, is used, which has a high etching selectivity of polysilicon with respect to the capping layer.

Abstract: A method of fabricating a self-align-contact is provided. A first gate and a second gate are formed on a semiconductor substrate. A spacer is formed on the sidewalls of the first gate and the second gate, and a source/drain region is formed between the first gate and the second gate. A dielectric layer is formed on the first gate, the second gate, the source/drain region, the spacer, and the semiconductor substrate. A self-align-contact opening is formed in the dielectric layer to expose the source/drain region. A metal silicide layer is formed on the source/drain region. A first conductive layer, such as doped polysilicon, is formed on the metal silicide layer and in the self-align-contact opening. A second conductive layer is formed on the first conductive layer, and the first conductive layer and the second conductive layer are patterned.

Abstract: A first contact hole for a bit line is formed in an interlayer insulating film, and a polysilicon film is formed on the inner surface of the contact hole and on the interlayer insulating film. Subsequently, the polysilicon film is subjected to isotropic dry etching using a resist as a mask, and the interlayer insulating film is subjected to RIE etching, thereby forming a second contact hole in the interlayer insulating film in a peripheral circuit region. Then, a laminated film is formed on the inner surface of the second contact hole and on the polysilicon film, and the second contact hole is filled with a filling member. The laminated film and the polysilicon film are patterned, thereby forming a bit line in a memory cell region.

Abstract: The present invention provides a process for forming a sub-micron p-type metal oxide semiconductor (PMOS) structure on a semiconductor substrate. The process includes forming a gate oxide on the semiconductor substrate, forming a gate layer on the gate oxide by depositing a first gate layer on the gate oxide at a first deposition rate and depositing a second gate layer on the first layer at a second deposition rate to provide an improved stress accommodation within the gate structure. The process further includes forming a silicide dopant barrier on the gate. Due to the presence of the improved stress accommodation in the gate, the integrity of the silicide dopant barrier is substantially enhanced. This increased silicide integrity prevents significant damage to the silicide dopant barrier layer during subsequent fabrication processes.

Abstract: An embodiment of the present invention teaches a method used in a semiconductor fabrication process to form a memory cell in a semiconductor device comprising the steps of: subjecting a layered structure comprising a silicon gate insulating layer, a conductively doped polysilicon gate layer and a refractory metal silicide gate film to a thermal processing step; forming a sheet resistance capping layer directly on the refractory metal silicide film during at least a period of time of the thermal processing step, the sheet resistance capping layer forming a substantially uniform surface on the refractory metal silicide film; patterning and etching the layered structure to form the transistor gate; forming source and drain regions aligned to apposing sides of the transistor gate and formed into an underlying silicon substrate; and forming a storage capacitor (such as a stacked capacitor or a container cell) connecting to one of the source and drain regions.

Abstract: A multiple step chemical vapor deposition process for depositing a tungsten silicide layer on a substrate. A first step of the deposition process includes a pretreatment step in which WF6 is introduced into a deposition chamber. Next, the introduction of WF6 is stopped and a silicon-containing gas, e.g., SiH4, is introduced into the chamber. Finally, during a third step, the SiH4 flow is stopped and DCS and WF6 are introduced into the chamber to deposit a tungsten silicide layer on the substrate.

Abstract: Disclosed is a novel contact structure comprising an underlying layer of titanium silicide, an intermediate layer of titanium boride, and an overlying layer of polysilicon. Also disclosed is a method for forming the contact structure which comprises depositing a titanium layer in the bottom of a contact opening having oxide insulation sidewalls, forming an overlying layer of polysilicon above the titanium layer, and annealing the two layers together. The resulting contact structure is formed with fewer steps than contact structures of the prior art and without the need for additional steps to achieve uniform sidewall coverage, due to high adhesion of the overlying layer of polysilicon with oxide insulation sidewalls of the contact opening. The contact structure has low contact resistance, and provides a suitable diffusion barrier due to a high melting point.

Abstract: A method of manufacturing an interconnect. A wafer having an edge region and an interior region is provided. An insulating layer is formed on the wafer. An opening penetrating through the insulating layer in the interior region is formed and a portion of the insulating layer is removed to expose the surface of the wafer in the edge region, simultaneously. A conductive layer is formed on the insulating layer and the wafer exposed by the insulating layer and fills the opening. The conductive layer is patterned to form a wire in the opening.

Abstract: A method for forming a low resistance metal/polysilicon gate for use in CMOS devices comprising: (1) a novel anneal step prior to formation of a diffusion barrier layer and (2) a novel diffusion barrier layer composed of titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon. A first insulating layer is formed over a silicon substrate, and a polysilicon layer is formed over the first insulating layer. In a key step, the polysilicon layer is annealed to prevent peeling of the subsequently formed diffusion barrier layer. A diffusion barrier layer comprising titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon is formed over the polysilicon layer. A tungsten layer is formed over the diffusion barrier layer, and a capping layer comprising a silicon nitride layer over an oxide layer can be formed over the tungsten layer.

Abstract: This invention relates to a method of forming a landing pad on a semiconductor wafer comprising a silicon substrate, a dielectric layer, a passivation layer and a photo-resist layer. The photo-resist layer comprises a hole penetrating to the surface of the passivation layer which defines the position of the landing pad. An anisotropic etching through the hole is performed to vertically remove the passivation layer and a predetermined thickness of the dielectric layer under the hole to form a recess, and then the photo-resist layer is removed. A filling layer is deposited on the passivation layer and the recess. An etch-back process is performed to remove the filling layer on the bottom portion of the recess and form a circular spacer on the surrounding portion of the recess. Another anisotropic etching is performed to vertically remove the dielectric layer under the recess and down to the surface of the silicon substrate which forms a plug hole, over which the circular spacer is used as a hard mask.

Abstract: A method of fabricating an improved spacer comprising the steps of providing a semiconductor substrate that has a gate already formed thereon. A PNO spacer is formed on a sidewall of the gate. The method of forming the PNO spacer comprises first forming a PNO layer on the conductive layer and the semiconductor, and performing an anisotropic etching step on the PNO layer to form the PNO spacer. The step of forming the PNO layer includes chemical vapor deposition (CVD) using PH3, O2, NH3 and N2 as reagents. The step of etching the PNO layer includes plasma etching using CFX+O2 as plasma source. The material of the PNO spacer is a chemical compound PXNYOZ containing phosphorous (P), nitrogen (N) and oxygen (O) and does not contain silicon. Therefore, the PNO spacer can avoid erosion during etching and does not react with Ti during the Salicide process.

Abstract: A copper damascene process for forming copper plugs. A conductive structure that includes an amorphous silicon layer and a metal line is formed over a substrate. A dielectric liner layer is formed over the conductive structure and the substrate. A multi-level dielectric layer is formed over the dielectric liner layer, then the multi-level dielectric layer and dielectric liner layer are patterned to form a via that exposes a portion of the amorphous silicon layer on the conductive line. Metal barrier spacers are formed on the sidewalls of the via. A copper displacement process is next carried out to convert the amorphous silicon layer into a first copper layer. Since a portion of the metal barrier spacers is also converted into a second copper layer. a process is carried out to remove the second copper layer from the metal barrier spacers. Using the first copper layer as a seeding layer, a copper electroless plating is carried out.

Abstract: An improved method to form self-aligned contacts with polysilicon plugs is described. A semiconductor substrate is provided. A silicon oxide layer overlying the semiconductor substrate is deposited. A contact hole is etched through the silicon oxide layer to the surface of the semiconductor substrate. A polysilicon layer is deposited overlying the silicon oxide layer and filling completely the contact hole. The polysilicon layer is polished away to define only polysilicon remaining in the contact hole and to remove the silicon oxide layer sufficient to flatten the top surface of the silicon oxide layer. The fabrication of the integrated circuit device is completed.

Abstract: Many integrated circuits include a type of transistor known as a bipolar junction transistor, which has an emitter contact formed of polysilicon. Unfortunately, polysilicon has a relatively high electrical resistance that poses an obstacle to improving switching speed and current gain of bipolar transistors. Current fabrication techniques involve high temperature procedures that melt desirable low-resistance substitutes, such as aluminum, during fabrication. Accordingly, one embodiment of the invention provides an emitter contact structure that includes a polysilicon-carbide layer and a low-resistance aluminum, gold, or silver member to reduce emitter resistance. Moreover, to overcome manufacturing difficulties, the inventors employ a metal-substitution technique, which entails formation of a polysilicon emitter, and then substitution of metal for the polysilicon.

Abstract: A process for breaking silicide stringers extending between silicide regions of different active regions on a semiconductor device is provided. Consistent with an exemplary fabrication process, two adjacent silicon active regions are formed on a substrate and a metal layer is formed over the two adjacent silicon active regions. The metal layer is then reacted with the silicon active regions to form a metal silicide on each silicon active region. This silicide reaction also forms silicide stringers extending from each silicon active region. Finally, at least part of each silicide stringer is removed. During the formation of the silicide stringers at least one silicide stringer may be formed which bridges the metal silicide over one of the silicon regions and the metal silicide over the other silicon region. In such circumstances, the removal process may, for example, break the silicide stringer and electrically decouple the two silicon regions.

Abstract: A method for forming a contact plug formed of polysilicon and a method for manufacturing a semiconductor device using the same are provided. The contact plug is formed by etching back polysilicon which fills a contact hole and is deposited on an interlayer dielectric film using a gas mixture of SF6, CHF3, and CF4, thus planarizing the polysilicon. Also, the contact plug can be made protrude above the interlayer dielectric film by etching the entire surface of the exposed interlayer dielectric film around the polysilicon contact plug formed by etching back the polysilicon. According to the present invention, the degree of planarization of the polysilicon contact plug is improved by etching back the polysilicon using the gas mixture of SF6, CHF3, and CF4.

Abstract: A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

Abstract: A plug forming method for a semiconductor device includes the steps of forming an insulation layer in a semiconductor substrate, forming an opening on a predetermined surface portion of the semiconductor substrate, forming a polysilicon layer on the insulation layer including the opening, and etching back the polysilicon layer using a compound gas mixed by a first gas including fluorine, and a second gas including one selected from nitrogen and oxygen. The method decreases the etching loading effect and the plug loss, thereby improving the reliability of the semiconductor device.

Abstract: A method for forming a contact plug. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening that exposes a thin layer of native oxide. A first and a second conformal doped polysilicon layer are formed over the opening. The first doped polysilicon layer has a dopant concentration greater than that of the second doped polysilicon layer. A third doped polysilicon layer that also fills the opening is formed over second doped polysilicon layer. Dopant concentration of the third doped polysilicon layer is smaller than the second doped polysilicon layer. Last, the first, the second and the third doped polysilicon layer are annealed.

Abstract: A method for fabricating a semiconductor device improves step coverage and resistivity. The method includes the steps of forming a doped silicon layer on a substrate, forming a silicide layer containing more metal atoms than silicon atoms on the doped silicon layer, and heat treating in nitrogen to form a second silicide layer having a tetragonal phase crystal structure and a silicon nitride film on the top surface of the second silicide layer.

Abstract: A process for forming a low resistance, titanium disilicide layer, on regions of a MOSFET device, has been developed. The process features the deposition of a capping, silicon oxide layer, on first phase, high resistance, titanium disilicide regions. The capping, silicon oxide layer, featuring a compressive stress, reduces the risk of titanium disilicide regions, formed with a tensile stress, from adhesion loss, or peeling, from underlying regions of the MOSFET device, such as from the top surface of a narrow width, polysilicon gate structure. In addition the capping silicon oxide layer protects underlying titanium disilicide regions from the ambient used during the anneal cycle used to convert the first phase, high resistance, titanium disilicide region, to the second phase, low resistance, titanium disilicide region.

Abstract: There is provided a method for smoothing the surface of undoped polysilicon regions of a CMOS structure, primarily gate regions. A direct HPD-CVD argon sputter is used improve the surface roughness by a factor of more than 50%. The argon plasma sputter may be used either alone or in conjunction with a thin capping layer of oxide, nitride or oxynitride. The devices manufactured using the process exhibit excellent electrical characteristics and improved reliability compared to devices made using conventional manufacturing processes.

Abstract: This invention provides a method for forming a self aligned contact plug with low contact resistance in a semiconductor device using a two step process of (1) forming a high temperature polysilicon film and (2) forming a furnace doped polysilicon layer. The process begins by providing a substrate structure, having a first gate structure and a second gate structure thereon and having a contact area between the first gate structure and the second gate structure. An inter level dielectric layer is formed over the first gate structure and the second gate structure. The interlevel dielectric layer is patterned to form a self aligned contact opening over the contact area. Impurity ions are implanted into the substrate structure through the self aligned contact opening to form source and drain regions. In the key steps, a high temperature polysilicon film is formed over the source and drain regions, and a furnace doped polysilicon layer is formed over the high temperature polysilicon film.

Abstract: A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

Abstract: A method for fabricating salicide devices over a substrate is described. The substrate has a gate structure pair in which a first gate structure comprises a first gate and a first stuffed film located on the first gate, and a second gate structure comprises a second gate and a second stuffed film located on the first gate. A first spacer is formed on the sidewall of the first gate structure. A second spacer is formed at the sidewall of the second gate structure. The first and the second stuffed films are removed. The second spacer is etched back so as to form a third spacer lower than the second gate. Salicide layers are formed upon the first and the second gates.

Abstract: A method for fabricating a low resistivity polymetal silicide conductor/gate comprising, the steps of forming a polysilicon (66) over a gate oxide (64) followed by protection of the polysilicon (66) with a sacrificial material (68), is disclosed. Gate sidewalls (70) are created to protect the sides of the polysilicon (66) and the sacrificial material (68), followed by stripped the sacrificial material (68) to expose the top surface of the polysilicon (66). Next, a diffusion barrier (76) is deposited over the exposed polysilicon (66) and a metal layer (78) is selectively grown on the diffusion barrier (76) to form a gate contact and conductor. Finally, a dielectric layer (80) is deposited over the selectively grown metal layer (78), the sidewalls (70) and the gate oxide (64).

Abstract: An improved semiconductor device which prevents a short circuit between a wiring layer and a semiconductor substrate, caused by the penetration of a contact hole, will be provided. A lower conducting layer is formed on a second interlayer insulating film. A third interlayer insulating film covers lower conducting layer. A contact hole is formed in third interlayer insulating film in order to connect an upper conducting layer and lower conducting layer. A stopper layer of silicide or metal is formed below contact hole between the surface of a semiconductor substrate and lower conducting layer.

Abstract: This invention provides a method for forming a self aligned contact using a reverse self aligned contact etch process. A substrate structure is provided having conductive structures thereon. The conductive structures can be any of a number of structures including, but not limited to: floating gate transistors, capacitors, word lines, or a combination thereof. The substrate structure also has doped regions thereon adjacent to one or both sides of the conductive structures. A polysilicon layer is formed over the conductive structures and the doped regions. A photoresist mask is formed over the polysilicon layer having openings over the conductive structures. The polysilicon layer is etched through the openings in the photoresist mask and stopping on the hard masks to form self aligned contacts over the doped regions. A dielectric layer is formed over the self aligned contacts and the conductive structures. The dielectric layer and the self aligned contacts are planarized.

Abstract: A method of fabricating a self-align-contact is provided. A first gate and a second gate are formed on a semiconductor substrate. A spacer is formed on the sidewalls of the first gate and the second gate, and a source/drain region is formed between the first gate and the second gate. A dielectric layer is formed on the first gate, the second gate, the source/drain region, the spacer, and the semiconductor substrate. A self-align-contact opening is formed in the dielectric layer to expose the source/drain region. A metal silicide layer is formed on the source/drain region. A first conductive layer, such as doped polysilicon, is formed on the metal silicide layer and in the self-align-contact opening. A second conductive layer is formed on the first conductive layer, and the first conductive layer and the second conductive layer are patterned.

Abstract: The present invention is directed to a method of making a transistor having a very short channel length. The method generally comprises forming a plurality of process layers above a surface of a semiconducting substrate, one of the process layers being comprised of a gate dielectric material and another of the process layers being comprised of a gate conductor material. The method further comprises patterning the plurality of process layers to define an opening and forming a first sidewall spacer in the opening adjacent at least the process layer comprised of a gate conductor material. The method continues with the formation of a gate conductor mask by oxidation of a portion of at least one of the process layers other than those layers comprised of a gate dielectric material and the gate conductor material.

Abstract: A retardation layer of a copper damascene process and the fabrication method thereof, to replace the conventional barrier layer with a laminated layer. The laminated layer combines the conventional barrier layer with a porous layer, wherein the porous layer can be formed either above or below the barrier layer to improve the retardation of the copper atom diffusion. Preferably, the porous layer is formed above the barrier layer.

Abstract: A method of fabricating a buried contact avoids high resistance at a junction by forming a polysilicon layer in a trench. Thus, the current passage is not cut by the trench. The resistance of the trench junction is decreased.

Abstract: A method for a salicide process where S/D silicide contacts are formed in a separate silicide step than the gate silicide contacts. Preferably, TiSi.sub.2 is formed on S/D regions and TiSi.sub.2 or CoSi.sub.2 is formed on Poly electrodes (lines or gates) by etching back a sidewall spacer on the poly electrodes. The invention has two silicide steps. The TiSi.sub.2 is formed over the S/D regions while the gate electrode is protected by a silicon nitride Cap layer. Next, an ILD layer formed over the S/D regions. The interlevel dielectric (ILD) layer, cap layer and spacers on the sidewalls of the gate electrodes are etched back. The invention has two embodiments for the composition of the spacers. In a second silicide step, Titanium silicide (TiSi.sub.x or TiSi.sub.2) or Cobalt silicide (CoSi.sub.x or CoSi.sub.2) is formed on the top and sidewalls of the electrodes. A key feature of the invention is that the gate contact silicide is formed on the top and sidewalls of the electrodes.

Abstract: A process for forming a modified polysilicon plug structure, used to connect a bit line structure, of a semiconductor memory device, to an underlying source and drain region, of a transfer gate transistor, has been developed. The process features the formation of a dual shaped opening in an insulator layer, comprised of a wide, upper opening, overlying a narrower, lower opening, which exposes the top surface of a source and drain region. Polysilicon deposition and patterning result in the formation of the modified polysilicon plug structure, comprised of a wide polysilicon trench shape, in the upper opening in the insulator layer, and an underlying, narrower polysilicon plug, in the lower opening, in the insulator layer, with the narrow polysilicon plug contacting the underlying source and drain region. An overlying bit line structure is formed, contacting the top surface of the underlying, polysilicon trench shape, exposed in a bit line via hole.

Abstract: A method for making interlevel contacts having low contact resistance (R.sub.c) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi.sub.2) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide interconnecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings.

Abstract: A method is disclosed for providing a self-aligned silicide strap for connecting thin polysilicon layers (poly-1 and poly-2, etc.) separated by non-conducting gaps. A butting contact opening to the layers is formed in an overlying insulating layer. The contact exposes the poly-1 and poly-2 layers. A thin polysilicon layer (poly-3) is then deposited over the insulating layer and into the contact. This is followed by deposition of a refractory metal layer. The poly-3 layer should be thin enough that, alone, it cannot supply enough silicon to support full silicidation of the refractory metal layer. The structure is next sintered so that a silicide strap is formed in the contact opening and across exposed portions of the poly-1 and poly-2 layers. The ratio of silicon to titanium in regions over the insulating layer is lower than that in the strap, such that these more metallic regions may be selectively removed.

Abstract: A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.