Abstract: A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces.

Abstract: Nanolithographic deposition of metallic nanostructures using coated tips for use in microelectronics, catalysis, and diagnostics. AFM tips can be coated with metallic precursors and the precursors patterned on substrates. The patterned precursors can be converted to the metallic state with application of heat. High resolution and excellent alignment can be achieved.

Abstract: Systems and methods are provided for a scalable high-performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric constant (keff) such that a programming pulse voltage is scalable with Vdd. One aspect of the present subject matter is an antifuse device that is positioned or coupled between a first metal level and a second metal level. One embodiment of the antifuse device includes a porous antifuse dielectric layer, and at least one injector Silicon-Rich-Insulator (SRI) layer in contact with the porous antifuse dielectric layer. In one embodiment, the porous antifuse dielectric layer includes SiO2 formed with air-filled voids. In one embodiment, the at least one injector SRI layer includes two injector Silicon-Rich-Nitride layers that sandwich the porous antifuse dielectric layer. Other aspects are provided herein.

Abstract: A substrate having a built-in semiconductor apparatus includes: a semiconductor apparatus which comprises a first semiconductor chip having a first electrode pad formed on a main surface thereof, a protruding portion which is in contact with the first semiconductor chip and protrudes from a side surface of the first semiconductor chip to the outside, an apparatus wiring portion which is provided so as to extend from the first electrode pad onto a surface of the protruding portion, a conductive portion which is in connected with the apparatus wiring portion and provided on the apparatus wiring portion, and a sealing layer which covers the main surface and the surface of the protruding portion so as to expose a top face of the conductive portion; an insulating layer in which the semiconductor apparatus is embedded; an external terminal provided on the insulating layer; and a substrate wiring portion which electrically connects the conductive portion with the external terminal.

Abstract: A method of forming a flash memory cell includes providing a substrate, forming an oxide layer over the substrate, forming a polysilicon floating gate over the oxide layer including providing a bottom seed layer having microcrystalline polysilicon, providing an upper amorphous silicon layer over the bottom seed layer, and annealing the upper amorphous silicon layer, providing an inter-poly dielectric layer over the floating gate, and forming a polysilicon control gate over the inter-poly dielectric layer.

Abstract: A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.

Abstract: The present invention relates to a method of making a nanoscale electronic device wherein said device comprises a gap between about 0.1 nm and about 100 nm between at least two conductors, semiconductors or the combination thereof. The method features complete assembly of electrical contacts before addition of a molecular component thereby preserving the integrity of the molecular electronic component and maintaining a well-formed gap. The gap produced is within the nanoscale regime, has uniform width and is further characterized by surfaces that are uniformly smooth.

Abstract: Systems and methods are provided for a scalable high-performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric constant (keff) such that a programming pulse voltage is scalable with Vdd. One aspect of the present subject matter is an antifuse device that is positioned or coupled between a first metal level and a second metal level. One embodiment of the antifuse device includes a porous antifuse dielectric layer, and at least one injector Silicon-Rich-Insulator (SRI) layer in contact with the porous antifuse dielectric layer. In one embodiment, the porous antifuse dielectric layer includes SiO2 formed with air-filled voids. In one embodiment, the at least one injector SRI layer includes two injector Silicon-Rich-Nitride layers that sandwich the porous antifuse dielectric layer. Other aspects are provided herein.

Abstract: This invention is a process for forming an effective titanium nitride barrier layer between the upper surface of a polysilicon plug formed in a thick dielectric layer and a platinum lower capacitor plate in a dynamic random access memory which is being fabricated on a silicon wafer.

Abstract: An upper capacitor electrode of a trench capacitor of a DRAM memory cell is formed at least in part as a result of a plurality of metal-containing layers being deposited one on top of another and in each case being conditioned after they have been deposited. In this way, the internal stress of the electrode layer can be reduced, and therefore a breaking strength and a resistance to leakage currents of the trench capacitor can be increased.

Abstract: The surface of a solder ball and a conductive wire for a semiconductor package are coated with a predetermined colorant. Various colorants may be used according to the diameter and metal composition of the solder ball and the conductive wire. The colorant is formed by mixing organic compound and dye of a predetermined color. Examples of organic compounds excellent in physicochemical bonding with metal include benzotriazole, alkylimidazole and benzimidazole. The solder ball is fabricated by coating an organic compound of a predetermined color on the surface of a typical solder ball. The conductive wire is fabricated by coating an organic compound of a predetermined color on a general conductive wire between heat process and winding. Moreover, the solder ball is evaporated in a reflowing step after bumped via flux and the conductive wire is evaporated in a wire bonding step so that the solder ball and the conductive wire return to their unique colors.

Abstract: The electrode structure of this invention includes a silicon-containing film containing silicon as a principal constituent; a barrier metal layer of titanium nitride rich in titanium as compared with a stoichiometric ratio formed on the silicon-containing film; and a metal film with a high melting point formed on the barrier metal layer.

Abstract: An integrated circuit has a multi-layer stack such as a gate stack or a digit line stack disposed on a layer comprising silicon. A conductive film is formed on the transition metal boride layer. A process for fabricating such devices can include forming the conductive film using a vapor deposition process with a reaction gas comprising fluorine. In the case of a gate stack, the transition metal boride layer can help reduce or eliminate the diffusion of fluorine atoms from the conductive film into a gate dielectric layer. Similarly, in the case of digit line stacks as well as gate stacks, the transition metal boride layer can reduce the diffusion of silicon from the polysilicon layer into the conductive film to help maintain a low resistance for the conductive film.

Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.

Abstract: Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.

Abstract: The present invention provides a method for forming a contact plug in a semiconductor device capable of preventing an increase of contact resistance even if the contact size becomes smaller and degradation of a step coverage property and of suppressing a decrease of uniformity in the contact resistance. The inventive method includes the steps of: a method for forming a contact plug in a semiconductor device, comprising the steps of: forming a contact hole by etching an insulating layer on a substrate; forming a first silicon film with a first doping concentration on the substrate in the contact hole so that the contact hole is partially filled; flushing a doping gas on a surface of the first silicon film; and forming a second silicon film having a second doping concentration higher than the first doping concentration on the first silicon film until filling the contact hole.

Abstract: The invention comprises methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry. In one implementation, a method of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry includes forming a conductive metal interconnect layer over a substrate. An insulating dielectric mass is provided about the conductive metal interconnect layer. The insulating dielectric mass has a first dielectric constant. At least a majority of the insulating dielectric mass is etched away from the substrate. After the etching, an interlevel dielectric layer is deposited to replace at least some of the etched insulating dielectric material. The interlevel dielectric layer has a second dielectric constant which is less than the first dielectric constant.

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

Abstract: The invention is directed to a fabrication method of copper interconnects using dual damascene processing. Using silicon to provide an active surface, palladium can be selectively deposited on silicon by an immersion plating technique. After palladium deposition (about 1000 Å thick), either a layer of cobalt phosphorus or alloy cobalt/nickel phosphorus or nickel phosphorus is deposited on the palladium layer using an electroless plating technique. This cobalt phosphorus, cobalt/nickel phosphorus alloy, or nickel phosphorus layer serves as a copper diffusion barrier. The via and trenches are filled with copper by an electroless copper plating method and CMP is used to remove the excess copper and planarize-/-polish the copper/dielectric surface.

Abstract: To provide a technique for manufacturing a wiring line having a low resistance and a high heat resistance so as to make an active matrix type display device larger and finer. The wiring line is constructed of a laminated structure of a refractory metal, a low resistance metal and a refractory metal, and the wiring line is further protected with an anodized film. As a result, it is possible to form the wiring line having the low resistance and the high heat resistance and to form a contact with an upper line easily.

Abstract: A butting contact structure using a silicide to connect a contact region and a conductor and a method to manufacture the same are disclosed. The method comprises the steps of: forming a first area having a first conduction type and a second area having a second conduction type which is adjacent to the first area; forming a silicide to be in contact with the first and second areas; and depositing an insulating layer covering the first portion of the silicide; etching a contact window in the insulating layer for exposing a surface of the silicide; and forming a conductor filling in the contact window. The difficulty from the reduction of the contact window is overcome without altering the manufacturing process and the layer of masks. Moreover, the density and performance of the semiconductor element is improved.

Abstract: A method is provided for forming a conductive wire of a semiconductor device using, for example, a damascene process. A conductive wire, such as a metal wire, is formed, based on a notching phenomenon which occurs when the etching selectivity between a polycrystalline silicon layer and a lower film is approximately 5 to 500:1.

Abstract: A method of fabricating contact holes on a semiconductor chip with a plurality of gates and a first mask layer includes filling a dielectric layer into the inter-gate space of two gates, polishing the dielectric layer until the surface of the dielectric layer is coplanar with the gates, depositing a second mask layer, etching the second mask layer to form a bit line opening in an array area and simultaneously forming a gate opening and a substrate opening in a periphery area, removing a portion of the dielectric layer through the bit line opening and the substrate opening to form a bit line contact hole and a substrate contact hole, filling a metal layer into the bit line contact hole and the substrate contact hole, and etching the first mask layer through the gate opening to form a gate contact hole.

Abstract: A method and system for fabricating a capacitor utilized in a semiconductor device. A salicide gate is designated for use with the semiconductor device. A self-aligned contact (SAC) may also be configured for use with the semiconductor device. The salicide gate and the self-aligned contact are generally in a memory cell area of the semiconductor device to thereby permit the efficient shrinkage of memory cell size without an additional mask or weakening of associated circuit performance. Combining, the self-aligned contact and the salicide gate in the same memory cell area can effectively reduce gate resistance.

Abstract: A method of forming a capacitor includes forming a first capacitor electrode over a substrate. A substantially crystalline capacitor dielectric layer is formed over the first capacitor electrode. The substrate with substantially crystalline capacitor dielectric layer is provided within a chemical vapor deposition reactor. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the substantially crystalline capacitor dielectric region, and the polysilicon is formed into a second capacitor electrode.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low parasitic capacitance and a halo ion-implanted region in which a short channel effect can be effectively suppressed. The method for manufacturing the device is capable of performing high angle ion implantation without extending gate-to-gate space.

Abstract: This invention relates to a method of filling a via or recess in a semiconductor substrate including: (i) depositing or forming a sacrificial layer on a functional dielectric layer, (ii) etching a via or recess through the sacrificial and functional layers; (iii) depositing metal onto the substrate by: (iv) lifting off or ablating the metal deposited on the surface of the sacrificial layers; (v) repeating steps (iii) and (iv) until the vias or recesses are at least full of metal; and (vi) removing any remaining sacrificial layer and any excess metal.

Abstract: A semiconductor device comprises a base semiconductor substrate (201) having an edge area (120) which surrounds an element forming area (110), a buried oxide film (202) provided over the base semiconductor substrate (201) in the element forming area (110), an element forming semiconductor substrate (203) provided over the buried oxide film (202).

Abstract: According to one embodiment, a method of planarizing of a surface of a semiconductor substrate is provided. A copper layer is inlaid in a dielectric layer of the substrate. The semiconductor substrate is disposed opposite to a polishing pad and relative movement provided between the pad and the substrate. An electrolytic slurry containing abrasive particles is flowed over the substrate or the pad. A voltage is applied between the polishing pad and the substrate to perform electropolishing of the substrate. The rate of chemical mechanical polishing is controlled by the down force applied to a polishing head urging the substrate against the polishing pad.

Abstract: A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

Abstract: A method for providing self aligned contacts for a trench power MOSFET is disclosed. The method includes, etching trenches in a substrate through a mask of silicon nitride deposited on an oxide layer, forming a gate oxide layer on the walls of the trenches, applying polysilicon to fill the trenches and to cover the surface of the mask of silicon nitride, removing the polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus.

Abstract: A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon nitride in two steps. A tilted ion implantation step is performed to implant nitrogen ions into the polysilicon residue to rich nitrogen containing of the polysilicon residue. A nitrogen anneal step is subsequently performed to completely convert the rich nitrogen containing polysilicon residue into silicon nitride that can eliminate the conductivity of the polysilicon residue and prevent conventional oxygen encroachment occurring.

Abstract: A method for forming a microelectronics device is disclosed. In one embodiment, the method includes depositing a conductive structure on a substrate. A first layer comprising silicon and nitrogen is formed on the substrate. A second layer comprising silicon and nitrogen is then formed on the first layer. The nitrogen to silicon ratio in the first layer is greater than the nitrogen to silicon ratio in the second layer.

Abstract: An embodiment of the present invention teaches a method used in a semiconductor fabrication process to form a memory cell in a semiconductor device comprising the steps of: subjecting a layered structure comprising a silicon gate insulating layer, a conductively doped polysilicon gate layer and a refractory metal silicide gate film to a thermal processing step; forming a sheet resistance capping layer directly on the refractory metal silicide film during at least a period of time of the thermal processing step, the sheet resistance capping layer forming a substantially uniform surface on the refractory metal silicide film; patterning and etching the layered structure to form the transistor gate; forming source and drain regions aligned to opposing sides of the transistor gate and formed into an underlying silicon substrate; and forming a storage capacitor (such as a stacked capacitor or a container cell) connecting to one of the source and drain regions.

Abstract: A semiconductor device having a pad for electrical connection provided on a semiconductor substrate, a first insulating film with which a surface of the semiconductor substrate is coated and having an opening to which the pad is exposed, a conductive film joined to the pad on a bottom surface of the opening of the first insulating film and extending to a surface of the first insulating film outside the opening, a second insulating film with which the conductive film is coated and having an opening to which a part of the conductive film is exposed, and a connecting member arranged so as to be joined to the conductive film inside the opening of the second insulating film.

Abstract: A method and apparatus for component to substrate assembly permits in situ reflow of a flip chip (or other suitable component) in a manner which promotes proper settling of the component as solder begins to flow at the contact points between the component and the substrate. The component is heated and held by a pick-up head while applying downforce that serves to level the component. The initiation of solder reflow can be detected with the pick-up head by sensing a decrease in the downforce. Downforce applied to the component with the pick-up head is then decreased and the retention mechanism holding the component is released, freeing the component from the pick-up head and permitting the component to properly self-center using the liquid solder's surface tension.

Abstract: A network of electrically conductive plate contacts is provided within the structure of a DRAM chip to enable storage of non-zero voltage levels in each charge storage region. An improved cell or top plate contact provides low contact resistance and improved structural integrity making the contact less prone to removal during subsequent processing steps. A top plate conformally lines a container patterned down into a subregion. A metal contact structure comprises a waist section, a contact leg, and an anchor leg. The contact leg makes contact to the top plate within the container interior. The waist section joins the top of the contact leg to the top of the anchor leg and extends over the edge of the top plate. The anchor leg extends downward through the subregion adjacent to but spaced from the container to anchor the structure in place and provide structural integrity.

Abstract: A gate oxide layer, a first polysilicon layer, a polycide layer and a first interpolysilicon oxide (IPO) layer are sequentially formed on a semiconductor substrate. The first IPO layer, the polycide layer and the first polysilicon layer are then etched to form a gate and a bottom electrode plate. A second IPO layer and a polysilicon layer are then formed on the substrate and are etched to form a conductive wire and a top electrode plate thereafter. Finally, a spacer is formed, and an ion implantation process and a self-aligned suicide (salicide) process are performed to complete a mixed mode process for the formation of the conductive wire, a metal-oxide-semiconductor (MOS) transistor and a capacitor structure.

Abstract: A novel gate structure and a method of forming the same for a self-aligned contact on a semiconductor substrate. The method includes forming a gate oxide layer on the semiconductor substrate. Then a first conductive layer is formed on the gate oxide layer. Next, a second conductive layer, preferably a refractory metal silicide (e.g. WSix), is formed overlying the first conductive layer. A capping layer is formed overlying the second conductive layer. Then the capping layer is etched to form a patterned capping layer having a lower outside corner. An upper portion of the second conductive layer is selectively dry etched laterally to form a lateral recess under the capping layer to increase etch margin. A lower portion of the second conductive layer is then etched anisotropically down to the first conductive layer along a sidewall approximately vertically aligned with the lower outside corner of the patterned capping layer.

Abstract: An integrated circuit is described having a substrate, a power transistor in a first region of the substrate, and a plurality of barrier regions of the substrate around the first region. Each barrier region includes a barrier transistor and at least one substrate connection connecting the barrier transistor to at least one floating region of the substrate adjacent the barrier region. During operation of the integrated circuit, the floating regions and the barrier transistors operate to inhibit operation of parasitic devices associated with the power transistor.

Abstract: A method for forming within a substrate employed within a microelectronics fabrication an electrical interconnection cross-over bridging between conductive regions separated by non-conductive regions formed within the substrate. There is formed over a substrate provided with conductive and non-conductive regions a blanket dielectric layer and a blanket polysilicon layer. After patterning the polysilicon and dielectric layers. A portion of the dielectric layer at the periphery of the polysilicon layer is etched away, leaving a gap between the polysilicon patterned layer and the underlying substrate contact region. There is formed over the substrate a layer of refractory metal and after rapid thermal annealing, there is formed a surface layer of refractory metal silicide over the surfaces of the polysilicon layer and within the gap between the polysilicon layer and the substrate, completing the electrical connection.

Abstract: The invention encompasses methods of forming silicide interconnects over silicon comprising substrates. In one implementation, a first layer comprising a metal and a non-metal impurity is formed over a region of a silicon comprising substrate where a silicide interconnection is desired. An elemental metal comprising second layer is formed over the first layer. The substrate is annealed to cause a reaction between at least the elemental metal of the second layer and silicon of the substrate region to form a silicide of the elemental metal of the second layer. In another considered aspect, a method of forming a silicide interconnect over a silicon comprising substrate includes providing a buffering layer to silicon diffusion between a refractory metal comprising layer and a silicon containing region of a substrate.

Abstract: The present invention relates to a method for removing polysilicon layers used as a hard mask from contact holes without damaging the semiconductor substrate during the etching process. The present invention according to the present invention comprises the steps of: forming a nitride layer on a contact region to be contacted with a conducting layer; forming an interlayer insulation layer on the nitride layer, wherein the interlayer insulation layer has a different etching rate from the nitride layer so that the nitride layer acts as an etching barrier layer for the interlayer insulation layer; forming a polysilicon pattern on the interlayer insulation layer; etching the interlayer insulation layer using the polysilicon pattern as an etching mask, whereby a first opening to expose a portion of the nitride layer is formed; and etching the exposed nitride layer, thereby forming a second opening to expose the contact region.

Abstract: Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented, after silicidation and removal of any unreacted nickel, by treating the exposed surfaces of the silicon nitride sidewall spacers with a HDP plasma to oxidize nickel silicide thereon forming a surface layer comprising silicoin oxide and silicon oxynitride. Embodiments include treating the silicon nitride sidewall spacers with a HDP plasma to form a surface silicon oxide/silicon oxynitride region having a thickness of about 40 Å to about 50 Å.

Abstract: A method of de-oxidizing a surface onto which a refractory metal or molecule which contains a refractory metal atom will be adhered. The method utilizes a plasma which includes a gas such as argon, nitrogen, helium or hydrogen, or a mixture of any of the foregoing, to remove oxygen molecules from the surface to which adherence of the refractory metal is desired. Radicals in the plasma coat the surface to prevent further oxidation thereof. The method also includes techniques for depositing refractory metals onto a surface such as a substrate or layer of semiconductor material on which integrated circuitry has been fabricated.

Abstract: A method of forming spaces between polysilicon lines can include patterning structures having top SiON layers and bottom amorphous carbon layers where the structures are located over a polysilicon layer and are separated by a first width, forming amorphous carbon spacers along lateral side walls of the patterned structures, etching apertures into the polysilicon layer not covered by the amorphous carbon spacers and the patterned structures where the apertures in the polysilicon layer between adjacent patterned structures have a second width, and ashing away the amorphous carbon spacers and the patterned structures. The second width is less than the first width.

Abstract: An integrated raised contact formation method to achieve ultra shallow junction devices is described. Semiconductor device structures are provided in and on a substrate and covered with a dielectric layer. The dielectric layer is etched through to form first openings to the substrate. The surface of the substrate exposed within the first openings is amorphized. A silicon layer is selectively formed on the amorphized substrate surface. Then, ions are implanted into the silicon layer to form raised contacts. Thereafter, the dielectric layer is etched through to form second openings to gates. The first and second openings are filled with a conducting layer to complete formation of contacts in the fabrication of an integrated circuit device.

Abstract: A semiconductor device manufactured by cleaning without dissolving W, Ti, or TiN even if these metallic materials are exposed on the substrates to be cleaned, and a method for manufacturing such a semiconductor device. Impurities present on a silicon substrate can be removed while controlling the etching of a tungsten film exposed on the surface of a silicon substrate, by dipping and cleaning the silicon substrate in one or a plurality of chemical solutions selected from a group consisting of HF, HCl, and NH4OH, under the condition that the surface of the silicon substrate is entirely covered with a tungsten film. After dry etching for patterning the tungsten film and the barrier metal, impurities present on a silicon substrate can be removed while controlling the etching of the tungsten film and the barrier metal exposed on the surface of a silicon substrate, by dipping and cleaning the silicon substrate in one or a plurality of chemical solutions selected from a group consisting of HCl and NH4OH.

Abstract: A multi-level memory cell capable of storing two or three bits of digital data occupies only four lithographic squares and requires only one or two logic level voltage sources, respectively. High noise immunity derives from integration of the multi-level signal in the memory cell directly from logic level digital signals applied to two capacitors (as well as the bit line for the eight level mode of operation) by using capacitors having different values in order to avoid digital-to-analog conversion during writing. The capacitors can be simultaneously written and read to reduce memory cycle time. Transistor channels and capacitor connections are formed on adjacent semiconductor pillars using plugs of semiconductor material between pillars as common gate structures and connections. Opposite surfaces of the pillars also serve as storage nodes with common capacitor plates formed by conformal deposition between rows of plugs and pillars.

Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.