Abstract: A MOS-technology power device integrated structure includes a first plurality of elongated doped semiconductor stripes of a first conductivity type formed in a semiconductor layer of a second conductivity type, each including an elongated source region of the first conductivity type, an annular doped semiconductor region of the first conductivity type formed in the semiconductor layer and surrounding and merged with the elongated stripes, insulated gate stripes extending over the semiconductor layer between adjacent elongated stripes, a plurality of conductive gate fingers extending over and electrically connected to the insulated gate stripes, and a plurality of source metal fingers, each one extending over a respective elongated stripe and contacting the elongated stripe and the respective elongated source region, so that the source metal fingers and the conductive gate fingers are interdigitated.

Abstract: A method of a method of fabricating a contact. A substrate having a plurality of gates and a plurality of lightly doped source/drain regions is provided. A dielectric layer is formed and patterned to form a self-align contact window to expose a first lightly doped source/drain region of said lightly doped source/drain regions, and to form a first spacer on a side wall of a first gate of said gates simultaneously. An ion implantation is performed by using the first spacer as a mask, so that a first heavily doped source/drain region is formed in the first lightly doped source/drain region. A doped poly-silicon layer is formed over the substrate, and a metal silicide layer is formed on the doped poly-silicon layer. The doped poly-silicon and the metal silicide layer are patterned to form a self-align contact.

Abstract: A process for completely removing TiN residue existing outside contact windows is described: electrical elements are formed on a silicon substrate, an insulating layer is then formed over the entire silicon substrate, next, the insulating layer is partially etched to form metal contact windows, a TiN barrier layer and a tungsten metal layer are then sequentially deposited overlaying the insulating layer and filling into the metal contact windows, two stage CMP process is performed to remove the metal and TiN barrier layers exposed outside the contact windows respectively, finally, an dry etching step employing HCl/Cl.sub.2 plasmas is performed to make sure there is not any TiN residues left outside contact windows.

Abstract: Method for fabricating a semiconductor device, is disclosed, which is suitable for improving a resistivity, including the steps of forming a silicon layer on a substrate, forming a crystalline metal silicide layer on the silicon layer, forming an amorphous metal silicide layer by injecting ions into the crystalline metal silicide layer, and crystallizing the amorphous metal silicide by heat treating the amorphous metal silicide.

Abstract: The degradation of integrity of the gate oxide in a CMOS transistor due to the formation of a tungsten silicide strapping layer on the polycrystalline silicon gate as a result of the migration of fluorine atoms from the tungsten hexafluoride used to form the tungsten silicide is reduced by increasing the dopant concentration of the polycrystalline silicon layer thereby to form dopant atoms in the grain boundaries of the polycrystalline silicon to block the migration of fluorine through the polycrystalline silicon to the underlying gate oxide. By preventing fluorine from reaching the gate oxide in this manner, the degradation of the gate oxide due to the replacement of oxygen by fluorine is decreased.

Abstract: Contact holes are formed in a dielectric layer. An undoped polysilicon layer is formed on the dielectric layer and along the surface of the contact holes. A first photoresist is patterned on the dielectric layer to cover a region for forming P+ contact. Then, an ion implantation is carried out. A second photoresist is formed over the n conductivity type impurity regions in the cell area and the n+ conductive type impurity region in peripheral area. An ion implantation is then performed to dope ions into the substrate to form a p+ conductivity type impurity region in the peripheral area for PMOS. A titanium layer and a titanium nitride layer are respectively formed on the surface of the contact holes. Subsequently, a tungsten layer is refilled in to the contact holes. An etching back process or chemical mechanical polishing (CMP) is employed to removed a portion of the tungsten layer to form a plurality of tungsten plugs.

Abstract: A method for increasing landing pad area is disclosed. Firstly, providing a fundamental structure, wherein shallow trench isolation (STI) is used and acting as an electrical isolation inside of substrate. Moreover, there are at least two gates with an isolation layer on top of the substrate and covered with a dielectric layer. Between the neighboring gates there is a contact hole that penetrates the dielectric layer from the top of the dielectric layer to the substrate. Taking this fundamental structure as the starting point for forming a conductor within the contact hole. Etching back the dielectric layer and exposing its top surface and a portion of sidewalls. Finally, a protection layer on top of the exposed portion of sidewalls of the conductor is formed in order to expand the landing pad area. After all, one would still be able to increase the landing pad area even though the distance between two gates is rather small.

Abstract: A new method of removing impurities and moisture from the surface of a wafer and thereby preventing polysilicon residue is described. A dielectric layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the dielectric layer. A hard mask layer is deposited overlying the polysilicon layer and patterned to form a hard mask. The wafer is cleaned whereby moisture and impurities form on the surfaces of the hard mask and the polysilicon layer. Thereafter, the wafer is heat treated whereby the moisture and impurities are removed. Thereafter, the polysilicon layer is etched away where it is not covered by the hard mask to complete formation of a polysilicon line on a wafer in the fabrication of an integrated circuit.

Abstract: A semiconductor memory device suitable for forming a capacitor using a high dielectric film for a highly integrated semiconductor device includes a semiconductor substrate, an insulating film having a contact hole, the insulating film being over the semiconductor substrate, a conductive film on the semiconductor substrate through the contact hole, the conductive film having a top portion acting as a diffusion barrier, a first electrode over the conductive films, a dielectric film over the first electrode, and a second electrode over the dielectric film.

Abstract: A semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening includes, a) providing a node location and a plug molding layer outwardly thereof; b) providing a contact opening through the plug molding layer to the node location; c) providing a first layer of semiconductive material over the molding layer to within the contact opening, the first layer thickness being less than one-half the contact opening width to leave a first remaining opening, the first layer having an average conductivity enhancing dopant concentration from 0 atoms/cm.sup.3 to about 5.times.10.sup.18 atoms/cm.sup.3 ; d) after providing the first layer, increasing the average conductivity enhancing dopant concentration of the first layer to greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.

Abstract: Two approaches are proposed for forming an inter-metal dielectric layer with improved metal damage characteristics. This is of utmost importance for sub-quarter micron feature sizes, where thin metal lines are particularly susceptible to damage and where the HDP-CVD processes, which are used because of their excellent gap filling characteristics, are apt to cause metal damage. In approach one, a partially processed semiconductor wafer is provided containing a blanket layer of metal. A blanket dielectric layer is deposited. This layer could, for example, be silicone oxide, silicon nitride or silicone oxynitride; and the deposition process could be APCVD, LPCVD, 03-TEOS CVD or PECVD. The layer thickness could be in the range from about 0.01 microns to about 0.2 microns. Patterning and etching the blanket metal layer and protective dielectric layer results in the desired metal structure, except with a dielectric cap. The HDP-CVD insulating layer can now be deposited without concern for metal damage.

Abstract: An improved method for making an integrated circuit that includes forming a conductive layer on a substrate, then forming a dielectric layer comprising a polymer on the conductive layer. After forming the dielectric layer, a layer of photoresist is patterned to define a region to be etched. An etched region is then formed through the dielectric layer while simultaneously removing the layer of photoresist.

Abstract: On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact hole which extends to reach the diffusion layer of the opposite conductivity type. A contact plug is provided in the contact hole. The contact plug fills the contact hole and comprises a first silicon layer of the opposite conductivity type directly connected to the diffusion layer of the opposite conductivity type, a silicon-germanium alloy layer of the opposite conductivity type directly contact to the first silicon layer, and a second silicon layer of the opposite conductivity type directly contact to the silicon-germanium alloy layer. Wiring is provided on the surface of the insulator film in direct contact to the contact plug.

Abstract: An embodiment of the present invention teaches a method used in a semiconductor fabrication process to form a memory cell in a semiconductor device comprising the steps of: subjecting a layered structure comprising a silicon gate insulating layer, a conductively doped polysilicon gate layer and a refractory metal silicide gate film to a thermal processing step; forming a sheet resistance capping layer directly on the refractory metal silicide film during at least a period of time of the thermal processing step, the sheet resistance capping layer forming a substantially uniform surface on the refractory metal silicide film; patterning and etching the layered structure to form the transistor gate; forming source and drain regions aligned to apposing sides of the transistor gate and formed into an underlying silicon substrate; and forming a storage capacitor (such as a stacked capacitor or a container cell) connecting to one of the source and drain regions.

Abstract: A method for forming a barrier layer comprising the steps of first providing a semiconductor substrate that has a conductive layer already formed thereon. Then, a dielectric layer such as an organic low-k dielectric layer is deposited over the conductive layer and the semiconductor substrate. Next, an opening in formed in the dielectric layer exposing the conductive layer. Thereafter, a first barrier layer is deposited into the opening and the surrounding area. The first barrier layer can be a silicon-contained layer or a doped silicon (doped-Si) layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method, a low-pressure chemical vapor deposition (LPCVD) method, an electron beam evaporation method or a sputtering method. Finally, a second barrier layer is formed over the first barrier layer. The second barrier layer can be a titanium/titanium nitride (Ti/TiN) layer, a tungsten nitride (WN) layer, a tantalum (Ta) layer or a tantalum nitride (TaN) layer.

Abstract: A method of forming buried contacts in MOSFET and CMOS devices which substantially reduces the depth of the buried contact trench. A split polysilicon process is used to form the gate electrode and contact electrode. The first polysilicon layer is very thin layer of undoped polysilicon, having a thickness of less than 100 Angstroms. The second polysilicon layer is a layer of doped polysilicon having a thickness of between about 950 and 1150 Angstroms. The buried contact can be formed either using ion implantation or diffusion of impurities from the layer of doped second polysilicon into the contact region. When the metal layers are etched to form the gate electrode and contact electrode the resulting buried contact trench is less than 500 Angstroms deep.

Abstract: The method of the present invention includes forming a MOS on a semiconductor substrate. Subsequently, a silicon-rich metal silicide layer is deposited on the MOS and substrate by using chemical vapor deposition to act as a silicon material source. Then, a thermal process is carried out to separate a portion of the silicon out of the metal silicide layer, thereby forming a silicon layer on top of the gate of the MOS, source/drain. The nest step is to remove the metal suicide layer. A self-aligned metal silicide layer is formed on the silicon layer.

Abstract: In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed.

Abstract: A process for fabricating bitlines for DRAM devices having improved bitline electrical contact is disclosed. Good electrical connection for the bitline in its contact opening is secured by forming a contact interface utilizing titanium silicide. The process includes first forming contact openings revealing the source/drain regions of the transistor of the cell units followed by the formation of a polysilicon layer filling into the openings and contacting the revealed surface of the transistor source/drain regions. A tungsten silicide layer then covers the polysilicon layer, with a titanium layer further covering the tungsten silicide layer, and the polysilicon layer in the contact opening exposed out of coverage by the tungsten silicide layer due to insufficient step coverage of the tungsten silicide layer in the openings. A titanium nitride layer then covers the titanium layer, with a titanium silicide layer interfacing between the polysilicon layer and the tungsten silicide filled inside the openings.

Abstract: The method of metallization includes the steps as follows. At first, a semiconductor substrate is provided and a dielectric layer is formed over the semiconductor substrate. A portion of the dielectric layer is removed to form contact holes and a first conductive layer is formed within the contact holes and over the dielectric layer. A portion of the first conductive layer is removed to define a contact pattern. Using the first conductive layer as a mask, a portion of the dielectric layer is removed to form openings within the dielectric layer and over the first conductive layer. A second conductive layer is then formed within the openings and over the first conductive layer. To planarize the surface of the semiconductor substrate, a portion of the second conductive layer and the first conductive layer is removed to planarize to the dielectric layer.

Abstract: A semiconductor structure that includes a silicon substrate which has a top surface, a diffusion region formed in the substrate adjacent to the top surface, a polysilicon gate formed on the top surface of the substrate adjacent to but not contacting the diffusion region, an insulator layer substantially covers the polysilicon gate and the diffusion region, the layer contains a via opening therein, and an electrically conducting plug filling at least partially the via opening providing electrical communication between the polysilicon gate and the diffusion region.

Abstract: A semiconductor device (150) is formed having a first conductive member (64) overlying a field isolation region (36) that is typically less than two microns wide. Typically, the field isolation region (36) is relatively thinner compared to wider field isolation regions. The first conductive member (64) lies between the field isolation region (36) and a second conductive member (80) to shield the substrate (20). The shielding helps to increase the field threshold voltage of the field device. The invention is particularly useful in double polysilicon process flow used in forming devices operating at a potential higher than V.sub.DD. Examples of these devices include nonvolatile memories and microcontrollers having nonvolatile memory arrays.

Abstract: To provide a method for producing the semiconductor device in which contactability between a dielectric layer and a contact layer is not reduced during the formation of a metal plug, the method comprises forming a semiconductor device including a base; forming a lower conductive layer on the base; forming a dielectric layer formed on the lower conductive layer; forming an opening in the dielectric layer for electrically connecting the lower conductive layer with an upper conductive layer to be formed on the dielectric layer; forming a first contact layer formed on at least a bottom surface of the via hole and made of a single TiON layer, any portions of said first contact layer formed on the dielectric layer being removed; forming a second contact layer over an entire exposed surface of the first contact layer, depositing tungsten on the second contact layer by a chemical vapor deposition method; and removing portions of the second contact layer formed on the dielectric layer while leaving a tungsten plug and

Abstract: A method for fabricating a damascene interconnect includes the steps of depositing a metal layer of the surface of an insulating film; etching the metal layer and the insulating film to form an insulating groove; depositing a silicon layer on an upper surface on the metal layer and on each sidewall and a bottom of the insulating groove; annealing the silicon layer and the metal layer to form a silicide layer; implanting ions in the bottom of the insulating groove; and depositing an interconnect material in the insulating groove using selective chemical vapor deposition. In one embodiment, the metal layer is a titanium layer, the interconnect material is tungsten, and the implanted ions are arsenic ions.

Abstract: The present invention provides a method for preventing a polycide line situated between two dielectric layers from deformation during a reflow process for one of the dielectric layers by annealing the polycide line and thereby increasing its hardness prior to the reflow process being conducted. The annealing process can be carried out either before or after the polycide line is formed at an annealing temperature in the range between about 700.degree. C. and about 1000.degree. C. in a furnace or by a rapid thermal process.

Abstract: A natural oxide on an amorphous silicon exposed to a miniature contact hole is thermally decomposed in vacuum and an amorphous silicon is grown on the amorphous silicon without exposing to the atmosphere; the amorphous silicon is applied with heat so as to be epitaxially grown on a single crystal silicon beneath the amorphous silicon, thereby forming a conductive plug in the miniature contact hole.

Abstract: A method of making ohmic contact between a thin film polysilicon layer of a first conductivity type and a subsequently provided conductive layer includes: a) providing a semiconductor substrate having an outer region; b) providing a first insulating layer outwardly of the outer region; c) etching a first contact opening of a first diameter through the first insulating layer to the substrate outer region; d) providing conductivity enhancing dopant impurity of the first conductivity type into the substrate outer region to render the outer region electrically conductive; e) providing a thin film polysilicon layer of the first conductivity type into the first contact opening and in ohmic electrical connection with the substrate outer region; f) providing a second insulating layer outwardly of the thin film polysilicon layer and the first insulating layer; g) etching a second contact opening of a second diameter into the second insulating layer, the second contact opening overlapping with the first contact opening

Abstract: A method for forming metal plugs using fewer masks and photolithographic processes than a conventional one and therefore able to simplify the overall manufacturing processes and reduce cost. The steps are:providing a substrate having a polysilicon gate, a source/drain region and a spacer formed on the sidewall of the polysilicon gate;forming a self-aligned metal silicide layer above the substrate and covering the polysilicon gate as well as the surface of the source/drain region;forming a first dielectric layer above the substrate, and then a first conducting layer above the first dielectric layer;using a photolithographic process to define a pattern on the first conducting layer and then etching the first dielectric layer to a certain depth;forming a second dielectric layer above the substrate;etching the first dielectric layer and the second dielectric layer until the metal silicide layer is exposed so as to form contact windows in designated regions; andforming metal plugs inside the contact windows.

Abstract: An integrated circuit is provided having an improved interconnect structure. The interconnect structure includes a power-coupled local interconnect which is always retained at VDD or VSS (i.e., ground) level. The local interconnect resides a dielectric-spaced distance below critical runs of overlying interconnect. The powered local interconnect serves to sink noise transients from the critical conductors to ensure that circuits connected to the conductors do not inoperably function. Accordingly, the local interconnect extends along a substantial portion of the conductor length, and is either wider or narrower than the conductor under which it extends. The local interconnect can either be polysilicon, doped polysilicon, polycide, refractory metal silicide, or multi-level refractory metal.

Abstract: An CMOS interconnection method that permits small source/drain surface areas has been provided. The interconnection is applicable to both strap and via type connections. The surface areas of the small source/drain regions are extended into neighboring field oxide regions by forming a silicide film from the source/drain regions to the field oxide. Interconnections on the same metal level, or to another metal level are made by contact to the silicide covered field oxide. The source/drain regions need only be large enough to accept the silicide film. Transistors with small source/drain regions have smaller drain leakage currents and less parasitic capacitance. A CMOS transistor interconnection apparatus has also been provided.

Abstract: A method of making ohmic contact between a thin film polysilicon layer of a first conductivity type and a subsequently provided conductive layer includes: a) providing a semiconductor substrate having an outer region; b) providing a first insulating layer outwardly of the outer region; c) etching a first contact opening of a first diameter through the first insulating layer to the substrate outer region; d) providing conductivity enhancing dopant impurity of the first conductivity type into the substrate outer region to render the outer region electrically conductive; e) providing a thin film polysilicon layer of the first conductivity type into the first contact opening and in ohmic electrical connection with the substrate outer region; f) providing a second insulating layer outwardly of the thin film polysilicon layer and the first insulating layer; g) etching a second contact opening of a second diameter into the second insulating layer, the second contact opening overlapping with the first contact opening

Abstract: A method is provided for combining the process steps for forming a resistor and interconnect into one process layer, thus eliminating the need for at least two mask steps. An oxide layer is formed over a region of a polysilicon layer in which the resistor will be formed. The oxide protects the resistor from further processing. A conductive layer is then deposited at least over the exposed portion of the polysilicon layer. In a first preferred embodiment, a refractory metal forms the conductive layer. The refractory metal is sintered or heated to form silicide over the exposed portion of the polysilicon layer, and the non-silicided metal is removed. The underlying layer may be doped as desired, before or after silicidation, for the first preferred embodiment. Thus, a resistor and conductive interconnect is formed within the same layer. Also disclosed is an embodiment in which the conductive layer need not be sintered, and an embodiment in which the resistor is formed in the sidewalls of a vertical cavity.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is formed in the first opening and on a portion of the first dielectric layer adjacent the first opening. The dual landing pad is preferably formed from two polysilicon landing pads with an oxide formed in between a portion of the two polysilicon layers and over the first polysilicon layer. This landing pad will enhance the planarization of the wafer at this stage of the manufacturing and tolerate misalignment of subsequently formed metal contacts without invading design rules.

Abstract: A method of forming a buried contact junction without forming a buried contact trench and without a disconnection gap in the current path by using a tapered polysilicon profile and a large angle tilt buried contact implant is described. A layer of gate silicon oxide is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate silicon oxide layer. The first polysilicon layer is etched away where it is not covered by a buried contact mask to provide an opening to the semiconductor substrate wherein the first polysilicon layer is tapered such that the bottom of the opening has a width the size of the planned buried contact and wherein the top of the opening has a width larger than the size of the planned buried contact. Ions are implanted at a tilt angle into the substrate within the opening whereby the ions penetrate the substrate laterally underlying with said first polysilicon layer to form the buried contact.

Abstract: A method for reducing stray conductive material near vertical surfaces in semiconductor manufacturing processes comprising the following steps. Deposit the gate oxide, polysilicon and cap oxide layers. Apply a Poly1A mask. The Poly1A mask pattern comprises the Poly1 areas that are part of the final circuit layout as well as additional Poly1 areas that are included to provide planar surfaces to prevent stringer formation. Etch the cap, polysilicon and gate oxide layers to partially form the transistor gate structures. Form oxide spacers on the sides of the transistor gate structures. Apply a source/drain mask. Deposit source/drain dopants to form diffusions. Deposit an interlayer dielectric. Mask and pattern contacts to the diffusions and the Poly1 layer. Deposit blanket TiN/Ti layer(s). Pattern the TiN/Ti layer(s) using a TiN/Ti mask and a dry anisotropic etch. Patterning the TiN/Ti layer(s) may create TiN/Ti stringers along vertical surfaces of the interconnect layer.

Abstract: The present invention provides a method for fabricating tungsten local interconnections in high density CMOS circuits, and also provides high density CMOS circuits having local interconnections formed of tungsten. Pursuant to the method, an etch stop layer of chromium is initially deposited on the circuit elements of the CMOS silicon substrate. Next, a conductive layer of tungsten is non-selectively deposited on the chromium layer. A photoresist mask is then lithographically patterned over the tungsten layer. The tungsten layer is then etched down to, and stopping at, the chromium layer, after which the photoresist mask is stripped. The stripping preferably uses a low temperature plasma etch in O.sub.2 at a temperature of less than 100.degree. C. Finally, a directional O.sub.2 reactive ion etch is used to remove the chromium layer selectively to the silicon substrate. Borderless contacts are formed with the aid of the chromium etch stop layer beneath the tungsten local interconnection layer.

Abstract: A semiconductor processing method of providing a polysilicon film having induced outer surface roughness includes, a) providing a polysilicon layer over a substrate, the polysilicon layer having an outer surface of a first degree of roughness; b) providing a layer of a refractory metal silicide over the outer surface of the polysilicon layer, the refractory metal silicide preferably being WSi.sub.x where "x" is initially from 1.0 to 2.5, the WSi.sub.x layer and the polysilicon layer outer surface defining a first interface therebetween; c) annealing the substrate at a temperature and for a time period which are effective to transform the WSi.sub.x into a tetragonal crystalline structure and to transform the first interface into a different second interface, the WSi.sub.x layer not being in a tetragonal crystalline state prior to the anneal, the WSi.sub.x at the second interface having an increased value of "x" from the initial value of "x"; and d) etching the WSi.sub.

Abstract: An improved method for depositing the polysilicon layer from which a gate pedestal is later formed is described. Deposition takes place in two stages. Initially, the conventional deposition temperature of about 630.degree. C. is used. Then, when the intended thickness of polysilicon has been grown, the temperature is ramped down to about 560.degree. C., without interrupting the deposition process, and growth of the film continues to completion. This is followed by a standard doping step using POCl.sub.3. Polysilicon films formed in this way have been found to have very smooth surfaces because the topmost layer is less subject to uncontrolled grain growth. As a consequence, dielectric layers obtained by oxidizing such films exhibit superior breakdown voltages.

Abstract: A method for forming within a Field Effect Transistor (FET) for use within an integrated circuit a polycide gate electrode. There is first provided a semiconductor substrate. Formed upon the semiconductor is a patterned polysilicon layer. Formed then upon the semiconductor substrate and the patterned polysilicon layer is a blanket insulator layer. The blanket insulator layer is then patterned through planarizing to form a patterned planarized insulator layer while simultaneously exposing the surface of the patterned polysilicon layer. Finally, there is formed upon the exposed surface of the patterned polysilicon layer a patterned metal silicide layer. The patterned metal silicide layer and the patterned polysilicon layer form a polycide gate electrode. The metal silicide layer within the polycide gate electrode is not susceptible to encroachment upon adjoining insulator spacers or source/drain regions within the Field Effect Transistor (FET) within which is formed the polycide gate electrode.

Abstract: Integrated circuitry and a method of forming a contact landing pad are described. The method includes, in one embodiment, providing a substrate having a plurality of components which are disposed in spaced relation to one another; forming a silicon plug spanning between two adjacent components; forming a refractory metal layer over the silicon plug and at least one of the components; reacting the silicon plug and the refractory metal layer to form a silicide layer on the silicon plug; and after forming the silicide layer removing unreacted refractory metal layer material from the substrate.

Abstract: A method for fabricating a metal contact structure of semiconductor devices comprising forming a first conducting layer; a first insulating layer disposed on said first conducting layer; a first contact hole to said first conducting layer; wherein said first contact hole is formed in said first insulating layer; dummy conducting patterns formed in said first contact hole, wherein said conducting dummy patterns are contacted with said first conducting layer through said first contact hole, and said dummy film is partly overlapped on the said first insulating layer; a second insulating layer disposed on said first insulating layer; a second contact hole, wherein said second contact hole is formed in said second insulating layer, and wherein said first contact hole and said second contact hole substantially form a through-hole; and a second conducting layer disposed on said second insulating layer which is contacted to said dummy conducting patterns through said second contact hole.

Abstract: A process has been developed which allows contact between levels of interconnect metallization structures, to occur without the use of via holes, etched in interlevel insulator layers. The process features creation of a raised tungsten plug structure, used to provide contact between underlying active device regions and an overlying interconnect metallization structure. The tungsten plug structure is formed by photolithographic masking and dry etching procedures, thus avoiding increasing the size of a tungsten seam, in the center of the plug structure. In addition the tungsten definition process, also results in a raised plug structure, allowing subsequent contact of interconnect metallization levels to proceed without the use of etched via holes in interlevel insulator layers.

Abstract: A process for fabricating a MOSFET device, for a triple polysilicon SRAM process, using a self-aligned, halo implant, (SAC halo implant), region, used to improve MOSFET performance and yield, has been developed. This process features implanting the SAC halo region, into a region of the semiconductor substrate, already exposed and prepared for a self-aligned contact, (SAC), structure, therefore requiring no additional photolithographic procedures.

Abstract: A method of manufacturing a semiconductor device that does not interfere with electrical connection of a polysilicon interconnection layer to a source/drain region of a transistor. Patterning of the interconnection layer and the gate electrode occurs prior to removal of an underlying oxide film to prevent etching of the substrate. An interconnection layer of amorphous material is formed on the oxide film, and the patterned interconnection layer is subsequently electrically connected to the substrate by introducing ions into the amorphous material to reduce the oxide film underneath the interconnection layer. After introduction of ions into the amorphous layer, the amorphous material is crystallized to increase the conductivity of the interconnection layer.

Abstract: A semiconductor device which can interconnect different types of impurity region without increasing a contact resistance including a first impurity diffusion region formed on a first portion of a semiconductor substrate, a second impurity diffusion region formed on a second portion of the semiconductor substrate, an interlevel insulating layer having a contact hole exposing the first and second impurity regions on the semiconductor substrate, a first conductive layer formed on the interlevel insulating layer, a second conductive layer formed on the overall surface of the substrate, wherein the second conductive layer formed on the first impurity diffusion region is doped with the same impurities as doped into the first impurity diffusion region and the second conductive layer formed on the second impurity diffusion region is doped with the same impurities as doped into the second impurity diffusion region, and a manufacturing method thereof are disclosed.

Abstract: A buried interconnect structure which is stable at the high temperatures involved in BiCMOS, bipolar, and CMOS transistor process flows, and a method of making the same. The interconnect structure is fully insulated and can be used to form stable, doped structures suitable for use as electrodes and gate structures in a CMOS process, or to form low resistance contacts to N or P-type silicon as part of a bipolar process. Because the interconnect structure is buried and fully insulated from surrounding structures, it may be used to form complex, multi-level devices having a minimized geometry and increased circuit density.

Abstract: The present invention provides a method of fabrication for semiconductor devices which enables a photolithography technique in a fabrication process to have a maximal effect on the transistor characteristics. Polysilicon film 16 and silicon nitride film 17 are formed to active transistor 11 and field shield isolation transistor 12, with isotropic etching of silicon nitride film 17 carried out using a resist pattern 20 which was patterned within the minimum processing width as the mask. Then, using the pattern of silicon nitride film 17 as a mask, thermal oxidation of polysilicon film 16 is carried out. Next, after eliminating silicon nitride film 17, anisotropic etching of polysilicon film 16 is carried out using silicon oxide film 21 as a mask, silicon oxide film 21 being formed by thermal oxidation of polysilicon film 16. In this way, a contact pad 22 formed of polysilicon film 16 is completed.

Abstract: A method of forming electromigration resistant integrated circuit runners is disclosed. A collimated beam of particles is directed toward a substrate to form a metal nucleating layer. Then a non-collimated beam is used to form the rest of the metal layer. Then the layers are patterned to form runners.

Abstract: A MOS-technology power device integrated structure includes a first plurality of elongated doped semiconductor stripes of a first conductivity type formed in a semiconductor layer of a second conductivity type, each including an elongated source region of the first conductivity type, an annular doped semiconductor region of the first conductivity type formed in the semiconductor layer and surrounding and merged with the elongated stripes, insulated gate stripes extending over the semiconductor layer between adjacent elongated stripes, a plurality of conductive gate fingers extending over and electrically connected to the insulated gate stripes, and a plurality of source metal fingers, each one extending over a respective elongated stripe and contacting the elongated stripe and the respective elongated source region, so that the source metal fingers and the conductive gate fingers are interdigitated.

Abstract: A method for forming a residue free patterned polysilicon layer upon a high step height patterned substrate layer. First, there is provided a semiconductor substrate having formed thereon a high step height patterned substrate layer. Formed upon the high step height patterned substrate layer is a polysilicon layer, and formed upon the polysilicon layer is a patterned photoresist layer. The patterned photoresist layer exposes portions of the polysilicon layer at a lower step level of the high step height patterned substrate layer. The polysilicon layer is then patterned through the patterned photoresist layer as an etch mask employing an anisotropic first etch process to yield a patterned polysilicon layer upon the surface of the high step height patterned substrate layer and polysilicon residues at the lower step level of the high step height patterned substrate layer.