Abstract: The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten layer to fill the feature. Depositing the tungsten nucleation layer involves exposing the substrate to alternating pulses of a boron-containing reducing agent and a tungsten-containing precursor without using any hydrogen gas, e.g., as a carrier or background gas. Using this process, a conformal tungsten nucleation layer can be deposited to a thickness as small as about 10 Angstroms. The feature may then be wholly or partially filled with tungsten by a hydrogen reduction chemical vapor deposition process. Resistivities of about 14 ??-cm for a 500 Angstrom film may be obtained.

Abstract: Disclosed is a semiconductor device including: a substrate; a wiring layer formed on the substrate and made of copper or a copper alloy; a copper diffusion barrier film formed on the wiring layer and made of an amorphous carbon film formed by CVD using a processing gas containing a hydrocarbon gas; and a low-k insulating film formed on the copper diffusion barrier film.

Abstract: The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element.

Abstract: A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV.

Abstract: A process for producing a semiconductor device, comprising the wiring region forming step of forming a wiring region on a semiconductor substrate; the copper wiring layer forming step of forming a copper wiring layer on the formed wiring region by electrolytic plating technique, wherein the copper wiring layer is formed by passing a current of application pattern determined from the relationship between application pattern of current passed at electrolytic plating and impurity content characteristic in the formed copper wiring layer so that the impurity content in the formed copper wiring layer becomes desired one; and the wiring forming step of polishing the formed copper wiring layer into a wiring.

Abstract: A method of forming (and apparatus for forming) tantalum silicide layers (including tantalum silicon nitride layers), which are typically useful as diffusion barrier layers, on a substrate by using a vapor deposition process with a tantalum halide precursor compound, a silicon precursor compound, and an optional nitrogen precursor compound.

Abstract: In sophisticated semiconductor devices, the metal-containing layer stack at the back side of the substrate may be provided so as to obtain superior adhesion to the semiconductor material in order to reduce the probability of creating leakage paths in a bump structure upon separating the substrate into individual semiconductor chips. For this purpose, in some illustrative embodiments, an adhesion layer including a metal and at least one non-metal species may be used, such as titanium oxide, in combination with further metal-containing materials, such as titanium, vanadium and gold.

Abstract: Methods of improving the adhesion of low resistivity tungsten/tungsten nitride layers are provided. Low resistivity tungsten/tungsten nitride layers with good adhesion are formed by treating a tungsten or tungsten nitride layer before depositing low resistivity tungsten. Treatments include a plasma treatment and a temperature treatment. According to various embodiments, the treatment methods involve different gaseous atmospheres and plasma conditions.

Abstract: A method for etching features in an etch layer disposed below a mask on a process wafer is provided. A hydrocarbon based glue layer is deposited. The etch layer on the process wafer is etched with at least one cycle, wherein each cycle comprises depositing a hydrofluorocarbon layer over the mask and on the hydrocarbon based glue layer, wherein the hydrocarbon based glue layer increases adhesion of the hydrofluorocarbon layer and etching the etch layer.

Abstract: The invention relates to a method for producing a nanoporous layer, wherein a layer made of gold and silver is deposited onto a substrate, particularly in an electrochemical or galvanic fashion, wherein the composition of said layer lies between 20% and 40% gold and 80% to 60% silver. The silver is subsequently selectively removed in order to obtain a nanoporous gold layer.

Abstract: Organometallic precursors and methods for deposition on a substrate in seed/barrier applications are herein disclosed. In some embodiments, the organometallic precursor is a ruthenium-containing, tantalum-containing precursor or combination thereof and may be deposited by atomic layer deposition, chemical vapor deposition and/or physical vapor deposition.

Abstract: A method for forming a contact opening, such as a via hole, is provided. In the method, a sacrificial layer is deposited over a damascene feature prior to exposing a conductor formed in a substrate at a bottom of the opening. The sacrificial layer is provided to prevent damage or contamination of materials used. Even after the conductor has been exposed once or more times, the sacrificial layer can be deposited over the damascene feature to protect it from further damage or contamination by a subsequent process that will further expose the conductor at the contact opening bottom. The exposing step may form a recess in the conductor. By further forming a trench feature over the contact opening, a dual damascene feature can be fabricated.

Abstract: Embodiments of a method for applying a thermal-interface material are described. During this method, a first surface of a heat-removal device and a second surface of a semiconductor die are prepared. Next, a region on a given surface, which is at least one of the first surface and the second surface, is defined. Then, the thermal-interface material is applied to at least the region, where the thermal-interface material includes a material that is a liquid metal over a range of operating temperatures of the semiconductor die.

Abstract: Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode of the thin-film capacitor comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages.

Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Abstract: Deterioration of yield may be prevented when a contact in a semiconductor device is made by a method including forming a contact hole by selectively removing an insulating layer from a semiconductor substrate, depositing a barrier layer on the insulating layer and on the surface of (or in) the contact hole, depositing an initial tungsten layer on the barrier layer to at least a predetermined thickness, removing particles generated during at least one of the depositing steps, and filling the contact hole with an additional tungsten layer.

Abstract: A combined wide-image and loop-cutter pattern is provided for both cutting and forming a wide-image section to a hard mask on a substrate formed by sidewall imaging techniques in a reduced number of photolithographic steps. A single mask is formed which provides a wide mask section while additionally providing a mask to protect the critical edges of an underlying hard mask during hard mask etching. After the hard mask is cut into sections, the protective portions of the follow-on mask are removed to expose the critical edges of the underlying hard mask while maintaining shapes necessary for defining wide-image sections. Thus, the hard mask cutting, hard mask critical edge protecting, and large area mask may be formed in a reduced number of steps.

Abstract: An interlayer insulating film having a concave portion is formed on a semiconductor substrate. A tight adhesion film is formed on the inner surface of the concave portion and the upper surface of the insulating film. The surface of the adhesion layer is covered with an auxiliary film made of Cu alloy containing a first metal element. A conductive member containing a second metal element other than the first metal element is embedded in the concave portion, and deposited on the auxiliary film. Heat treatment is performed to make atoms of the first metal element in the auxiliary film segregate on the inner surface of the concave portion. The adhesion layer contains an element for enhancing tight adhesion of the auxiliary film more than if the auxiliary film is deposited directly on a surface of the interlayer insulating film.

Abstract: A method of forming an interconnect structure is provided. The method includes depositing a cobalt metal layer in an interconnect opening formed within a dielectric material containing a dielectric reactant element. The method further includes, in any order, thermally reacting at least a portion of the cobalt metal layer with at least a portion of the dielectric material to form a diffusion barrier containing a compound of the reactive metal from the cobalt metal layer and the dielectric reactant element from the dielectric material, and forming a cobalt nitride adhesion layer in the interconnect opening. The method further includes filling the interconnect opening with Cu metal, where the diffusion barrier and the cobalt nitride adhesion layer surround the Cu metal in the interconnect opening.

Abstract: A method of forming a metal wiring includes: forming a foundation layer on a substrate; applying a solution including fine metal particles and a dispersion stabilizer on the foundation layer; and heating the applied solution to form into a conductive layer, wherein after the applying of the solution, the conductive layer is formed by starting the heating of the applied solution within a detained time.

Abstract: In an embodiment, a storage electrode of a capacitor in a semiconductor device is resistant to inadvertent etching during its manufacturing processes. A method of forming the storage electrode of the capacitor is described. The storage electrode of the capacitor may include a first metal layer electrically connected with a source region of a transistor through a contact plug penetrating an insulating layer on a semiconductor substrate. A polysilicon layer may then be formed on the first metal layer. A second metal layer is formed on the polysilicon layer.

Abstract: There is provided a substrate treatment method performed on a substrate before forming a Cu film on a surface of a base material of the substrate. In the substrate treatment method, a substrate on which a Cu film is to be formed is prepared; and a specific treatment is performed on the substrate so that a crystalline orientation of the surface of the base material of the substrate has a small lattice mismatch with the Cu film.

Abstract: A method of fabricating an integrated circuit includes forming a barrier layer along lateral side walls and a bottom of a via aperture and providing a ternary copper alloy via material in the via aperture to form a via. The via aperture is configured to receive the ternary copper alloy via material and electrically connect a first conductive layer and a second conductive layer. The ternary copper alloy via material helps the via to have a lower resistance and an increased grain size with staffed grain boundaries.

Abstract: Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A method comprises a short (?2 sec) flash activation of an ILD surface followed by flowing a precursor such as silane, DEMS, over the activated ILD surface. The precursor reacts with the activated ILD surface thereby selectively protecting the ILD surface. The protected ILD surface is resistant to plasma processing damage. The protected ILD surface eliminates the requirement of using a hard mask to protect a dielectric from plasma damage.

Abstract: A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material.

Abstract: When forming sophisticated metallization systems, surface integrity of an exposed metal surface, such as a copper-containing surface, may be enhanced by exposing the surface to a vapor of a passivation agent. Due to the corresponding interaction with the metal surface, enhanced integrity may be accomplished, while at the same time damage of exposed dielectric surface portions may be significantly reduced compared to conventional aggressive wet chemical cleaning processes that are typically used in conventional patterning regimes.

Abstract: A semiconductor device that includes an electrode of one material and a conductive material of lower resistivity formed over the electrode and a process for fabricating the semiconductor device.

Abstract: In some embodiments, an alternative to desmear for build-up roughening and copper adhesion promotion is presented. In this regard, a substrate in introduced having a dielectric layer, a plurality of polyelectrolyte multilayers on the dielectric layer, and a copper plating layer on the polyelectrolyte multilayers. Other embodiments are also disclosed and claimed.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired lining material. Exemplary process flows include alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with nitrogen. Near perfect step coverage allows minimal thickness for a diffusion barrier function, thereby maximizing the volume of a subsequent filling metal for any given trench and via dimensions.

Abstract: A dielectric layer is patterned with at least one line trough and/or at least one via cavity. A metallic nitride liner is formed on the surfaces of the patterned dielectric layer. A metal liner is formed on the surface of the metallic nitride liner. A conformal copper nitride layer is formed directly on the metal liner by atomic layer deposition (ALD) or chemical vapor deposition (CVD). A Cu seed layer is formed directly on the conformal copper nitride layer. The at least one line trough and/or the at least one via cavity are filled with an electroplated material. The direct contact between the conformal copper nitride layer and the Cu seed layer provides enhanced adhesion strength. The conformal copper nitride layer may be annealed to covert an exposed outer portion into a contiguous Cu layer, which may be employed to reduce the thickness of the Cu seed layer.

Abstract: By providing large area metal plates in combination with respective peripheral areas of increased adhesion characteristics, delamination events may be effectively monitored substantially without negatively affecting the overall performance of the semiconductor device during processing and operation. In some illustrative embodiments, dummy vias may be provided at the periphery of a large area metal plate, thereby allowing delamination in the central area while substantially avoiding a complete delamination of the metal plate. Consequently, valuable information with respect to mechanical characteristics of the metallization layer as well as process flow parameters may be efficiently monitored.

Abstract: A method for fabricating a semiconductor device, includes forming a first dielectric film above a substrate, forming an opening in the first dielectric film, forming a catalytic characteristic film using at least one of a metal having catalytic characteristics and a conductive oxide having catalytic characteristics as its material on sidewalls and at a bottom of the opening, depositing a conductive material film using a conductive material in the opening in which the catalytic characteristic film is formed on the sidewalls and at the bottom, removing the catalytic characteristic film formed on the sidewalls of the opening, and forming a second dielectric film above the first dielectric film and the conductive material film after the removing.

Abstract: Disclosed is a method for forming a capacitor of a semiconductor device. In such a method, a mold insulating layer is formed on an insulating interlayer provided with a storage node plug, and the mold insulating layer is etched to form a hole through which the storage node plug is exposed. Next, a metal storage electrode with an interposed WN layer is formed on a hole surface including the exposed storage node plug and the mold insulating layer is removed. Finally, a dielectric layer and a plate electrode are formed in order on the metal storage electrode.

Abstract: An interlayer insulation layer is formed on a semiconductor substrate to cover a lower wiring layer that is also formed on the semiconductor substrate. A contact hole to expose a surface of the lower wiring layer is formed by etching the interlayer insulation film. A wetting layer is formed on an inner wall of the contact hole. An anti-deposition layer is formed around an entrance of the contact hole to prevent an aluminum layer from being deposited around the entrance of the contact hole. The contact hole is filled with the aluminum layer.

Abstract: A method for forming a variable thickness Cu seed layer on a substrate for a subsequent Cu electrochemical plating process, where the Cu seed layer thickness profile improves uniformity of the electroplated Cu layer compared to when using a constant thickness Cu seed layer. The method includes depositing a Ru metal layer on the substrate, depositing a variable thickness Cu seed layer on the Ru metal layer by a physical vapor deposition process, whereby the variable thickness Cu seed layer is deposited with a Cu thickness at the edge of the substrate that is less than a Cu thickness at the center of the substrate, and plating bulk Cu onto the variable thickness Cu seed layer. The Ru metal layer may be a variable thickness Ru metal layer, or alternately, the Ru metal layer may have a substantially uniform Ru metal thickness across the substrate.

Abstract: Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to minimize contact resistance and maximize the total cross-sectional area of metal, including but not limited to tungsten, within the contact.

Abstract: Embodiments relate to a method of manufacturing a semiconductor device that may simplify a manufacturing process and may reduce process costs. According to embodiments, the method may include simultaneously forming a first gate of a first device area and a second gate of a second device area, patterning a PMD layer to form a first contact hole exposing the first gate, depositing and planarizing a high dielectric constant material and first and second metallic materials on the semiconductor substrate to expose PMD layer, forming an insulating layer, a metal layer and a third gate in the first contact hole, patterning the PMD layer to form a second contact hole exposing the second gate, and depositing a third metallic material on the semiconductor substrate and planarizing it such that the PMD layer is exposed, thereby forming a contact in the second contact hole.

Abstract: A back-end-of-line (BEOL) interconnect structure and a method of forming an interconnect structure. The interconnect structure comprises a conductor, such as copper, embedded in a dielectric layer, and a low-k dielectric capping layer, which acts as a diffusion barrier, on the conductor. A method of forming the BEOL interconnect structure is disclosed, where the capping layer is deposited using plasma-enhanced chemical vapor deposition (PECVD) and is comprised of Si, C, H, and N. The interconnect structure provides improved oxygen diffusion resistance and improved barrier qualities allowing for a reduction in film thickness.

Abstract: Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to minimize contact resistance and maximize the total cross-sectional area of metal, including but not limited to tungsten, within the contact.

Abstract: The laminated structure includes a substrate of low dielectric constant material of silicon compound and an electroless copper plating layer laminated thereon with a barrier layer. The barrier layer is interposed between the substrate and the copper layer, and the barrier layer is formed by electroless plating. And the laminated structure is characterized in that the barrier layer is formed on the substrate with a monomolecular layer of organosilane compound and a palladium catalyst which are interposed between the substrate and the barrier layer, the palladium catalyst modifies the terminal, adjacent to the barrier layer, of the monomolecular layer, and the barrier layer includes an electroless NiB plating layer which is disposed on the substrate side, and a electroless CoWP plating layer.

Abstract: Embodiments of a method for applying a thermal-interface material are described. During this method, a first surface of a heat-removal device and a second surface of a semiconductor die are prepared. Next, a region on a given surface, which is at least one of the first surface and the second surface, is defined. Then, the thermal-interface material is applied to at least the region, where the thermal-interface material includes a material that is a liquid metal over a range of operating temperatures of the semiconductor die.

Abstract: One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier layer of nickel and a layer of nobel metal, such as, gold. To prevent edge attack of copper after dicing, the layer of nickel is formed to seal the copper edge. To also prevent edge attack of the layer of nickel after dicing, the layer of gold is formed to seal both the layer of copper and the layer of nickel.

Abstract: A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The wafer or substrate is protected by an insulating overcoat (104). In the structure, the barrier metal layer is selectively exposed by a window (110) in the insulating overcoat. A layer of copper (105), adherent to the barrier metal, conformally covers the exposed barrier metal. Preferably, the copper layer is deposited by sputtering using a shadow mask. A layer of nickel (106) is adherent to the copper layer and a layer of noble metal (106) is adherent to the nickel layer. The noble metal may be palladium, or gold, or a palladium layer with an outermost gold layer. Preferably, the nickel and noble metal layers are deposited by electroless plating.

Abstract: The present invention provides a method for adhering dielectric layers to metals, in particular inert metals, using an adhesive layer comprising silicon-rich silicon nitride. Good adhesion is achieved at temperatures of less than 300° C., thereby facilitating the fabrication of semiconductor structures containing II-VI and III-V semiconductors.

Abstract: The present invention provides a technique by which a component forming a display device, such as a wiring can be formed with good adhesion. In the invention, a component forming a thin film transistor, a display device, or the like is formed with a material which is the same as at least one of the substances forming the formation subject surface added (mixed); thus, adhesion between the component and the formation subject is improved. An insulating layer formed over the component is formed with a laminate of a first insulating layer containing an organic material and a second insulating layer containing an inorganic material; thus, the insulating layer sufficiently covers irregularities on the surface of the component, and is also dense enough so as to be reliable as an insulating layer.

Abstract: A device and method for improving adhesion for thin film layers includes applying a diblock copolymer on a surface where adhesion to subsequent layers is needed and curing the diblock copolymer. Pores are formed in the diblock copolymer by treating the diblock copolymer with a solvent. The surface is etched through the pores of the diblock copolymer to form adhesion promoting features. The diblock copolymer is removed, and a layer is deposited on the surface wherein the adhesion promoting features are employed to promote adhesion between the layer and the surface.

Abstract: An aggregate structure of carbon fibers, organized by a plurality of carbon fibers, includes, an aggregate of the carbon fibers aligned in a lengthwise direction, in which a density of the carbon fibers at one side end is different from a density of the carbon fibers at the other side end.

Abstract: A method of manufacturing a device includes doping a low voltage threshold area and a high voltage threshold area. Gate structures are formed over the low voltage threshold and high voltage threshold areas while protecting the gate structure over the low voltage threshold area. A silicidation process is performed over the high voltage threshold area while the gate structure over the low voltage threshold area remains protected. Siliciding includes depositing metal on the gate of the high voltage threshold area and annealing the metal, the metal is deposited either by CVD or sputtering followed by anneal to fully suicide the gate structure of the high voltage threshold area. The metal, preferably cobalt or nickel is deposited to a thickness of approximately 500 ?, annealed for about 3 minutes at about 400° C.

Abstract: In a method for fabricating an inter dielectric layer in semiconductor device, a primary liner HDP oxide layer is formed by supplying a high density plasma (HDP) deposition source to a bit line stack formed on a semiconductor substrate. A high density plasma (HDP) deposition source is supplied to the bit line stack to form a primary liner HDP oxide layer. The primary liner HDP oxide layer is etched to a predetermined depth to form a secondary liner HDP oxide layer. An interlayer dielectric layer is formed to fill the areas defined by the bit line stack where the secondary liner HDP oxide layer is located.

Abstract: A die, comprising a substrate and one or more pillar structures formed over the substrate in a pattern and the method of forming the die.