Abstract: A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench formed therein, forming a firs conductive layer on the substrate blanketly, forming a patterned photoresist having a surface lower than an opening of the trench in the trench, removing the first conductive layer not covered by the patterned photoresist to form a second conductive layer having a top lower than an opening of the trench in the trench, removing the patterned photoresist, performing a dry etching process to remove the second conductive layer from the bottom of the trench to form a third conductive layer on the sidewalls of the trench, performing a selective metal chemical vapor deposition to form a metal layer having a surface lower than a surface of the substrate, and forming a protecting layer filling the trench on the metal layer.

Abstract: Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect, within a substrate, such as an interlayer dielectric substrate, includes providing a substrate having an embedded copper feature disposed therein. The embedded copper feature has an exposed surface and the substrate has a substrate surface adjacent to the exposed surface of the embedded copper feature. The exposed surface of the embedded copper feature is nitrided to form a layer of copper nitride in the embedded copper feature. Copper nitride is selectively etched from the embedded copper feature to recess the embedded copper feature within the substrate.

Abstract: Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device.

Abstract: A process for forming a metal interconnection in an integrated circuit includes forming a first metal layer and a second metal layer on the first metal layer. Photoresist is placed on the second metal layer and patterned to form a mask. The second metal layer is etched. The mask is then removed and the first metal layer is patterned with the second metal layer acting as mask for the first metal layer.

Abstract: An electronic device includes a substrate and a plurality of particles anchored to the substrate. An electrode material is formed over the particles and configured to form peaks over the particles. One or more operational layers are fog led over the electrode material for performing a device function.

Abstract: A method of forming circuit structures within openings includes forming pairs of spaced projections that project elevationally relative to a support material on opposing sides of respective openings formed into the support material. At least two of the spaced projections of different of the pairs are received between immediately adjacent of the openings. Conductive metal is formed elevationally over the projections and into and overfilling the openings. The metal is of a composition different from that of at least elevationally outermost portions of the projections. The metal is removed from being elevationally over the projections and at least some of the metal between the projections is removed. Other embodiments and aspects are disclosed.

Abstract: A capacitor and an NVM cell are formed in an integrated fashion so that the etching of the capacitor is useful in end point detection of an etch of the NVM cell. This is achieved using two conductive layers over an NVM region and over a capacitor region. The first conductive layer is patterned in preparation for a subsequent patterning step which includes a step of patterning both the first conductive layer and the second conductive layer in both the NVM region and the capacitor region. The subsequent etch provides for an important alignment of a floating gate to the overlying control gate by having both conductive layers etched using the same mask. During this subsequent etch, the fact that first conductive material is being etched in the capacitor region helps end point detection of the etch of the first conductive layer in the NVM region.

Abstract: A method of manufacturing a semiconductor device includes: forming a lower electrode layer in contact with a surface of a nitride semiconductor layer; forming an Al layer on the lower electrode layer; performing a heat treatment after the formation of the Al layer; removing the Al layer after the heat treatment is performed; and forming an upper electrode layer on the lower electrode layer after the removal of the Al layer.

Abstract: A method and apparatus are described for fabricating metal gate electrodes (85, 86) over a high-k gate dielectric layer (32) having a rare earth oxide capping layer (44) in at least the NMOS device area by treating the surface of a rare earth oxide capping layer (44) with an oxygen-free plasma process (42) to improve photoresist adhesion, forming a patterned photoresist layer (52) directly on the rare earth oxide capping layer (44), and then applying a wet etch process (62) to remove the exposed portion of the rare earth oxide capping layer (44) from the PMOS device area.

Abstract: A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer, a second electrically conductive material layer, and a third electrically conductive material layer. A resist material layer is deposited over the third electrically conductive material layer. The resist material layer is patterned to expose a portion of the third electrically conductive material layer. Some of the third electrically conductive material layer is removed to expose a portion of the second electrically conductive material layer. The third electrically conductive material layer is caused to overhang the second electrically conductive material layer by removing some of the second electrically conductive material layer. Some of the first electrically conductive material layer is removed.

Abstract: A method for fabricating a semiconductor device includes: forming a plurality of photoresist patterns over a substrate structure; forming an insulation layer for a spacer over a structure including the photoresist patterns; forming a plurality of spacers on sidewalls of the photoresist patterns by anisotropically etching the insulation layer, and forming a first opening through the insulation layer; and forming second openings in the insulation layer to expose the substrate structure.

Abstract: A method for fabricating an integrated device with reduced plasma damage is disclosed, including providing a substrate, forming a structural layer on the substrate, forming a photoresist layer on the structural layer, and performing an etching process to the structural layer, wherein the photoresist layer is conductive to reduce plasma damage during the etching process.

Abstract: A manufacturing method for a semiconductor device includes: the step of preparing a semiconductor chip which is provided with a functional element formed on a front surface side of a semiconductor substrate, a feedthrough electrode which is placed within a through hole that penetrates the semiconductor substrate, a front surface side connection member which protrudes from the front surface, and a rear surface side connection member which has a joining surface within a recess that is formed in a rear surface; the step of preparing a solid state device where a solid state device side connection member for connection to the front surface side connection member is formed on one surface; and the joining step of making the front surface of the semiconductor chip face the first surface of the solid state device by holding the rear surface of the semiconductor chip, and of joining the front surface side connection member to the solid state device side connection member.

Abstract: A conductive film containing aluminum or an aluminum alloy with a thickness equal to or greater than 1 ?m and equal to or less than 10 ?m is etched by wet-etching to be a predetermined thickness, and then etched by dry-etching, whereby side-etching of the conductive film can be suppressed and thickness reduction of a mask can be suppressed. The suppression of side-etching of the conductive film and the suppression of thickness reduction of the mask enable a conductive film containing aluminum or an aluminum alloy even with a large thickness equal to or greater than 1 ?m and equal to or less than 10 ?m to be etched such that the gradient of the edge portion of the conductive film can be steep, a predetermined thickness of the conductive film can be obtained, and shape difference from a mask pattern can be suppressed.

Abstract: A substrate structure with compliant bump comprises a substrate, a plurality of bumps, and a metallic layer, wherein the substrate comprises a surface, a trace layer, and a protective layer. The trace layer comprises a plurality of conductive pads, and each of the conductive pads comprises an upper surface. The protective layer comprises a plurality of openings. The bumps are formed on the surface, and each of the bumps comprises a top surface, an inner surface and an outer surface and defines a first body and a second body. The first body is located on the surface. The second body is located on top of the first body. The metallic layer is formed on the top surface, the inner surface, and the upper surface.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer.

Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate, forming a first insulating layer, a first redistribution layer, a second insulating layer, a second redistribution layer, and at least one of first processing, in which, after the first electrically conductive material is filled in the first opening to form a first via interconnect, the first redistribution layer is formed on the first insulating layer with the first electrically conductive material such that the first redistribution layer is electrically connected to the first via interconnect; or second processing, in which, after the second electrically conductive material is filled in the second opening to form a second via interconnect, the second redistribution layer is formed on the second insulating layer with the second electrically conductive material such that the second redistribution layer is electrically connected to the second via interconnect.

Abstract: Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.

Abstract: A photo-mask includes a first opaque pattern, a second opaque pattern, a transparent single slit, and a translucent pattern. The transparent single slit is disposed between the first opaque pattern and the second opaque pattern, and the width of the transparent single slit is substantially between 1.5 micrometers and 2.5 micrometers. The translucent pattern is connected to the first opaque pattern and the second opaque pattern.

Abstract: A manufacturing process technology creates a pattern on a first layer using a focused ion beam process. The pattern is transferred to a second layer, which may act as a traditional etch stop layer. The pattern can be formed on the second layer without irradiation by light through a reticle and without wet chemical developing, thereby enabling conformal coverage and very fine critical feature control. Both dark field patterns and light field patterns are disclosed, which may enable reduced or minimal exposure by the focused ion beam.

Abstract: A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.

Abstract: Methods for removing a masking material, for example, a photoresist, and electronic devices formed by removing a masking material are presented. For example, a method for removing a masking material includes contacting the masking material with a solution comprising cerium. The cerium may be comprised in a salt. The salt may be cerium ammonium nitrate.

Abstract: Methods for imparting a dual stress property in a stress liner layer of a semiconductor device. The methods include depositing a metal layer over a compressive stress liner layer, applying a masking agent to a portion of the metal layer to produce a masked and unmasked region of the metal layer, etching the unmasked region of the metal layer to remove the metal layer in the unmasked region to thereby expose a corresponding portion of the compressive stress liner layer, removing the mask to expose the metal layer from the masked region, and irradiating the compressive stress liner layer to impart a tensile stress property to the exposed portion of the compressive stress liner layer. Methods are also provided for imparting a compressive-neutral dual stress property in a stress liner layer, as well as for imparting a neutral-tensile dual stress property in a stress liner layer.

Abstract: A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate.

Abstract: A method of manufacturing a semiconductor device includes: preparing a wafer member, the wafer member including a wafer, a conductive layer formed on a surface of the wafer and a negative photoresist formed on the conductive layer; applying a light blocking material so as to cover at least a part of an outer edge of the wafer member from an upper surface of the negative photoresist to a side surface of the negative photoresist; exposing the negative photoresist to exposure light; removing the light blocking material; and developing the negative photoresist.

Abstract: A method of fabricating a metal interconnection and a method of fabricating image sensor using the same are provided. The method of fabricating a metal interconnection including forming a interlayer dielectric layer on a substrate, forming an interconnection formation region in the interlayer dielectric layer, performing an ultraviolet (UV) treatment on the substrate after the interconnection formation region is formed and forming a metal interconnection in the interconnection formation region.

Abstract: A semiconductor chip includes a semiconductor substrate, a through via provided in a through hole that passes through the semiconductor substrate, insulating layers laminated on the semiconductor substrate, a multi-layered wiring structure having a first wiring pattern and a second wiring pattern, and an external connection terminal provided on an uppermost layer of the multi-layered wiring structure, wherein the through via and the external connection terminal are connected electrically by the second wiring pattern.

Abstract: A method for fabricating a semiconductor device includes providing a substrate including cell regions and peripheral regions; selectively forming a gate conductive layer over the substrate in the peripheral regions, forming a sealing layer over the substrate with the gate conductive layer formed thereon, forming an insulation layer over the sealing layer to cover the substrate with the gate conductive layer formed on the substrate, planarizing the insulation layer to expose the sealing layer formed over the gate conductive layer, and forming a plurality of plugs in the cell regions, the plurality of the plugs penetrating the insulation layer and the sealing layer.

Abstract: A method of forming a metal pattern on a dielectric material that comprises forming at least one trench in a photosensitive, insulative material is disclosed. The at least one trench may be positioned over at least one bond pad. A metal is formed over the photosensitive, insulative material and into the at least one trench and a photoresist material is formed over the metal. A portion of the photoresist material may be removed to expose elevated areas of the metal such that a remaining portion of the photoresist material does not extend beyond sidewalls of the at least one trench and onto the elevated areas of the metal. The metal may be exposed laterally beyond the remaining portion of the photoresist material.

Abstract: A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.

Abstract: An embodiment of the present invention provides a manufacturing method of an interposer including: providing a semiconductor substrate having a first surface, a second surface and at least a through hole connecting the first surface to the second surface; electrocoating a polymer layer on the first surface, the second surface and an inner wall of the through hole; and forming a wiring layer on the electrocoating polymer layer, wherein the wiring layer extends from the first surface to the second surface via the inner wall of the through hole. Another embodiment of the present invention provides an interposer.

Abstract: A semiconductor process is provided. A mask layer is formed on a substrate and has a first opening exposing a portion of the substrate. Using the mask layer as a mask, a dry etching process is performed on the substrate to form a second opening therein. The second opening has a bottom portion and a side wall extending upwards and outwards from the bottom portion, wherein the bottom portion is exposed by the first opening and the side wall is covered by the mask layer. Using the mask layer as a mask, a vertical ion implantation process is performed on the bottom portion. A conversion process is performed, so as to form converting layers on the side wall and the bottom portion of the second opening, wherein a thickness of the converting layer on the side wall is larger than a thickness of the converting layer on the bottom portion.

Abstract: A via is formed on a wafer to lie within an opening in a non-conductive structure and make an electrical connection with an underlying conductive structure so that the entire top surface of the via is substantially planar, and lies substantially in the same plane as the top surface of the non-conductive structure. The substantially planar top surface of the via enables a carbon nanotube switch to be predictably and reliably closed.

Abstract: A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction.

Abstract: A method for making contact landing pad structures in a semiconductor integrated circuit device includes forming an isolation region and forming active regions in the semiconductor substrate. The active regions are separated by the isolation region, and each of the active regions includes one or more contact regions. The method includes forming a raised structure overlying the isolation region and disposed between a first and second contact regions. The method includes depositing a cap layer and forming an interlayer dielectric layer overlying the cap layer. The method includes depositing a photoresist layer overlying the interlayer dielectric layer and uses a mask pattern to selectively remove a portion of the photoresist layer to form a line type opening, which exposes a portion of the interlayer dielectric layer overlying at least the first and second contact regions. The method deposits a conductive fill material and performs a planarization process to form multiple conductive landing contact pads.

Abstract: Embodiments of the present invention generally provide methods and apparatus for material removal using lasers in the fabrication of solar cells. In one embodiment, an apparatus is provided that removes portions of a dielectric layer deposited on a solar cell substrate according to a desired pattern. In certain embodiments, methods for removing a portion of a material via a laser without damaging the underlying substrate are provided. In one embodiment, the intensity profile of the beam is adjusted so that the difference between the maximum and minimum intensity within a spot formed on a substrate surface is reduced to an optimum range. In one example, the substrate is positioned such that the peak intensity at the center versus the periphery of the substrate is lowered. In one embodiment, the pulse energy is improved to provide thermal stress and physical lift-off of a desired portion of a dielectric layer.

Abstract: In a method of forming a pattern, a plurality of first line patterns and first spacers filling spaces between the adjacent first line patterns are formed on an object layer. The first line patterns and the first spacers extend in a first direction. A plurality of second line patterns are formed on the first line patterns and the first spacers. The second line patterns extend in a second direction substantially perpendicular to the first direction. The first spacers are partially removed by a wet etching process. The object layer is etched using the first and second line patterns as an etching mask.

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning.

Abstract: A method of manufacturing a semiconductor component includes the steps of manufacturing of a wafer, applying structures of components on the wafer to form a wafer assembly, applying a metal coating on the wafer, removing the metal coating in non-contact areas of the components, applying surrounds on the edge areas of the components, arranging the wafer on a foil held by a clamping ring, separating the components of the wafer compound carried by the foil from one another, arranging a covering mask on the areas of the separated components carried by the foil which are not to be coated, applying a metal coating on the separate components covered with the mask, removal of the mask, and removal of the components from the foil and further processing the separate components wherein that applying a metal coating on the separate components covered by the mask takes place by means of thermal spraying.

Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

Abstract: A method of manufacturing a semiconductor device includes, but is not limited to, the following processes. A seed layer is formed over a substrate. The seed layer includes first, second, and third portions. A first electrode covering the first portion of the seed layer is formed without forming an electrode on the second and third portions of the seed layer. The third portion of the seed layer is removed so that the first and second portions remain over the substrate, and the first and second portions are separated from each other.

Abstract: A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. The first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch.

Abstract: A method for fabricating a metal pattern in a semiconductor device includes forming a metal layer over a substrate, forming a hard mask layer over the metal layer, forming a sacrifice pattern over the hard mask layer, forming a spacer pattern on sidewalks of the sacrifice pattern, removing the sacrifice pattern, forming a hard mask pattern by etching the hard mask layer using the spacer pattern as an etch barrier, forming an etching protection layer over the hard mask pattern and on sidewalks of the hard mask pattern, and forming the metal pattern by performing primary and secondary etching processes on the metal layer using the etching protection layer as an etch barrier.

Abstract: Methods of forming nonvolatile memory devices include forming first and second floating gate electrodes of first and second nonvolatile memory cells, respectively, at side-by-side locations on a substrate. The substrate is selectively etched to define a trench therein extending between the first and second floating gate electrodes. The trench is at least partially filled with a first electrical insulation pattern. An inorganic polysilazane-type spin-on-glass (SOG) layer is conformally deposited on the first and second floating gate electrodes and on the first electrical insulation pattern and then partially removed.

Abstract: A method of fabricating a semiconductor device, the method including providing a substrate; forming an underlying layer on the substrate; forming a sacrificial layer on the underlying layer; forming an opening in the sacrificial layer by patterning the sacrificial layer such that the opening exposes a predetermined region of the underlying layer; forming a mask layer in the opening; forming an oxide mask by partially or completely oxidizing the mask layer; removing the sacrificial layer; and etching the underlying layer using the oxide mask as an etch mask to form an underlying layer pattern.

Abstract: A microelectromechanical systems device fabricated on a pre-patterned substrate having grooves formed therein. A lower electrode is deposited over the substrate and separated from an orthogonal upper electrode by a cavity. The upper electrode is configured to be movable to modulate light. A semi-reflective layer and a transparent material are formed over the movable upper electrode.

Abstract: The present invention provides a method of fabricating a semiconductor device including forming stop layers (32) that include silicon oxy-nitride films above a semiconductor substrate, forming a cover film (34) between and on the stop layers, in which a top surface of the cover film above a region between the stop layers is higher than top surfaces of the stop layers, and polishing the cover film to the stop layers by using ceria slurry, and also provides a semiconductor device including metal layers (30) provided above a semiconductor substrate, silicon oxy-nitride films (32) provided on the metal layers, and an embedded layer (36) provided between the metal layers to have a top surface substantially coplanar with top surfaces of the silicon oxy-nitride films. According to the present invention, it is possible to provide a semiconductor device having a film of excellent planarization on a surface thereof and fabrication method therefor.

Abstract: A method of fabricating a vertical light emitting diode including: growing a low doped first semiconductor layer on a sacrificial substrate; forming an aluminum layer on the low doped first semiconductor; forming an AAO layer having a large number of holes formed therein by anodizing the aluminum layer; etching and patterning the low doped first semiconductor layer using the aluminum layer as a shadow mask, thereby forming grooves; removing the aluminum layer remaining; sequentially forming a high doped first semiconductor layer, an active layer and a second semiconductor layer on the low doped first semiconductor layer with the grooves; forming a metal reflective layer and a conductive substrate on the second semiconductor layer; separating the sacrificial substrate; and forming an electrode pad on the other surface of the low doped first semiconductor layer, the electrode pad filled in the grooves and in ohmic contact with the high doped first semiconductor.

Abstract: Embodiments of the invention are concerned with a method of manufacturing a radiation detector having one or more conductive contacts on a semiconductor substrate, and comprise the steps of: applying a first conductive layer to a first surface of the semiconductor substrate; applying a second conductive layer to form a plurality of contiguous layers of conductive materials, said plurality of contiguous layers including said first conductive layer; and selectively removing parts of said plurality of contiguous layers so as to form said conductive contacts, the conductive contacts defining one or more radiation detector cells in the semiconductor substrate.