Abstract: One or more embodiments relate to a method of making a semiconductor structure, comprising: forming a opening partially through a semiconductor substrate, the opening including an upper portion and a lower portion; forming a first dielectric layer over a sidewall surface of the upper portion, wherein the first dielectric layer does not overlie a sidewall surface of the lower portion; and forming a conductive material over a sidewall surface of the first dielectric layer, the conductive material not being in direct contact with a sidewall surface of the lower portion.

Abstract: In a method for manufacturing a silicon carbide semiconductor device, a conductive layer is formed on a silicon carbide layer. The silicon carbide layer and the conductive layer react with each other thus forming an alloy layer formed of a reaction layer in contact with the silicon carbide layer and a silicide layer on the reaction layer. A carbon component is removed from the silicide layer. A portion of the silicide layer is removed using an acid thus exposing at least a portion of the reaction layer. An electrode layer is formed on an upper side of the exposed reaction layer.

Abstract: An etchant composition including 0.5 wt % to 20 wt % of a persulfate, 0.01 wt % to 1 wt % of a fluorine compound, 1 wt % to 10 wt % of an inorganic acid, 0.01 wt % to 2 wt % of an azole-based compound, 0.1 wt % to 5 wt % of a chlorine compound, 0.05 wt % to 3 wt % of a copper salt, 0.01 wt % to 5 wt % of an antioxidant or a salt thereof, based on a total weight of the etchant composition, and water in an amount sufficient for the total weight of the etchant composition to be equal to 100 wt % is disclosed. The etchant composition is suitable for use in forming a metal wiring by etching a metal layer including copper or in fabricating a thin film transistor substrate for a display apparatus.

Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer.

Abstract: Semiconductor devices and methods of making thereof are disclosed. The semiconductor device includes a substrate prepared with a first dielectric layer formed thereon. The dielectric layer includes at least first, second and third contact regions. A second dielectric layer is disposed over the first dielectric layer. The device also includes at least first, second and third via contacts disposed in the second dielectric layer. The via contacts are coupled to the respective underlying contact regions and the via contacts do not extend beyond the underlying contact regions.

Abstract: A solution for processing devices is provided, comprising an activator comprising at least one of pyridine, pyrole, pyrrolidine, pyrimidine, N,N-dimethylformamide, tetraethylamine chloride, 4 pyridinethiol, or other organic compounds with a single N with a lone pair electron activator and an etchant comprising at least one of thionly chloride, Cl2, Br2, I2, SOF2, SOF4, SO2Cl2, SOBr2, S2O6F2, HSO3F, or C2Cl4O2.

Abstract: A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later.

Abstract: Integrated circuits with smooth metal gates and methods for fabricating integrated circuits with smooth metal gates are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a partially fabricated integrated circuit including a dielectric layer formed with a trench bound by a trench surface. The method deposits metal in the trench and forms an overburden portion of metal overlying the dielectric layer. The method includes selectively etching the metal with a chemical etchant and removing the overburden portion of metal.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a film having different filling properties dependent on space width above the patterning film to cover the first line patterns and the second line patterns to form the film on the first line patterns and on the first inter-line pattern space while making a cavity in the first inter-line pattern space and to form the film on at least a bottom portion of the second inter-line pattern space and a side wall of each of the second line patterns. The method includes performing etch-back of the film to remove the film on the first line patterns and on the first inter-line pattern space while causing the film to remain on at least the side wall of the second line patterns.

Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Abstract: Provided are an abrasive particle including auxiliary particles formed on a surface of a mother particle, a polishing slurry prepared by mixing the abrasive particles with a polishing accelerating agent and a pH adjusting agent, and a method of manufacturing a semiconductor device in which an insulating layer is polished by the polishing slurry while using a conductive layer as a polishing stop layer.

Abstract: A semiconductor memory device includes a first chip and a second chip connected to the first chip physically and electrically, wherein the first chip and the second chip are coupled by through silicon vias (TSVs) formed in a first region, and the first chip and the second chip are coupled by alignment keys formed in second regions.

Abstract: The present invention provides an array substrate, a method for manufacturing the same and a display device, and relates to technical field of displays. The method for manufacturing an array substrate comprises forming a metal layer on a substrate and removing superficial metallic oxide on the metal layer by a washing process. The method for manufacturing an array substrate according to the present inversion can remove the superficial metal oxide on the metal layer and improve the performance of a TFT.

Abstract: Implementations described herein generally relate to methods for forming tungsten materials on substrates using vapor deposition processes. The method comprises positioning a substrate having a feature formed therein in a substrate processing chamber, depositing a first film of a bulk tungsten layer by introducing a continuous flow of a hydrogen containing gas and a tungsten halide compound to the processing chamber to deposit the first tungsten film over the feature, etching the first film of the bulk tungsten layer using a plasma treatment to remove a portion of the first film by exposing the first film to a continuous flow of the tungsten halide compound and an activated treatment gas and depositing a second film of the bulk tungsten layer by introducing a continuous flow of the hydrogen containing gas and the tungsten halide compound to the processing chamber to deposit the second tungsten film over the first tungsten film.

Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.

Abstract: A method of patterning a platinum layer includes the following steps. A substrate is provided. A platinum layer is formed on the substrate. An etching process is performed to pattern the platinum layer, wherein an etchant used in the etching process simultaneously includes at least a chloride-containing gas and at least a fluoride-containing gas.

Abstract: Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.

Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.

Abstract: A method for processing a workpiece may include: providing a workpiece including a first region and a second region; forming a porous metal layer over the first region and the second region; wherein the first region and the second region are configured such that an adhesive force between the second region and the porous metal layer is lower than an adhesive force between the first region and the porous metal layer.

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.

Abstract: A semiconductor structure includes a molding compound, a conductive plug, and a cover. The conductive plug is in the molding compound. The cover is over a top meeting joint between the conductive plug and the molding compound. The semiconductor structure further has a dielectric. The dielectric is on the cover and the molding compound.

Abstract: A method for fabricating an integrated device includes the following steps. First, a multi-layered structure is formed on a substrate, wherein the multi-layered structure is embedded in a lower isolation layer. Then, a bottom conductive pattern and a top conductive pattern are formed on a top surface of the lower isolation layer, wherein the top conductive pattern is on a top surface of the bottom conductive pattern. Afterwards, portions of the top conductive pattern are removed to expose portions of the bottom conductive pattern. Subsequently, an upper isolation layer is deposited on the lower isolation layer so that the upper isolation layer can be in direct contact with the portions of the bottom conductive pattern. Finally, portions of the lower isolation layer and the upper isolation layer are removed so as to expose portions of the substrate.

Abstract: A method of providing microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is provided. The method providing for processes and manufacturing sequences limiting the maximum exposure of an integrated circuit upon which the MEMS is manufactured to below 350° C., and potentially to below 250° C., thereby allowing direct manufacturing of the MEMS devices onto electronics, such as Si CMOS circuits. The method further providing for the provisioning of MEMS devices with multiple non-conductive structural layers such as silicon carbide separated with small lateral gaps. Such silicon carbide structures offering enhanced material properties, increased environmental and chemical resilience whilst also allowing novel designs to be implemented taking advantage of the non-conductive material of the structural layer.

Abstract: An electrically, thermally, or electrically and thermally actuated device is disclosed herein. The device includes a substrate, a first electrode established on the substrate, an active region established on the electrode, and a second electrode established on the active region. A pattern is defined in at least one of the substrate, the first electrode, the second electrode, or the active region. At least one of grain boundaries are formed within, or surface asperities are formed on, at least one of the electrodes or the active region. The pattern controls the at least one of the grain boundaries or surface asperities.

Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.

Abstract: A conductive circuit is formed by printing a pattern of an ink composition and curing the pattern. The ink composition is a substantially solvent-free, liquid, addition curable, ink composition comprising (A) an organopolysiloxane having at least two alkenyl groups, (B) an organohydrogenpolysiloxane having at least two SiH groups, (C) conductive particles having an average particle size ?5 ?m, (D) conductive micro-particles having an average particle size <5 ?m, (E) a thixotropic agent, and (F) a hydrosilylation catalyst.

Abstract: Disclosed are devices comprising multiple nanogaps having a separation of less than about 5 nm. Also disclosed are methods for fabricating these devices.

Abstract: A method of fabricating a semiconductor device is described. A substrate having first and second areas is provided. A first patterned mask layer having at least one first opening in the first area and at least one second opening in the second area is formed over the substrate, wherein the first opening is smaller than the second opening. A portion of the substrate is removed with the first patterned mask layer as a mask to form first and second trenches respectively in the substrate in the first and second areas, wherein the width and the depth of the first trench are less than those of the second trench. A first dielectric layer is formed at least in the first and second trenches. A conductive structure is formed on the first dielectric layer on at least a portion of the sidewall of each of the first and second trenches.

Abstract: Methods for depositing nanomaterial onto a substrate are disclosed. Also disclosed are compositions useful for depositing nanomaterial, methods of making devices including nanomaterials, and a system and devices useful for depositing nanomaterials.

Abstract: On a surface of a substrate (3) on which surface a vapor-deposited film is to be formed, a photoresist (13) is formed so as to have an opening in a sealing region including a display region (R1) which sealing region is formed by a sealing resin (11) of a frame shape. Then, luminescent layers (8R, 8G, and 8B) having a striped pattern are formed. Subsequently, the photoresist (13) is removed with the use of an exfoliative solution so as to form the luminescent layers (8R, 8G, and 8B) patterned with high definition.

Abstract: One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the layer of insulating material, performing at least one etching process to define a cavity in the layer of insulating material, forming a layer of sacrificial material so as to overfill the cavity, performing at least one planarization process to remove a portion of the layer of sacrificial material and the patterned hard mask while leaving a remaining portion of the layer of sacrificial material within the cavity, and removing the remaining portion of the layer of sacrificial material positioned within the cavity.

Abstract: One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the layer of insulating material, performing at least one etching process to define a cavity in the layer of insulating material that exposes at least a portion of a conductive structure, forming a layer of sacrificial material that covers the exposed portion of the conductive structure, with the layer of sacrificial material in position, performing at least one second etching process to remove the patterned hard mask while leaving the layer of sacrificial material in position within the cavity, and removing the layer of sacrificial material positioned within the cavity.

Abstract: Devices and methods for forming a self-aligned airgap interconnect structure includes etching a conductive layer to a substrate to form conductive structures with patterned gaps and filling the gaps with a sacrificial material. The sacrificial material is planarized to expose a top surface of the conductive layer. A permeable cap layer is deposited over the conductive structure and the sacrificial material. Self-aligned airgaps are formed by removing the sacrificial material through the permeable layer.

Abstract: Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.

Abstract: A structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall of the first metal line and in the space, wherein an edge of the first metal line is exposed to the first air gap. A second air gap is on a sidewall of the second metal line and in the space, wherein an edge of the second metal line is exposed to the second air gap. A dielectric material is disposed in the space and between the first and the second air gaps.

Abstract: A blanket includes a releasable base; and a sacrificial layer being provided on the base and separated from the base in printing.

Abstract: The invention relates to a method 10 for forming a multi-level surface on a substrate 2, wherein said surface comprises areas of different wettability, the method comprising the step (A, B) of applying a multi-level stamp to the substrate for forming the multi-level surface, said multi-level stamp having different structural regions 1a arranged along the multi-level surface for locally altering wettability properties of at least a portion of a level of the multi-level surface 2a, 2b. The invention further relates to a semiconductor device and a method for manufacturing a semiconductor device.

Abstract: A method for forming a fine exposure pattern where a width and an interval of the pattern are each 1CD, by first exposing a photoresist by using an exposure mask where an interval ratio of a light shielding part and a light transmission part is 2CD:1CD to 4CD:1CD, and then second exposing the photoresist after the exposure mask is shifted at a predetermined interval, or second exposing the photoresist by using an exposure mask formed at a position where a light transmission part is shifted at a predetermined interval, and developing the photoresist, such that it is possible to form a display device having a pixel electrode including a plurality of fine branch electrodes having a smaller width and interval than a resolution of an exposure apparatus.

Abstract: A method of manufacturing a semiconductor device includes: preparing a wafer member, the wafer member including a wafer, a conductive layer formed on a surface of the wafer and a negative photoresist formed on the conductive layer; applying a light blocking material so as to cover at least a part of an outer edge of the wafer member from an upper surface of the negative photoresist to a side surface of the negative photoresist; exposing the negative photoresist to exposure light; removing the light blocking material; and developing the negative photoresist.

Abstract: A semiconductor process for forming specific pattern features comprising the steps of forming a target layer, a hard mask layer and a plurality of equally spaced-apart core bodies on a substrate, forming spacers on sidewalls of the core bodies, removing the core bodies so that the spacers are spaced-apart on the hard mask layer, using spacers as a mask to pattern the hard mask layer, removing the hard mask bodies outside of a predetermined region, forming photoresists on several outermost hard mask bodies of the predetermined region, and using the photoresists and remaining hard mask bodies as a mask to pattern the target layer.

Abstract: An embodiment of a system and method produces a random half pitched interconnect layout. A first normal-pitch mask and a second normal-pitch mask are created from a metallization layout having random metal shapes. The lines and spaces of the first mask are printed at normal pitch and then the lines are shrunk to half pitch on mask material. First spacers are used to generate a half pitch dimension along the outside of the lines of the first mask. The mask material outside of the first spacer pattern is partially removed. The spacers are removed and the process is repeated with the second mask. The mask material remains at the locations of first set of spacers and/or the second set of spacers to create a half pitch interconnect mask with constant spaces.

Abstract: The invention relates to a substrate (1) comprising a medium (10), said medium (10) comprising, on at least one of its main faces, a functional layer (11) that has low-E or antisolar properties or is electrically conductive, characterized in that said functional layer (11) comprises, on its extreme surface opposite the medium (10), at least one sulphurous compound, in particular a sulphate, a sulphonate and/or a thiosulphate.

Abstract: A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch mask located on a blanker layer of metal or metal alloy. Exposed portions of the blanket layer of metal or metal alloy that are not protected by the etch mask are removed utilizing an etch comprising a plasma that forms a polymeric compound and/or complex which protects a portion of the blanket layer of metal or metal alloy located directly beneath the etch mask during the etch.

Abstract: A process is provided for producing at least one interconnecting well to achieve a conductive pathway between at least two connection layers of a component comprising a stack of at least one first substrate and one second substrate which are electrically insulated from one another, the process including defining a surface contact region of a surface connection layer over a surface of the stack and of at least one first contact region embedded in the stack starting from a first embedded connection layer of the first substrate. A region devoid of material is positioned between the first substrate and second substrates and which comprises a stage of producing a interconnecting well which passes through the second substrate and extends between the surface contact region and the first embedded contact region and passes through the region devoid of material, and also a first layer which covers the first embedded connection layer.

Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

Abstract: Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern.

Abstract: According to one embodiment, a MEMS device comprises a first electrode provided on a support substrate, a second electrode opposed to the first electrode and movable in the direction it is opposed to the first electrode, and beam parts, each connected to those sides of the second electrode, which oppose to each other, and each supporting the second electrode. The second electrode has a slit extending parallel to the sides to which the beam parts are connected and opening at both the front and the back. Further, the second electrode has at least one bridge part extending over the slit, crossing the slit and made of a material different from that of the second electrode.

Abstract: A thin film photovoltaic device includes a substrate and a first conductive layer coupled to the substrate. The first conductive layer includes at least one first groove extending through a first portion of the first conductive layer to a portion of the substrate. The device also includes at least one semiconductor layer coupled to a remaining portion of the first conductive layer and the portion of the substrate. The at least one semiconductor layer includes a plurality of non-overlapping vias, each via extending through a portion of the at least one semiconductor layer to a portion of the first conductive layer. The device further includes a second conductive layer coupled to a remaining portion of the at least one semiconductor layer and portions of the first conductive layer. The second conductive layer includes at least one second groove extending through a portion of the second conductive layer to a portion of the at least one semiconductor layer.