Abstract: A composition and associated method for chemical mechanical planarization of a metal-containing substrate (e.g., a copper substrate) are described herein which afford high and tunable rates of metal removal as well as low dishing and erosion levels during CMP processing.

Abstract: Provided is a trench filling method, which includes: forming a silicon oxide liner on a semiconductor substrate with trenches formed therein, the trenches including narrow-width portions having a first minimum isolation width and wide-width portions having a second minimum isolation width being wider than the first minimum isolation width; forming an oxidation-barrier film on the silicon oxide liner; forming a silicon liner on the oxidation-barrier film; filling the narrow-width portions with a first filling material; filling the wide-width portions with a second filling material; and oxidizing the silicon liner.

Abstract: A method of manufacturing an electronic device that comprises a microelectromechanical (MEMS) element, the method comprising the steps of: providing a material layer (34) on a first side of a substrate (32); providing a trench (40) in the material later (34); etching material from the trench (40) such as to also etch the substrate (32) from the first side of the substrate (32); grinding the substrate (32) from a second side of the substrate to expose the trench (40); and using the exposed trench (40) as an etch hole. The exposed trench (40) is used as an etch hole for releasing a portion of the material layer (34), for example a beam resonator (12), from the substrate (32). An input electrode (6), an output electrode (8), and a top electrode (10) are provided.

Abstract: (A) solid polymer particles being finely dispersed in the aqueous phase and containing pendant functional groups (a1) capable of strongly interacting and forming strong complexes with the metal of the surfaces to be polished, and pendant functional groups (a2) capable of interacting less strongly with the metal of the surfaces to be polished than the functional groups (a1); and (B) an organic non-polymeric compound dissolved in the aqueous phase and capable of interacting and forming strong, water-soluble complexes with the metal of the surfaces to be polished and causing an increase of the material removal rate MRR and the static etch rate SER of the metal surfaces to be polished with increasing concentration of the compound (B); a CMP process comprising selecting (A) and (B) and the use of the CMP agent and process for polishing wafers with ICs.

Abstract: The invention provides a method of trimming a structure that includes a first wafer bonded to a second wafer, with the first wafer having a chamfered edge. The method includes a first trimming step carried out over a first depth that includes at least the thickness of the first wafer and over a first width determined from the edge of the first wafer. A second trimming step is then carried out over a second depth that includes at least the thickness of the first wafer and over a second width that is less than the first width.

Abstract: Semiconductor die break strength and yield are improved with a combination of laser dicing and etching, which are followed by dicing an underlying layer of material, such as die attach film (DAF) or metal. A second laser process or a second etch process may be used for dicing of the underlying layer of material. Performing sidewall etching before cutting the underlying layer of material reduces or prevents debris on the kerf sidewalls during the sidewall etching process. A thin wafer dicing laser system may include either a single laser process head solution or a dual laser process head solution to meet throughput requirements.

Abstract: The method for producing a silicon epitaxial wafer according to the present invention has: a growth step F at which an epitaxial layer is grown on a silicon single crystal substrate; a first polishing step D at which, before the growth step, at least a front surface of the silicon single crystal substrate is polished without using abrasive grains; and a second polishing step G at which at least the front surface of the silicon single crystal substrate is subjected to finish polishing after the growth step.

Abstract: The present invention relates to a plasma etching method with which a wide-gap semiconductor substrate can be etched with high accuracy. An inert gas is supplied into a processing chamber and plasma is generated from the inert gas, a bias potential is applied to a platen on which a wide-gap semiconductor substrate is placed, thereby making ions generated by the generation of plasma from the inert gas incident on the semiconductor substrate on the platen to thereby heat the semiconductor substrate. After the temperature of the semiconductor substrate reaches an etching temperature between 200° C. and 400° C., an etching gas is supplied into the processing chamber and plasma is generated from the etching gas and a bias potential is applied to the platen, thereby etching the semiconductor substrate while maintaining the temperature of the semiconductor substrate at the etching temperature.

Abstract: Provided is a method of producing a liquid ejection head substrate, the method including, in sequence; grinding a second surface of a silicon substrate, which is an opposite surface of a first surface on which a function element is formed, polishing the ground second surface, etching the polished second surface by reactive ion etching using ion incident energy, forming an etching mask on the second surface after the reactive ion etching, and forming a liquid supply port by subjecting the silicon substrate to wet etching using the etching mask.

Abstract: Described is a method for improving the flatness of a layer deposited on a doped polycrystalline layer, which includes reducing the grain size of the polycrystalline layer to decrease the out-diffusion amount of the dopant from the polycrystalline layer, and/or reducing the amount of the out-diffusing dopant on the surface of the polycrystalline layer.

Abstract: Disclosed is an adjuvant for use in simultaneous polishing of a cationically charged material and an anionically charged material, wherein the adjuvant comprises a polyelectrolyte salt containing: (a) a mixture of a linear polyelectrolyte having a weight average molecular weight of 2,000˜50,000 with a graft type polyelectrolyte that has a weight average molecular weight of 1,000˜20,000 and comprises a backbone and a side chain; and (b) a basic material. CMP (chemical mechanical polishing) slurry comprising the above adjuvant and abrasive particles is also disclosed. The adjuvant comprising a mixture of a linear polyelectrolyte with a graft type polyelectrolyte makes it possible to increase polishing selectivity as compared to CMP slurry using the linear polyelectrolyte alone, and to obtain a desired range of polishing selectivity by controlling the ratio of the linear polyelectrolyte to the graft type polyelectrolyte.

Abstract: Semiconductor material substrates are polished by a method including at least one polishing step A by means of which the substrate is polished on a polishing pad containing an abrasive material bonded in the polishing pad and a polishing agent solution is introduced between the substrate and the polishing pad during the polishing step; and at least one polishing step B by means of which the substrate is polished on a polishing pad containing an abrasive material-containing polishing pad and wherein a polishing agent slurry containing unbonded abrasive material is introduced between the substrate and the polishing pad during the polishing step.

Abstract: A method of manufacturing a semiconductor device according to an embodiment includes a process of forming a metal film on the surface of the insulation film with which a concave portion is filled and a first polishing process of polishing the surface of the metal film while supplying an oxidation agent containing no abrasive grains. The method of manufacturing the semiconductor device further includes a second polishing process of polishing the surface of the metal film while supplying a polishing agent excluding the oxidation agent to the surface of the metal film oxidized by the oxidation agent, after the first polishing process.

Abstract: A method includes performing a grinding on a backside of a semiconductor substrate. An image sensor is disposed on a front side of the semiconductor substrate. An impurity is doped into a surface layer of the backside of the semiconductor substrate to form a doped layer. A multi-cycle laser anneal is performed on the doped layer.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. Self-aligned assist pattern (SAP) is derived from original design layout in an automated manner using geometric Boolean operations based on some predefined design rules, and are included in the mask layout for efficient self-alignment of various sub-layouts of the target pattern during a multiple patterning lithography process. SAP can be of any shape and size, and can have continuous features (e.g., a ring), or discontinuous (e.g., bars not connected to each other) features. An end-to-end multiple patterning lithography using spacer and SAP may use positive tone lithography, and/or negative tone lithography for line and/or space printing.

Abstract: Provided are a polishing slurry for metal films and a polishing method which restrain the generation of erosion and seams, and makes the flatness of a surface polished therewith or thereby high. The slurry and the method are a polishing slurry, for metal films, comprising abrasive grains, a methacrylic acid based polymer and water, and a polishing method using the slurry, respectively.

Abstract: A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.

Abstract: An organic electro-optical component, with an electrode, counter-electrode, and organic region made up of one or more organic materials, which is in electrical contact and in an active region overlapping with the electrode and the counter-electrode, wherein the electrode and/or the counter-electrode have part electrodes which extend from a part electrode connecting section which is arranged outside of the active region, a distal electrode section is electrically connected via a proximal electrode section to the part electrode connecting section, the distal electrode section is formed at least in sections within the active region, and the proximal electrode section is formed outside of the active region and by means of an electrical pathway, the pathway length of which is larger than the shortest distance between an end of the distal electrode section facing the part electrode connecting section and the part electrode connecting section.

Abstract: A method of manufacturing is disclosed. An exemplary method includes providing a substrate and forming one or more layers over the substrate. The method further includes forming a surface layer over the one or more layers. The method further includes performing a patterning process on the surface layer thereby forming a pattern on the surface layer. The method further includes performing a cleaning process using a cleaning solution to clean a top surface of the substrate. The cleaning solution includes tetra methyl ammonium hydroxide (TMAH), hydrogen peroxide (H2O2) and water (H2O).

Abstract: A semiconductor chip and semiconductor package with stack chip structure include align patterns. The align patterns are formed of magnetic materials having opposite polarities on the top and bottom of the semiconductor chip. Thus, when the plurality of chips are stacked on the substrate in order for the packaging, the semiconductor chips may be exactly aligned by the magnetic force between the align patterns of the vertically stacked chips. The semiconductor package includes a plurality of stacked semiconductor chips and a filling material. Each of the stacked semiconductor chips includes a semiconductor substrate having a first surface and a second surface, wherein a circuit pattern such as a bonding pad is formed on the first surface, and a first align pattern formed on the first surface of the semiconductor substrate, wherein the first align pattern is formed of a magnetic material.

Abstract: One or more embodiments relate to a method for forming a semiconductor structure, comprising: providing a workpiece; forming a dielectric barrier layer over the workpiece; forming an opening through the dielectric barrier layer; forming a seed layer over the dielectric barrier layer and within the dielectric barrier layer opening; and electroplating a first fill layer on the seed layer.

Abstract: According to one embodiment, a semiconductor device manufacturing method is disclosed. The method can include polishing a film on a semiconductor substrate by pressing the film against a polishing pad. Polishing the film comprises performing first polishing in which an entrance temperature of the polishing pad is adjusted to 40° C. (inclusive) to 50° C. (inclusive), and an exit temperature of the polishing pad is adjusted to be higher by 5° C. or more than the entrance temperature. Polishing the film comprises performing second polishing in which the entrance temperature is adjusted to 30° C. or less, and the exit temperature is adjusted to be higher by 5° C. or more than the entrance temperature.

Abstract: Disclosed are a variety of porous and non-porous wire-like structures of microscopic and nanoscopic scale. For instance, disclosed are structures that comprise a porous object that comprises: (i) a first region; and (ii) a second region adjacent to the first region along an axis of the object, where the first region has at least one porous property different from that of the second region. Also disclosed are structures that include: (i) a high resistivity silicon; and (ii) a cross-section that is substantially perpendicular to an axis of the object. Also disclosed are methods of making and using such structures.

Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.

Abstract: A chemical-mechanical planarization pad for semiconductor manufacturing is provided. The pad comprises synthetic fibers that are non-crimped fibers which are present in an amount of 1.0% by weight to 98.0% by weight in the mat and wherein the non-crimped fibers have a length of 0.1 cm to 127 cm and a diameter of 1.0 to 1000 micrometers.

Abstract: A polishing slurry includes an abrasive, a dispersion agent, a polish accelerating agent and an adhesion inhibitor. The adhesion inhibitor includes a benzene compound combined with a carboxyl group. Methods of planarizing an insulating layer using the slurry are also provided.

Abstract: A polishing method and a method for forming a gate are provided. The method includes forming a dummy gate on a semiconductor substrate including a sacrificial oxide layer and a polysilicon layer which covers the sacrificial oxide layer, forming spacers around the dummy gate, and successively forming a silicon nitride layer and a dielectric layer covering the silicon nitride layer. The method further includes polishing the dielectric layer until the silicon nitride layer is exposed, polishing the silicon nitride layer on a fixed abrasive pad until the polysilicon layer is exposed by using a polishing slurry with a PH value ranging from 10.5 to 11 and comprising an anionic surfactant or a zwitterionic surfactant. Additionally, the method includes forming an opening after removing the dummy gate, and forming a gate in the opening. The method eliminates potential erosion and dishing caused in the polishing of the silicon nitride layer.

Abstract: A polishing composition that can improve polishing property without foaming is provided. A polishing composition includes a pH regulator, a water-soluble polymer compound, and a compound containing an alkylene diamine structure having two nitrogens represented by the following general formula (1), and having at least one block type polyether bonded to the two nitrogens of the alkylene structure, the block type polyether having a bond of an oxyethylene group and an oxypropylene group: where R represents an alkylene group represented by CnH2n, in which n is an integer of 1 or more.

Abstract: Methods for creating nano-shaped patterns are described. This approach may be used to directly pattern substrates and/or create imprint lithography molds that may be subsequently used to directly replicate nano-shaped patterns into other substrates in a high throughput process.

Abstract: A method of manufacturing a SiC substrate which has a first principal surface and a second principal surface, includes the step of removing, by a vapor phase etching process, at least a portion of a work-affected layer which is formed by mechanical flattening or cutting on the first principal surface of the SiC substrate.

Abstract: Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.

Abstract: The present invention provides a polishing composition that can be suitably used in polishing of polysilicon, and a polishing method using the polishing composition. The polishing composition contains abrasive grains and an anionic surfactant having a monooxyethylene group or a polyoxyethylene group and has a pH of 9 to 12. If the anionic surfactant contained in the polishing composition has a polyoxyethylene group, the number of repeating oxyethylene units in the polyoxyethylene group is preferably 2 to 8. The anionic surfactant contained in the polishing composition can be an anionic surfactant that has a phosphate group, a carboxy group, or a sulfo group as well as a monooxyethylene group or a polyoxyethylene group. The content of the anionic surfactant in the polishing composition is preferably 20 to 500 ppm.

Abstract: The invention provides a polishing composition that contains (a) an abrasive comprising (i) first alpha alumina particles that have an average aspect ratio of 0.8:1 to 1.2:1, (ii) second alpha alumina that have an average aspect ratio of greater than 1.2:1, (iii) fumed alumina particles, and (iv) wet-process silica particles, and (b) water. The invention also provides a method of polishing a substrate, especially a nickel-phosphorous substrate, with the polishing composition.

Abstract: A chemical mechanical polishing slurry composition is provided, having, as initial components: water; an abrasive, wherein the abrasive is colloidal silica abrasive; a halogenated quaternary ammonium compound according to formula (I); optionally, a diquaternary substance according to formula (II); and, optionally, a pH adjusting agent selected from phosphoric acid, nitric acid, sulfuric acid, hydrochloric acid, ammonium hydroxide and potassium hydroxide; wherein the chemical mechanical polishing slurry composition has a pH of 2 to <7. Also, provided are methods for making the chemical mechanical polishing slurry composition and for using the chemical mechanical polishing composition to polish a substrate.

Abstract: A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.

Abstract: Example embodiments are directed to a wafer dividing apparatus and method thereof. The wafer dividing apparatus includes a chuck unit having upper and lower chucks, a cutting wire that is provided in a space between the upper and lower chucks to cut a wafer and driven by a first driving unit, and an etchant supplying nozzle supplying etchant to a groove of the wafer, which is formed by the cutting wire.

Abstract: A method of etching a programmable memory microelectronic device (10) having a substrate covered with at least one of the following layers in succession: a first electrode (2) based on a first metallic element; a layer (4) of chalcogenide doped with a second metallic element; a second electrode (5) based on a third metallic element; a diffusion barrier type electrically-conductive layer (6); and a hard mask (7); is provided. The method includes etching, using an inert gas plasma, at least the hard mask (7), the electrically-conductive layer (6), the second electrode (5) and the chalcogenide layer (4), where the etching step is carried out by cathode sputtering at a temperature strictly less than 150° C., preferably at a temperature of at most 120° C., and particularly preferably at a temperature of at most 100° C.

Abstract: A process for fabricating a semiconductor device includes depositing n-type dopant on a p-type substrate, implanting n-type material into the substrate, and growing an n-type epitaxial layer atop the n+ layer. Trenches surrounding the device region are formed and an n+ layer on the sidewalls of the trenches is formed. The trenches are filled by growing a layer of thermal oxide on the sidewalls of the trenches and deposition of plasma enhanced oxide or polysilicon into the trenches, and planarizing the top surface. n+ region of the device is formed by forming an oxide layer on the top surface of the device layer and etching the oxide, depositing n-type dopant material and driving in by high temperature diffusion. p+ region of the device is formed by etching the oxide, depositing p-type dopant material and driving in by high temperature diffusion so that the breakdown voltage is set for circuit protection.

Abstract: A method for processing a semiconductor wafer includes bringing at least one grinding tool in contact with the semiconductor wafer; removing material from the semiconductor wafer using the grinding tool; disposing a liquid medium having a viscosity of at least 3×10?3 N/m2·s and at most 100×10?3 N/m2·s between the at least one grinding tool and the semiconductor wafer; and separating the at least one grinding tool and the semiconductor wafer so as to end the processing.

Abstract: A polishing method includes polishing, in a first polish, a wafer to remove overburden and planarize a top layer leaving a portion remaining on an underlying layer. A second polishing step includes two phases. In a first phase, the top layer is removed and the underlying layer is exposed, with a top layer to underlying layer selectivity of between about 1:1 to about 2:1 to provide a planar topography. In a second phase, residual portions of the top layer are removed from a top of the underlying layer to ensure complete exposure of an underlying layer surface.

Abstract: A method for chemical mechanical polishing of a substrate is provided, comprising: providing a substrate, wherein the substrate comprises polysilicon and at least one of silicon oxide and silicon nitride; providing a chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; and an alkyl aryl polyether sulfonate compound, wherein the alkyl aryl polyether sulfonate compound has a hydrophobic portion having an alkyl group bound to an aryl ring and a nonionic acyclic hydrophilic portion having 4 to 100 carbon atoms; providing a chemical mechanical polishing pad with a polishing surface; moving the polishing surface relative to the substrate; dispensing the chemical mechanical polishing composition onto the polishing surface; and, abrading at least a portion of the substrate to polish the substrate; wherein at least some of the polysilicon is removed from the substrate; and, wherein at least some of the at least one of silicon oxide and silicon nitride is removed from the su

Abstract: A method for chemical mechanical polishing of a substrate is provided, comprising: providing a substrate, wherein the substrate comprises polysilicon and at least one of silicon oxide and silicon nitride; providing a chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; and an acyclic organosulfonic acid compound, wherein the acyclic organosulfonic acid compound has an acyclic hydrophobic portion having 6 to 30 carbon atoms and a nonionic acyclic hydrophilic portion having 10 to 300 carbon atoms; providing a chemical mechanical polishing pad with a polishing surface; moving the polishing surface relative to the substrate; dispensing the chemical mechanical polishing composition onto the polishing surface; and, abrading at least a portion of the substrate to polish the substrate; wherein at least some of the polysilicon is removed from the substrate; and, wherein at least some of the at least one of silicon oxide and silicon nitride is removed from the substrate.

Abstract: A method for chemical mechanical polishing of a substrate is provided, comprising: providing a substrate, wherein the substrate comprises polysilicon, silicon oxide and silicon nitride; providing a chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; an alkyl aryl polyether sulfonate compound, wherein the alkyl aryl polyether sulfonate compound has a hydrophobic portion having an alkyl group bound to an aryl ring and a nonionic acyclic hydrophilic portion having 4 to 100 carbon atoms; and a substance according to formula I wherein each of R1, R2, R3, R4, R5, R6 and R7 is a bridging group having a formula —(CH2)n—, wherein n is an integer selected from 1 to 10; providing a chemical mechanical polishing pad with a polishing surface; moving the polishing surface relative to the substrate; dispensing the chemical mechanical polishing composition onto the polishing surface; and, abrading at least a portion of the substrate to polish the substrate; wherein at least s

Abstract: A chemical mechanical polishing aqueous dispersion is used to polish a polishing target that includes an interconnect layer that contains tungsten. The chemical mechanical polishing aqueous dispersion includes: (A) a cationic water-soluble polymer; (B) an iron (III) compound; and (C) colloidal silica particles. The content (MA) (mass %) of the cationic water-soluble polymer (A) and the content (MB) (mass %) of the iron (III) compound (B) satisfy the relationship “MA/MB=0.004 to 0.1”. The chemical mechanical polishing aqueous dispersion has a pH of 1 to 3.

Abstract: A polishing slurry for metal comprises an oxidizer, a metal oxide dissolving agent, a metal inhibitor, and water, wherein the metal inhibitor is at least one of a compound having an amino-triazole skeleton and a compound having an imidazole skeleton. The use of the polishing slurry for metal makes it possible to raise the polishing speed sufficiently while keeping the etching speed low, restrain the generation of corrosion of the surface of a metal and dishing, and form a metal-film-buried pattern having a high reliability in the process of formation of wiring of semiconductor devices.

Abstract: A through via process is performed on a semiconductor substrate with a contact plug formed in an interlayer dielectric (ILD), and then a via plug is formed in the ILD layer to extend through a portion of the semiconductor substrate, followed forming an interconnection structure electrically connected with the contact plug and the via plug.

Abstract: A chemical mechanical polishing aqueous dispersion that is used to polish a polishing target that includes a wiring layer that contains tungsten, the chemical mechanical polishing aqueous dispersion including: (A) a cationic water-soluble polymer; (B) an iron (III) compound; and (C) colloidal silica having an average particle diameter calculated from a specific surface area determined by the BET method of 10 to 60 nm, the content (MA) (mass %) of the cationic water-soluble polymer (A) and the content (MC) (mass %) of the colloidal silica (C) satisfying the relationship “MA/MC=0.0001 to 0.003”, and the chemical mechanical polishing aqueous dispersion having a pH of 1 to 3.

Abstract: The present teachings provide methods for forming organic layers for an organic light-emitting device (OLED) using a thermal printing process. The method can further use one or more additional processes, such as vacuum thermal evaporation (VTE), to create an OLED stack. OLED stack structures are also provided wherein at least one of the charge injection or charge transport layers is formed by a thermal printing method at a high deposition rate. The organic layer can be subject to post-deposition treatment such as baking. The structure of the organic layer can be amorphous, crystalline, porous, dense, smooth, rough, or a combination thereof, depending on deposition parameters and post-treatment conditions. The organic layer can improve light out-coupling efficiency of an OLED, increase conductivity, decrease index of refraction, and/or modify the emission chromaticity of an OLED. An OLED microcavity is also provided and can be formed by one of more of these methods.

Abstract: Manufacturing an electrode assembly comprising forming an intermediate assembly comprising a carrier member having one or more electrode contacts embedded therein, the surface of the electrode contacts having a layer of carrier member material thereon; removing the layer of carrier member from the surface of the one or more electrode contacts, wherein a residual amount of the carrier member material remains on the surface of at least one of the electrode contacts; and substantially removing the residual carrier member material from the surface of the at least one electrode contact so as to increase the effective surface area of the at least one electrode contact.

Abstract: A chemical mechanical polishing composition, comprising, as initial components: water; 0.1 to 20 wt % abrasive having an average particle size of 5 to 50 nm; and, 0.001 to 1 wt % of an adamantyl substance according to formula (II): wherein A is selected from N and P; wherein each R8 is independently selected from hydrogen, a saturated or unsaturated C1-15 alkyl group, C6-15 aryl group, C6-15 aralkyl group, C6-15 alkaryl group; and, wherein the anion in formula (II) can be any anion that balances the positive charge on the cation in formula (II).