Abstract: A polysilicon structure and method of forming the polysilicon structure are disclosed, where the method includes a two-step deposition and planarization process. The disclosed process reduces the likelihood of defects such as voids, particularly where polysilicon is deposited in a trench having a high aspect ratio. A first polysilicon structure is deposited that includes a trench liner portion and a first upper portion. The trench liner portion only partially fills the trench, while the first upper portion extends over the adjacent field isolation structures. Next, at least a portion of the first upper portion of the first polysilicon structure is removed. A second polysilicon structure is then deposited that includes a trench plug portion and a second upper portion. The trench is filled by the plug portion, while the second upper portion extends over the adjacent field isolation structures. The second upper portion is then removed.

Abstract: A method for reclaiming a surface of a substrate, wherein the surface, in particular a silicon surface, comprises a protruding residual topography, comprising at least the layer of a first material. By providing a filling material in the non-protruding areas of the surface of the substrate and the subsequent polishing, the reclaiming can be carried out such that the material consuming double-sided polishing step used in the prior art is no longer necessary.

Abstract: A chemical mechanical polishing composition useful for chemical mechanical polishing a semiconductor wafer containing an interconnect metal is provided, comprising, as initial components: water; an azole inhibitor; an alkali metal organic surfactant; a hydrotrope; a phosphorus containing agent; a water soluble cellulose; optionally, a non-saccharide water soluble polymer; optionally, a water soluble acid compound of formula I, wherein R is selected from a hydrogen and a C1-5 alkyl group, and wherein x is 1 or 2; optionally, a complexing agent; optionally, an oxidizer; optionally, an organic solvent; and, optionally, an abrasive.

Abstract: A method of forming an aperture (e.g., a through via, a blind via, a trench, an alignment feature, etc.) within a substrate includes irradiating a substrate with a laser beam to form a laser-machined feature having a sidewall. The laser-machined feature is then processed to change at least one characteristic (e.g., the sidewall surface roughness, diameter, taper, aspect ratio, cross-sectional profile, etc.) of the laser-machined feature. The laser-machined feature can be processed to form the aperture by performing an isotropic wet-etch process employing an etchant solution containing HNO3, HF and, optionally acetic acid.

Abstract: The various embodiments described in the specification provide improved mechanisms of removal of unwanted deposits on the bevel edge to improve process yield. The embodiments provide apparatus and methods of treating the bevel edge of a copper plated substrate to convert the copper at the bevel edge to a copper compound that can be wet etched with a fluid at a high etch selectivity in comparison to copper. In one embodiment, the wet etch of the copper compound at high selectivity to copper allows the removal of the non-volatile copper at substrate bevel edge in a wet etch processing chamber. The plasma treatment at bevel edge allows the copper at bevel edge to be removed at precise spatial control to about 2 mm or below, such as about 1 mm, about 0.5 mm or about 0.25 mm, to the very edge of substrate.

Abstract: A polishing liquid for polishing a barrier layer of a semiconductor integrated circuit, which liquid includes: a quaternary ammonium cation; a corrosion inhibiting agent; a polymer compound having a sulfo group at a terminal; inorganic particles; and an organic acid, the pH of the polishing liquid being in the range of 1 to 7.

Abstract: The present invention provides an aqueous CMP slurry composition that includes abrasive particles and from about 0.01% to the limit of solubility in water of a compound according to Formula (I): wherein only one of R1, R2, R3, R4 and R5 is a hydroxyl group (—OH), only one of R1, R2, R3, R4 and R5 is a methoxy group (—OCH3), and the three of R1, R2, R3, R4 and R5 that are not either a hydroxyl group (—OH) or a methoxy group (—OCH3) are hydrogen atoms (—H).

Abstract: A method and system for fabricating an optical component are described. The method and system include providing a first planarization stopping and a second planarization stopping structure. The first planarization stopping structure has a first height and a first edge. The second planarization stopping structure has a second height different from the first height and a second edge. The first edge is separated from the second edge by a distance. The method and system also include providing an optical material. The optical material resides at least between the first edge of the first planarization stopping structure and the second edge of the second planarization stopping structure. The method and system also include planarizing the optical components. The planarization removes a portion of the optical material to form a surface between the first planarization stopping structure and the second planarization stopping structure. This surface has a curvature.

Abstract: The invention relates to a method for incorporating a structure into a surface of a workpiece that is transparent in a certain wavelength range. For this purpose the surface to be structured is brought into contact with a target surface containing a target material by means of a laser beam, the wavelength of which is within the certain wavelength range, energy is introduced at least at one position through the workpiece and into the boundary region of the surface to be structured and the target surface such that target material is deposited at the respective position in and/or on the surface to be structured. For this purpose a pulsed laser beam having a pulse repetition rate of more than 10 kHz is used, which is focused such that the focus is positioned on or under the target surface, wherein the laser beam has a power density in the focus of more than 2000 W/mm2. The invention further relates to a device for introducing a structure into a surface of a workpiece transparent in a certain wavelength range.

Abstract: Method for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer, and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask exposes a surface of only the second portion of the cap layer which has the greater height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer. Material can be removed from the dielectric layer where exposed to the etchant.

Abstract: A method is provided for growing a stable p-type ZnO thin film with low resistivity and high mobility. The method includes providing an n-type Li—Ni co-doped ZnO target in a chamber, providing a substrate in the chamber, and ablating the target to form the thin film on the substrate.

Abstract: A chemical-mechanical polishing process includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a cap layer is formed over the polished dielectric layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second conductive line that couples electrically with the first conductive line through the via opening.

Abstract: Semiconductor wafers are produced by a process of: a) providing a semiconductor wafer by cutting a silicon ingot into wafers; b) rounding the edge of the wafer, so that the wafer comprises plane surfaces on the frontside and backside and rounded oblique surfaces in the edge region; c) polishing the frontside and backside of the wafer, the frontside being polished by chemical-mechanical polishing using a polishing pad which is free of abrasive fixed in the polishing pad; backside polishing being carried out in three steps, using a polishing pad containing fixed abrasive which is pressed onto the backside of the wafer, a polishing agent free of solids introduced between the polishing pad and the backside of the wafer in the first step, a polishing agent containing abrasive being introduced in the second and third steps, a polishing pressure of 8-15 psi in the first and second steps being reduced to 0.5-5 psi in the third step.

Abstract: Provided are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes a substrate; an sealing substrate facing the substrate, an organic light emitting unit disposed between the substrate and the sealing substrate and having a plurality of organic light emitting devices emitting light, and a plurality of grooves formed in a light extracting surface of the organic light emitting display device through which the light is emitted to the outside. In one embodiment, the grooves are formed on the sealing substrate, and in another embodiment, the grooves are formed on the substrate.

Abstract: Methods and apparatus for reducing damage of a semiconductor donor wafer include the steps of: (a) rotating a polishing pad, rotating the semiconductor donor wafer, applying a polishing slurry to the polishing pad, and pressing the semiconductor donor wafer and the polishing pad together; and (b) rotating the polishing pad and the semiconductor donor wafer, discontinuing the application of the polishing slurry, applying a rinsing fluid to the polishing pad, and pressing the semiconductor donor wafer and the polishing pad together, wherein step (a) followed by step (b) is carried out in sequence at least two times, and at least one of the following are reduced in at least two successive intervals of step (a): (i) a pressure at which the semiconductor donor wafer and the polishing pad are pressed together, (ii) a mean particle size of an abrasive within the polishing slurry, and (iii) a concentration of the slurry in water and stabilizers.

Abstract: A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.

Abstract: Versatile methods of refining a first and a second layer of a workpiece are discussed. New refining methods and refining apparatus are disclosed. The new refining methods can help improve yield and appreciably change the cost of manufacture for refining of workpieces. The methods can be applied to workpieces having extremely close tolerances such as semiconductor wafers. New methods of control are also discussed. Methods use controllers, processors, computers, and processor readable memory devices are discussed. Use of stored information is to make changes in process control are discussed. Use of process models are discussed for refining. Determining a changed process control with stored information from first and second layers of a workpiece is disclosed. A changed process control can make an appreciable changes to the cost of manufacture of a workpiece.

Abstract: An object of the present invention is to provide a polishing pad which enables high accuracy optical end-point detection in a state where polishing is carrying out, and which can prevent slurry leakage from a polishing layer to a cushion layer even in the case of being used for a long period. Another object is to provide a method for producing a semiconductor device using the polishing pad. The present invention relates to a polishing pad in which a polishing layer having a polishing region and a light-transmitting region, and a cushion layer having a through hole are laminated via a double-sided adhesive sheet such that the light-transmitting region and the through hole are laid one upon another, wherein a transparent member is stuck on an adhesive layer of the double-sided adhesive sheet in the through hole.

Abstract: The present invention relates to a polishing slurry including: a colloidal silica having an average particle size of 40 nm or more; water; and a ? potential adjusting component, in which the ? potential adjusting component includes at least one water-soluble organic polymer selected from a water-soluble polyether polyamine and a water-soluble polyalkylene polyamine and at least one acid selected from hydrochloric acid, sulfuric acid, nitric acid, nitrous acid and amidosulfuric acid, and the ? potential adjusting component contains the acid at a ratio of from 0.6 to 1.4 to the water-soluble organic polymer in terms of molar ratio, and the polishing slurry has a pH of 8 or more.

Abstract: A method for producing a semiconductor wafer includes a number of steps in order including a bilateral material-removing process followed by rounding off an edge of the wafer and grinding front and back sides of the wafer by holding one side and grinding the other. The front and back arc then polished with a polishing cloth including bound abrasives and subsequently treated with an etching medium to carry out a material removal of no more than 1 ?m on each side. The front side is then polished using a polishing cloth including bound abrasives and the back side is simultaneously polished using a polishing cloth free of abrasives while a polish with abrasives is provided. The edge is then polished followed by polishing the back with a polishing cloth including bound abrasives and simultaneously polishing the front with a cloth free of abrasives while a polish including abrasives is provided.

Abstract: A method for making a semiconductor device includes forming a first mask pattern on a device layer, forming a second mask pattern on the first mask pattern, etching the device layer not covered by the first and second mask patterns to thereby form a first trench, trimming the first mask pattern to form an intermediate mask pattern, depositing a material layer to fill the first trench, polishing the material layer to expose a top surface of the intermediate mask pattern, removing the intermediate mask pattern to form an opening, etching the device layer through the opening to thereby form a second trench.

Abstract: There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing liquid at least once, and each step of polishing with the polishing liquid employs a basic polishing liquid or an acidic polishing liquid as the polishing liquid. The step of polishing with the basic or acidic polishing liquid allows removal of impurity such as abrasive grains remaining on the surface of the group III nitride crystal after it is polished with the slurry containing the abrasive grains.

Abstract: The surrounding length of a junction separation portion can be shortened to improve an insulating resistance in order to provide a solar cell with highly efficiency. In a photoelectric transducer of the type where a light-receiving surface electrode is wired to another electrode on a back surface via a through electrode passing through a semiconductor substrate of a first conductive type, the photoelectric transducer comprises: a junction separation portion made around the through electrode on a back surface of the semiconductor substrate; a dielectric layer formed for covering the junction separation portion, the through electrode penetrating the dielectric layer; and a back electrode provided on the dielectric layer and coupled to the through electrode which is connected to the light-receiving surface electrode.

Abstract: A polishing liquid for a chemical mechanical polishing of a semiconductor device includes (a) a carboxylic acid compound having one or more carboxy groups, (b) colloidal silica particles having a ? potential of ?10 mV to ?35 mV when used in the polishing liquid, (c) a benzotriazole derivative, (d) an anionic surfactant, and (e) an oxidizing agent, and the polishing liquid has a pH of from 5.0 to 8.0.

Abstract: A CMP slurry for metallic film is provided, which includes water, 0.01 to 0.3 wt %, based on a total quantity of the slurry, of polyvinylpyrrolidone having a weight average molecular weight of not less than 20,000, an oxidizing agent, a protective film-forming agent containing a first complexing agent for forming a water-insoluble complex and a second complexing agent for forming a water-soluble complex, and colloidal silica having a primary particle diameter ranging from 5 to 50 nm.

Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.

Abstract: Methods for performing damage etch and texturing of single crystal silicon substrates, particularly for use as solar cells or photovoltaic cells. Damage etch with a TMAH solution followed by texturing using solution of KOH or NaOH mixed with IPA is particularly advantageous. The substitution of some of the IPA with ethylene glycol further improves results. Also disclosed is a process that combines both damage etch and texturing etch into a single step.

Abstract: A stacking carrier and a stacking method are provided. The stacking method is used between a wafer and a stacking carrier having the same shape. The stacking method includes the following steps. Firstly, an adhesive layer is coated on a surface of the carrier. Then, the adhesive layer corresponding to an edge of the carrier is partially removed, thereby defining at least one adhesive layer indentation. Afterwards, the wafer is stacked on the carrier through the adhesive layer having the adhesive layer indentation.

Abstract: The invention relates to a method for recycling a substrate with a step-like residue in a first region of its surface, in particular along the edge of the substrate, which protrudes with respect to the surface of a remaining second region of the substrate, and wherein the first region comprises a modified zone, in particular an ion implanted zone, essentially in a plane corresponding to the plane of the surface of the remaining second region of the substrate and/or chamfered towards the edge of the substrate. To prevent the negative impact of contaminants in subsequent laminated wafer fabricating processes, the recycling method comprises a material removal step which is carried out such that the surface of the substrate in the first region is lying lower than the level of the modified zone before the material removal.

Abstract: Suspensions of cerium oxide particles in which the particles (secondary particles) have an average size not exceeding 200 nm, such secondary particles being comprised of primary particles having an average size not exceeding 100 nm with a standard deviation having a value not exceeding 30% of the value of this average size, are prepared from a solution of a cerium-III salt, including cerium IV or hydrogen peroxide, which is contacted with a base in the presence of nitrate ions and in an inert atmosphere; the medium thus obtained is subjected to a thermal processing in an inert atmosphere, then acidified and scrubbed and the powder is obtained by drying and calcining of the suspension, which suspension and powder are useful for polishing applications.

Abstract: Provided is a method of preparing an SOI substrate having a backside roughened which the SOI substrate has a reduced number of defects in a silicon layer at the front surface in spite of sandblasting having been applied to the backside of the SOI substrate. Specifically provided is the method comprising the steps of: etching 10 nm or more of a surface of a silicon film of an SOI substrate; sandblasting a backside of the SOI substrate with protective tape attached to the etched surface of the silicon film, the back side being the other side of the SOI substrate from the etched surface; removing the protective tape after the sandblasting; and polishing and cleaning a silicon film surface from which the protective tape has been removed.

Abstract: A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns.

Abstract: A microscopic metallic structure is produced by creating or exposing a patterned region of increased conductivity and then forming a conductor on the region using electrodeposition. In some embodiments, a microscopic metallic structure is formed on a substrate, and then the substrate is etched to remove the structure from the substrate. In some embodiments, a focused beam of gallium ion without a deposition precursor gas scans a pattern on a silicon substrate, to produce a conductive pattern on which a copper structure is then formed by electrochemical deposition of one or more metals. The structure can be freed from the substrate by etching, or can used in place. A beam can be used to access an active layer of a transistor, and then a conductor can be electrodeposited to provide a lead for sensing or modifying the transistor operation while it is functioning.

Abstract: The invention relates to a chemical-mechanical polishing composition comprising silica, one or more organic carboxylic acids or salts thereof, one or more polysaccharides, one or more bases, optionally one or more surfactants and/or polymers, optionally one or more reducing agents, optionally one or more biocides, and water, wherein the polishing composition has an alkaline pH. The polishing composition exhibits a high removal rate and low particle defects and low haze. The invention further relates to a method of chemically-mechanically polishing a substrate using the polishing composition described herein.

Abstract: A method of manufacturing a dual face package, including: preparing an upper substrate composed of an insulating layer including a post via-hole; forming a filled electrode in a semiconductor substrate, the filled electrode being connected to a die pad; applying an adhesive layer on one side of the semiconductor substrate including the filled electrode, and attaching the upper substrate to the semiconductor substrate; cutting another side of the semiconductor substrate in a thickness direction, thus making the filled electrode into a through-electrode; and forming a post electrode in the post via-hole, forming an upper redistribution layer connected to the post electrode of the semiconductor substrate, and forming a lower redistribution layer connected to the through-electrode on the other side of the semiconductor substrate.

Abstract: A circumferential portion of an epitaxial wafer is removed to remove an anomalously grown elevated portion formed in a circumferential chamfer. An epitaxial layer in the circumferential portion is removed with a width q=t to 5t wherein t is the thickness of the epitaxial layer so that the surface of a substrate is exposed. Therefore, cracking of the epitaxial layer in processing steps can be prevented.

Abstract: The invention provides a chemical-mechanical polishing composition for polishing a substrate. The polishing composition comprises silica, a compound selected from the group consisting of an amine-substituted silane, a tetraalkylammonium salt, a tetraalkylphosphonium salt, and an imidazolium salt, a carboxylic acid having seven or more carbon atoms, an oxidizing agent that oxidizes a metal, and water. The invention further provides a method of chemically-mechanically polishing a substrate with the aforementioned polishing composition.

Abstract: A composition and associated method for chemical mechanical planarization of a metal-containing substrate (e.g., a copper substrate) are described herein which afford high and tunable rates of metal removal as well as low dishing and erosion levels during CMP processing.

Abstract: A process for forming a copper wiring and the prevention of copper ion migration in a semiconductor device is disclosed herein. The process includes conducting a post-cleaning process for a copper layer that is to form the cooper wiring after already having undergone a CMP process. The post-cleaning process includes conducting a primary chemical cleaning using a citric acid-based chemical. A secondary chemical cleaning is then conducted on the copper layer having undergone the primary chemical cleaning using an ascorbic acid-based chemical. After the post-cleaning process is completed, the migration of copper ions over time is prevented thereby improving the reliability of the semiconductor device.

Abstract: The invention provides chemical-mechanical polishing (CMP) compositions and methods for polishing a silicon-containing substrate. A method of the invention comprises the steps of contacting a silicon-containing substrate with a polishing pad and an aqueous CMP composition, and causing relative motion between the polishing pad and the substrate while maintaining a portion of the CMP composition in contact with the surface of the substrate to abrade at least a portion of the substrate. The CMP composition comprises a ceria abrasive, a polishing additive bearing a functional group with a pKa of about 4 to about 9, a nonionic surfactant with an hydrophilic portion and a lipophilic portion wherein the hydrophilic portion has a number average molecular weight of about 500 g/mol or higher, and an aqueous carrier, wherein the pH of the composition is 7 or less. The method reduces defects on the wafers, particularly local areas of high removal.

Abstract: The present invention relates to a method for manufacturing an acceleration sensor. In the method, thin SOI-wafer structures are used, in which grooves are etched, the walls of which are oxidized. A thick layer of electrode material, covering all other material, is grown on top of the structures, after which the surface is ground and polished chemo-mechanically, thin release holes are etched in the structure, structural patterns are formed, and finally etching using a hydrofluoric acid solution is performed to release the structures intended to move and to open a capacitive gap.

Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

Abstract: A chemical mechanical polishing composition, comprising, as initial components: water; 0.1 to 40 wt % abrasive having an average particle size of 5 to 150 nm; 0.001 to 1 wt % of an adamantyl substance according to formula (II); 0 to 1 wt % diquaternary substance according to formula (I); and, 0 to 1 wt % of a quaternary ammonium compound. Also, provided is a method for chemical mechanical polishing using the chemical mechanical polishing composition.

Abstract: A method comprising: providing at least one first diamond film comprising polycrystalline diamond, e.g., nanocrystalline or ultrananocrystalline diamond, disposed on a substrate, wherein the first diamond film comprises a surface comprising diamond asperities and having a first diamond film thickness, removing asperities from the first diamond film to form a second diamond film having a second diamond film thickness, wherein the second thickness is either substantially the same as the first thickness, or the second thickness is about 100 nm or less thinner than the first diamond film thickness, optionally patterning the second diamond film to expose substrate regions and, optionally, depositing semiconductor material on the exposed substrate regions, and depositing a solid layer on the second diamond film to form a first layered structure.

Abstract: A method of relieving stress in a semiconductor wafer and providing a wafer backside surface finish capable of hiding cosmetic imperfections. Embodiments of the invention include creating a wafer backside surface which can be used for all dies on the semiconductor wafer intended for different product applications and be deposited with backside metallization (BSM) material. The method provides a rough texture on the wafer backside followed by isotropic etching of the wafer backside to recover the wafer strength as well as to preserve the rough texture of the wafer backside. After wafer backside metallization, the rough texture of the wafer backside hides cosmetic imperfections introduced by subsequent processes.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other.

Abstract: Devices and methods for electrical interconnection for microelectronic circuits are disclosed. One method of electrical interconnection includes forming a bundle of microfilaments, wherein at least two of the microfilaments include electrically conductive portions extending along their lengths. The method can also include bonding the microfilaments to corresponding bond pads of a microelectronic circuit substrate to form electrical connections between the electrically conductive portions and the corresponding bond pads. A microelectronic circuit can include a bundle of microfilaments bonded to corresponding bond pads to make electrical connection between corresponding bonds pads and electrically-conductive portions of the microfilaments.

Abstract: Objects of the invention are to further enhance crystallinity and crystallinity uniformity of a semiconductor crystal produced through the flux method, and to effectively enhance the production yield of the semiconductor crystal. The c-axis of a seed crystal including a GaN single-crystal layer is aligned in a horizontal direction (y-axis direction), one a-axis of the seed crystal is aligned in the vertical direction, and one m-axis is aligned in the x-axis direction. Thus, three contact points at which a supporting tool contacts the seed crystal are present on m-plane. The supporting tool has two supporting members, which extend in the vertical direction. One supporting member has an end part, which is inclined at 30° with respect to the horizontal plane ?. The reasons for supporting a seed crystal at m-plane thereof are that m-plane exhibits a crystal growth rate, which is lower than that of a-plane, and that desired crystal growth on c-plane is not inhibited.

Abstract: A method for fabricating a capacitor includes forming a first storage node (SN) oxide layer over a substrate, forming a second SN oxide layer over the first SN oxide layer, forming a mask pattern over the second SN oxide layer, dry-etching the first and the second SN oxide layers using the mask pattern as an etch barrier to form a capacitor region, and wet-etching a resultant structure including the capacitor region to enlarge a bottom width of the capacitor region, thereby forming a final capacitor region having the enlarged bottom width, wherein the first SN oxide layer comprises one portion of high impurity concentration and the other portion of low impurity concentration, the one portion corresponding to a region where the final capacitor region is to be formed.

Abstract: A method for patterning a multilayered conductor/substrate structure includes the steps of: providing a multilayered conductor/substrate structure which includes a plastic substrate and at least one conductive layer overlying the plastic substrate; and irradiating the multilayered conductor/substrate structure with ultraviolet radiation such that portions of the at least one conductive layer are ablated therefrom. In a preferred embodiment, a projection-type excimer laser system is employed to rapidly and precisely ablate a pattern from a mask into the at least one conductive layer. Preferably, the excimer laser is controlled in consideration of how well the at least one conductive layer absorbs radiation at particular wavelengths. Preferably, a fluence of the excimer laser is controlled in consideration of an ablation threshold level of at least one conductive layer.