Abstract: A method for manufacturing a phase change memory device that prevents or minimizes adverse performance characteristics associated with inadequate overlap between top electrode contacts and top electrodes. The method prevents or minimizes unwanted chemical changes and etch losses of the phase change material when building the top electrode. The method includes forming spacers on sidewalls of remaining portions of the insulation layer and the hard masks so that subsequent etching of the conductive layer and the phase change material layer uses the spacers and the hard masks as an etch mask to form top electrodes and a phase change layer. Accordingly, the method promises to provide a way of achieving a high level of integration for the resultant phase change memory devices.

Abstract: The present disclosure provides a concentrate for use in chemical mechanical polishing slurries, and a method of diluting that concentrate to a point of use slurry. The concentrate comprises abrasive, complexing agent, and corrosion inhibitor, and the concentrate is diluted with water and oxidizer. These components are present in amounts such that the concentrate can be diluted at very high dilution ratios, without affecting the polishing performance.

Abstract: A method is provided for growing a stable p-type ZnO thin film with low resistivity and high mobility. The method includes providing an n-type Li—Ni co-doped ZnO target in a chamber, providing a substrate in the chamber, and ablating the target to form the thin film on the substrate.

Abstract: A process for removing contaminating metals from a substrate to improve electrical performance is provided. Polycationic metals are known to be particularly detrimental to the electrical properties of an insulator or semiconductor substrate. The process includes the exposure of the substrate to an aqueous solution of at least one compound of the formula: (I) where n in each occurrence is independently an integer value between 0 and 6, and X is independently in each occurrence H, NR4, Li, Na or K and at least one of X is NR4; where R in each occurrence is independently H or C1-C6 alkyl, to improve electrical performance of the substrate. A kit for preparing such a solution includes a 1-20 total weight percent aqueous concentrate of at least one compound of formula (I). The kit also provides instructions for the dilution of the concentrate to form the solution.

Abstract: A method of manufacturing an electronic device that comprises a microelectromechanical (MEMS) element, the method comprising the steps of: providing a material layer (34) on a first side of a substrate (32); providing a trench (40) in the material later (34); etching material from the trench (40) such as to also etch the substrate (32) from the first side of the substrate (32); grinding the substrate (32) from a second side of the substrate to expose the trench (40); and using the exposed trench (40) as an etch hole. The exposed trench (40) is used as an etch hole for releasing a portion of the material layer (34), for example a beam resonator (12), from the substrate (32). An input electrode (6), an output electrode (8), and a top electrode (10) are provided.

Abstract: Various embodiments of the invention include methods and systems for trimming electronic circuits using short laser pulses of near-infrared wavelength at a high repetition rate. The laser pulses ablate material from a spot on a circuit with minimal thermal and photoelectric disturbances to circuit performance. Minimal disturbance to circuit performance allows for repeated trimming and testing without pausing for circuit reinitialization. To optimize trimming, the laser pulses can also be adjusted responsive to the composition of the material ablated. In some embodiments, the system is configured to trim a plurality of circuits in parallel.

Abstract: Disclosed is an adjuvant for use in simultaneous polishing of a cationically charged material and an anionically charged material, which forms an adsorption layer on the cationically charged material in order to increase polishing selectivity of the anionically charged material, wherein the adjuvant comprises a polyelectrolyte salt containing: (a) a mixture of a linear polyelectrolyte having a weight average molecular weight of 2,000˜50,000 with a graft type polyelectrolyte that has a weight average molecular weight of 1,000˜20,000 and comprises a backbone and a side chain; and (b) a basic material. CMP (chemical mechanical polishing) slurry comprising the above adjuvant and abrasive particles is also disclosed.

Abstract: The invention discloses a method of fabricating a first substrate and a method of recycling a second substrate during fabrication of the first substrate. The second substrate is heterogeneous for the first substrate. First, the fabricating method according to the invention is to prepare the second substrate. Subsequently, the fabricating method is to deposit a buffer layer on the second substrate. Then, the fabricating method is to deposit a semiconductor material layer on the buffer layer. The buffer layer assists the epitaxial growth of the semiconductor material layer, and serves as a lift-off layer. Finally, with an etching solution, the fabricating method is to only etch the lift-off layer to debond the second substrate away from the semiconductor material layer, where the semiconductor material layer serves as the first substrate.

Abstract: Compound-semiconductor-substrate polishing methods, compound semiconductor substrates, compound-semiconductor-epitaxial-substrate manufacturing methods, and compound semiconductor epitaxial substrates whereby oxygen superficially present on the substrates reduced. A compound semiconductor-substrate polishing method includes a preparation step (S10), a first polishing step (S20), and a second polishing step (S30). In the preparation step (S10), a compound semiconductor substrate is prepared. In the first polishing step (S20), the compound semiconductor substrate is polished with a chloric polishing agent. In the second polishing step (S30), subsequent to the first polishing step (S20), a polishing operation utilizing an alkaline aqueous solution containing an inorganic builder and having pH of 8.5 to 13.0 inclusive is performed.

Abstract: A disclosed device includes a manufacturing method of semiconductor device including preparing a semiconductor substrate including semiconductor chip forming regions, scribing regions surrounding these regions, and cutting regions formed in the scribing regions and narrower than the scribing regions, forming check patterns and semiconductor chips, forming a resist film, forming through grooves narrower than the scribing regions and wider than the check patterns and the cutting regions, removing the check patterns with a wet blast process using the resist film and collectively forming grooves at portions of a protection film and the semiconductor substrate facing the through grooves, removing the resist film, forming internal connection terminals on the contacting faces, forming an insulating resin layer, forming a wiring forming face by removing until connecting faces are exposed, forming wiring patterns, and cutting the semiconductor substrate, the insulating resin layer, and a solder resist layer to separat

Abstract: A method of manufacturing a thin TFT over a flexible substrate is provided. In formation of a TFT on a surface of a substrate having heat resistance, a liquid repellent film is formed selectively on a surface of the substrate, and an organic film is formed thereover. An element such as a TFT is formed over the organic film. Since the liquid repellent film is formed over the substrate, adhesion between the substrate and the organic film is low; therefore, the element which is formed can be peeled off from the substrate easily. Further, since the element is not transferred to another substrate, a semiconductor device which is thinner than conventional ones can be manufactured. In order to form the liquid repellent film selectively, light exposure of a front surface or a back surface of the substrate provided with a mask, a droplet discharging method, or the like is used.

Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a photo resist material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.

Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region.

Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.

Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.

Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a doped dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.

Abstract: The disclosure pertains to compositions and methods for modifying or refining the surface of a wafer suited for semiconductor fabrication. The compositions include working liquids useful in modifying a surface of a wafer suited for fabrication of a semiconductor device. In some embodiments, the working liquids are aqueous solutions of initial components substantially free of loose abrasive particles, the components including water, a surfactant, and a pH buffer exhibiting at least one pKa greater than 7. In certain embodiments, the pH buffer includes a basic pH adjusting agent and an acidic complexing agent, and the working liquid exhibits a pH from about 7 to about 12. In further embodiments, the disclosure provides a fixed abrasive article comprising a surfactant suitable for modifying the surface of a wafer, and a method of making the fixed abrasive article. Additional embodiments describe methods that may be used to modify a wafer surface.

Abstract: The instant invention is a method of polishing a substrate including contacting a substrate having at least one metal layer including copper with a chemical-mechanical polishing composition. The CMP composition includes an abrasive, a surfactant, an oxidizer, an organic acid including polyacrylic acid or polymethacrylic acid, a corrosion inhibitor, and a liquid carrier. A portion of the copper in the metal layer is abraded to polish the substrate. A second CMP composition contacts the abraded substrate, the second acrylate free composition including an abrasive, a surfactant, an oxidizer, and a corrosion inhibitor, and a liquid carrier. Any dendrites that may have formed on the substrate are removed through abrasion.

Abstract: A metal-polishing liquid used for chemical-mechanical polishing of a conductor film of copper or a copper alloy in a process for manufacturing a semiconductor device, the metal-polishing liquid comprising: (1) an amino acid derivative represented by the formula (I); and (2) a surfactant, wherein, in the formula (I), R1 represents an alkyl group having 1 to 4 carbon atoms and R2 represents an alkylene group having 1 to 4 carbon atoms.

Abstract: To provide a polishing composition particularly useful for an application to polish a conductor layer made of copper in a semiconductor wiring process, and a polishing process employing it. A polishing composition comprising an anionic surfactant and a nonionic surfactant, characterized in that the composition is prepared so that the water contact angle of the surface of an object to be polished, after being polished by the composition, would be at most 60°.

Abstract: Provided are several polishing compositions useful for modifying a surface, such as a semiconductor wafer suitable for fabrication of a semiconductor device, especially when used in fixed abrasive planarization techniques. The polishing compositions include a synergistic mixture of water, an oxidizing agent, a complexing agent, and metal ions. Also provided are various methods of surface planarization.

Abstract: Methods and apparatuses for removing polysilicon material from a semiconductor workpiece are disclosed. A particular method includes contacting a polishing pad with a semiconductor workpiece having a surface polysilicon material. The method also includes disposing a polishing liquid between the polysilicon material and the polishing pad. The polishing liquid contains an oxidizer that does not include metal elements. The method further includes moving at least one of the semiconductor workpiece and the polishing pad relative to the other while the semiconductor workpiece contacts the polishing pad and the polishing liquid. At least some of the polysilicon material is removed while the polysilicon material contacts the oxidizer in the polishing liquid, as at least one of the semiconductor workpiece and the polishing pad moves relative to the other.

Abstract: A method of fabricating an electronic device, the device including a plurality of layers on a substrate, the layers including an upper conductive layer and at least one patterned underlying layer between said conductive layer and said substrate. The method includes patterning said underlying layer, and patterning said upper conductive layer by laser ablation using a stepwise process in which successive areas of said upper conductive layer are ablated by successively applied laser patterns. The successively applied laser patterns overlap one another in an overlap region. The method further includes configuring a said laser pattern and said patterned underlying layer with respect to one another such that in a said overlap region said patterned underlying layer is substantially undamaged by said stepwise laser ablation.

Abstract: A polishing composition containing at least one or more aminocarboxylic acids selected from the group consisting of serine, cysteine and dihydroxyethylglycine, ceria particles and an aqueous medium; a polishing process of a semiconductor substrate, including the step of polishing a semiconductor substrate with a polishing composition for a semiconductor substrate, containing at least one or more aminocarboxylic acids selected from the group consisting of serine, cysteine and dihydroxyethylglycine, ceria particles and an aqueous medium; a method for manufacturing a semiconductor device including the step of polishing a semiconductor substrate having a film formed on its surface, the film containing a silicon atom and having a shape with dents and projections, with a polishing pad pressed against a semiconductor substrate at a polishing load of from 5 to 100 kPa in the presence of a polishing composition for a semiconductor substrate, containing at least one or more aminocarboxylic acids selected from the group

Abstract: The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF, generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used.

Abstract: A wafer polishing method is provided. First, a wafer, having a first surface, a second surface, and a plurality of opening portions depressed on the first surface, is provided. A plastic adhesive is filled in the opening portions and cured later. A polishing step is performed to thin the thickness of the wafer. Therefore, the yield of the wafer in the polishing process can be improved by the protection of the plastic adhesive.

Abstract: A method includes forming a first layer containing silicon oxide on a first substrate, partially removing the first layer to form an exposure portion on the first substrate, depositing amorphous gallium nitride system compound semiconductor on the first substrate with the exposure portion, evaporating the semiconductor on the first layer to form cores of the semiconductor on the exposure portion of the first substrate, forming an epitaxial layer of the semiconductor on the first substrate, and removing the epitaxial layer of the semiconductor on the exposure portion on the first substrate to form a separating groove.

Abstract: A slurry composition for polishing metal includes a polymeric polishing accelerating agent, the polymeric polishing accelerating agent including a backbone of hydrocarbon and a side substituent having at least one of a sulfonate ion (SO3?) and a sulfate ion (OSO3?), and an acidic aqueous solution.

Abstract: Provided is a method for fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a backside, where active or passive devices are formed in the front side, rotating the semiconductor substrate, and etching the backside of the semiconductor substrate by introducing a first etchant while the substrate is rotated, the first etchant including an R—COOH.

Abstract: A first layer is formed over a substrate, a light absorbing layer is formed over the first layer, and a layer having a light-transmitting property is formed over the light absorbing layer. The light absorbing layer is selectively irradiated with a laser beam via the layer having a light-transmitting property. When the light absorbing layer absorbs energy of the laser beam, due to emission of gas that is within the light absorbing layer, or sublimation, evaporation, or the like of the light absorbing layer, a part of the light absorbing layer and a part of the layer having a light-transmitting property in contact with the light absorbing layer are removed. By using the remaining part of the layer having a light-transmitting property or the remaining part of the light absorbing layer as a mask and etching the first layer, the first layer can be processed into a desired shape.

Abstract: Provided is a method for manufacturing a photovoltaic device which is capable of easily forming a texture having an aspect ratio larger than 0.5. The method for manufacturing a photovoltaic device include the steps of: forming an etching-resistant film on a silicon substrate; forming a plurality of fine holes in the etching-resistant film with an irradiated laser beam which has a focal depth adjusted to 10 ?m or more to expose a surface of the silicon substrate which is a base layer; and etching the exposed surface of the silicon substrate, in which the step of exposing the surface of the silicon substrate includes forming a fine recess at a concentric position to each of the fine holes in the surface of the silicon substrate which lies under the etching-resistant film.

Abstract: To provide a polishing technique with which in production of a semiconductor integrated circuit device, when a plane to be polished is polished, an appropriate polishing rate ratio of a polysilicon film to another material can be obtained, whereby high level planarization of a plane to be polished including a polysilicon film can be realized. A polishing compound for chemical mechanical polishing, containing cerium oxide particles, a water-soluble polyamine and water and having a pH within a range of from 10 to 13, is used.

Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.

Abstract: A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.

Abstract: A slurry composition includes an acidic aqueous solution and one or both of, an amphoteric surfactant and a glycol compound. Examples of the amphoteric surfactant include a betaine compound and an amino acid compound, and examples of the amino acid compound include lysine, proline and arginine. Examples of the glycol compound include diethylene glycol, ethylene glycol and polyethylene glycol.

Abstract: Aqueous cerium oxide dispersion Aqueous cerium oxide dispersion, containing 5 to 60% by weight cerium oxide. It can be used to polish SiO2 in the semiconductor industry.

Abstract: Provided are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes a substrate; an sealing substrate facing the substrate, an organic light emitting unit disposed between the substrate and the sealing substrate and having a plurality of organic light emitting devices emitting light, and a plurality of grooves formed in a light extracting surface of the organic light emitting display device through which the light is emitted to the outside. In one embodiment, the grooves are formed on the sealing substrate, and in another embodiment, the grooves are formed on the substrate.

Abstract: A method for the production of a planar structure is disclosed. The method comprises producing on a substrate a plurality of structures of substantially equal height, and there being a space in between the plurality of structures. The method further comprises providing a fill layer of electromagnetic radiation curable material substantially filling the space between the structures. The method further comprises illuminating a portion of the fill layer with electromagnetic radiation, hereby producing a exposed portion and an unexposed portion, the portions being separated by an interface substantially parallel with the first main surface of the substrate. The method further comprises removing the portion above the interface.

Abstract: A process for splitting a semiconductor substrate having an identification notch on its periphery, by creating a weakened zone in the substrate by implanting atomic species into the substrate while the substrate is held in place on a portion of its periphery during the implanting; and splitting the substrate along the weakened zone by placing the held portion of the substrate in a splitting-wave initiation sector while positioning the notch for initiating a splitting wave followed by the propagation of the wave into the substrate. During splitting the notch is positioned so that it is in a quarter of the periphery of the substrate diametrically opposite the sector for initiating the splitting wave or in the quarter of the periphery of the substrate that is centered on the sector.

Abstract: A system (500) removes wafer edge residue from a target wafer (508). A wafer holding mechanism (502) holds and rotates the target wafer (508). A residue remover mechanism (504) mechanically interacts or abrades an edge surface of the target wafer (508) and removes strongly adhered residue from the edge surface of the target wafer (508). The residue remover mechanism (504) controls coverage of the mechanical interaction and magnitude of the mechanical interaction.

Abstract: The inventive method comprises chemically-mechanically polishing a substrate comprising at least one layer of silicon carbide with a polishing composition comprising a liquid carrier, an abrasive, and an oxidizing agent.

Abstract: A method for forming a pattern in a semiconductor device includes forming an etch-target layer over a substrate, wherein the substrate includes a first region having a smaller pattern than the first region, forming a sacrificial layer and a passivation layer over the etch-target layer, etching the passivation layer and the sacrificial layer to form stack structures including a sacrificial pattern and a passivation pattern, forming spacers over sidewalls of the stack structures, forming a mask pattern covering the second region, removing a portion of the passivation pattern in the first region exposed by the mask pattern to expose a portion of the sacrificial pattern in the first region, removing the exposed portion of the sacrificial pattern in the first region, and etching the etch-target layer to form an etch-target pattern using the spacers in the first and second regions and the stack structure formed between the spacers in the second region.

Abstract: A method of forming a semiconductor device is provided, including a step of forming a layer which absorbs light over one face of a first substrate, a step of providing a second substrate over the layer which absorbs light, a step of providing a mask to oppose the other face of the first substrate, and a step of transferring the part of the layer which absorbs light to the second substrate by irradiating the layer which absorbs light with a laser beam through the mask.

Abstract: The inventive method comprises chemically-mechanically polishing a substrate with an inventive polishing composition comprising a liquid carrier, a cationic polymer, an acid, and abrasive particles that have been treated with an aminosilane compound.

Abstract: A factory, an apparatus, and methods of using an in situ finishing information for finishing workpieces and semiconductor wafers are described. Changes or improvements to cost of manufacture of a workpiece using current in-process cost of manufacture information, tracked current in-process cost of manufacture information, or current cost of manufacture parameters are discussed. Appreciable changes to quality or cost of manufacture of a workpiece using tracking, using in-process tracked information, networks including a multiplicity of apparatus, and using in situ finishing information are discussed. A factory, apparatus, and methods to change or improve process control are discussed. A factory, apparatus, and methods to change or improve real-time process control are discussed. A factory, apparatus, and methods to change or improve feedforward and feedback control are discussed. The workpieces can be tracked individually or by process group such as a process batch.

Abstract: A method for patterning a material during fabrication of a semiconductor device provides for the selective formation of either asymmetrical features or symmetrical features using a symmetrical photomask, depending on which process flow is chosen. The resulting features which are fabricated use spacers formed around a patterned material. If one particular etch is used to remove a base material, symmetrical features result. If two particular etches are used to remove the base material, asymmetrical features remain.

Abstract: The current invention presents a method for thinning wafers. The method uses a two-step process, whereby first the carrier wafer (2) is thinned and in a second step the device wafer (1) is thinned. The method is based on imprinting the combined thickness non-uniformities of carrier (2) and glue layer (3) essentially on the carrier (2), with a resulting low TTV of the wafer (100) after thinning.

Abstract: A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.

Abstract: A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.

Abstract: A method includes placing a first bonding layer on at least one of a first functional region bonded on a release layer with a light releasable adhesive layer on a first substrate, and a transfer region on a second substrate; bonding the first functional region to the second substrate by the first bonding layer; irradiating the release layer with light with a light blocking member being provided to separate the first substrate from the first functional region at the release layer; placing a second bonding layer on at least one of a second functional region on the first substrate, and a transfer region on the release layer or a transfer region on a third substrate; bonding the second functional region to the second substrate or the third substrate by the second bonding layer; and separating the first substrate from the second functional region at the release layer.