Abstract: A method of chemically-mechanically polishing a substrate having a Group III-nitride surface includes providing a chemical-mechanical polishing slurry composition. The slurry composition includes a slurry solution including a liquid carrier and an oxidizer including a transition metal or a per-based compound. The slurry solution includes at least one component that reacts with the Group III-nitride surface to form a softened Group III-nitride surface. The Group III-nitride comprising surface is contacted with the slurry composition by a pad to form the softened Group III-nitride surface. The pad is moved relative to the softened Group III-nitride surface, wherein at least a portion of the softened Group III-nitride surface is removed.

Abstract: Provided is a method of planarizing a semiconductor device. A dielectric layer is formed over a substrate. A plurality of openings is formed in the dielectric layer. The openings have varying distribution densities. The openings are filled with a metal material. A first chemical-mechanical-polishing (CMP) process is performed to remove portions of the metal material over the dielectric layer. Thereafter, a sacrificial layer is formed over the dielectric layer and the metal material. The sacrificial layer has a planar surface. The sacrificial layer is formed through one of: a spin-on process or a flowable chemical vapor deposition (FCVD) process. A second CMP process is then performed to remove the sacrificial layer and portions of the dielectric layer and the metal material therebelow. The second CMP process uses a slurry configured to have a substantially similar polishing selectivity between the sacrificial layer, the dielectric layer, and the metal material.

Abstract: A method of fabricating a semiconductor device includes dressing a surface of a polishing pad with a conditioning disk held by an arm while rotating a platen that holds the polishing pad in a chemical mechanical polishing apparatus, wherein the dressing is performed by pressing the conditioning disk to the polishing pad, and rotating the arm around a rotational axis of the arm thereby to move the conditioning disk substantially along a radius direction of the platen between a center part and a circumferential part of the platen, and wherein torque N applied to the arm is measured at plural positions of the conditioning disk along the substantial radius direction during the dressing, and it is determined whether maintenance to the arm is necessary in accordance with an average value <N> of the measured torques N and a fluctuation range Y of the measured torques N.

Abstract: The present invention relates to a CMP slurry composition comprising an abrasive particle; a dispersant; an ionic polymer additive; and a non-ionic polymer additive including a polyolefin-polyethylene glycol copolymer including at least two polyethylene glycol repeat unit as a backbone and at least a polyethylene glycol repeating unit as a side chain, and a polishing method with using the slurry composition. The CMP slurry composition shows a low polishing rate to a single-crystalline silicon layer or a polysilicon layer and a high polishing rate to a silicon oxide layer, resulting in having an excellent polishing selectivity.

Abstract: A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method also includes performing an ion implantation process to the back surface of the silicon substrate and performing a green laser annealing process to the implanted back surface of the silicon substrate. The green laser annealing process uses an annealing temperature greater than or equal to about 1100° C. for a duration of about 100 to about 400 nsec. After performing the green laser annealing process, a silicon polishing process is performed on the back surface of the silicon substrate.

Abstract: In a method for manufacturing a chemical sensor with multiple sensor cells, a substrate is provided and an expansion inhibitor is applied to the substrate for preventing a sensitive material to be applied to an area on the substrate for building a sensitive film of a sensor cell to expand from said area. The sensitive material is provided and the sensitive film is built by contactless dispensing the sensitive material to said area.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of circuit devices over a substrate. The method includes forming an organic layer over the substrate. The organic layer is formed over the plurality of circuit devices. The method includes polishing the organic layer to planarize a surface of the organic layer. The organic layer is free of being thermally treated prior to the polishing. The organic material is un-cross-linked during the polishing. The method includes depositing a LT-film over the planarized surface of the organic layer. The depositing is performed at a temperature less than about 150 degrees Celsius. The depositing is also performed without using a spin coating process. The method includes forming a patterned photoresist layer over the LT-film.

Abstract: A method for providing waveguide structures for an energy assisted magnetic recording (EAMR) transducer is described. The waveguide structures have a plurality of widths. At least one waveguide layer is provided. Mask structure(s) corresponding to the waveguide structures and having a pattern are provided on the waveguide layer(s). The mask structure(s) include a planarization stop layer, a planarization assist layer on the planarization stop layer, and a hard mask layer on the planarization assist layer. The planarization assist layer has a low density. The pattern of the mask structure(s) is transferred to the waveguide layer(s). Optical material(s) that cover the waveguide layer(s) and a remaining portion of the mask structure(s) are provided. The optical material(s) have a density that is at least twice the low density of the planarization assist layer. The method also includes performing a planarization configured to remove at least a portion of the optical material(s).

Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes a step of forming a dummy-fin semiconductor on a semiconductor substrate; a step of forming an insulating layer, into which a lower part of the dummy-fin semiconductor is buried, on the semiconductor substrate; a step of forming a fin semiconductor, which is bonded to a side face at an upper part of the dummy-fin semiconductor, on the insulating layer; and a step of removing the dummy-fin semiconductor on the insulating layer with the fin semiconductor being left on the insulating layer.

Abstract: A polishing method includes causing a polishing pad arranged on a turn table to rotate together with the turn table, and polishing a surface of a substrate by using the rotating polishing pad while supplying a chemical fluid to a surface of the polishing pad on a fore side of the substrate from an oblique direction with respect to the surface of the polishing pad.

Abstract: A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.

Abstract: The present invention provides chemical-mechanical polishing (CMP) compositions suitable for polishing a substrate comprising a germanium-antimony-tellurium (GST) alloy. The CMP compositions of the present invention are aqueous slurries comprising a particulate abrasive, a water-soluble surface active agent, a complexing agent, and a corrosion inhibitor. The ionic character of the surface active material (e.g., cationic, anionic, or nonionic) is selected based on the zeta potential of the particulate abrasive. A CMP method for polishing a GST alloy-containing substrate utilizing the composition is also disclosed.

Abstract: Compositions useful for the selective removal of silicon nitride materials relative to poly-silicon, silicon oxide materials and/or silicide materials from a microelectronic device having same thereon. The removal compositions include fluorosilicic acid, silicic acid, and at least one organic solvent. Typical process temperatures are less than about 100° C. and typical selectivity for nitride versus oxide etch is about 200:1 to about 2000:1. Under typical process conditions, nickel-based silicides as well as titanium and tantalum nitrides are largely unaffected, and polysilicon etch rates are less than about 1 ? min?1.

Abstract: Disclosed is a CMP slurry for silicon film polishing, comprising abrasive grains, an oxidizing agent, a cationic surfactant, and water. This CMP slurry is suitable for the CMP step of a silicon film of semiconductor devices, since it enables to obtain excellent planarity and excellent performance of controlling the remaining film thickness, while improving the yield and reliability of the semiconductor devices. This CMP slurry also enables to reduce the production cost.

Abstract: A method for manufacturing an epitaxial wafer that can reduce occurrence of a surface defect or a slip formed on an epitaxial layer is provided. The manufacturing method is characterized by comprising: a smoothing step of controlling application of an etchant to a wafer surface in accordance with a surface shape of a silicon wafer to smooth the wafer surface; and an epitaxial layer forming step of forming an epitaxial layer formed of a silicon single crystal on the surface of the wafer based on epitaxial growth.

Abstract: An aqueous CMP agent, comprising (A) solid polymer particles interacting and forming strong complexes with the metal of the surfaces to be polished; (B) a dissolved organic non-polymeric compound interacting and forming strong, water-soluble complexes with the metal and causing an increase of the material removal rate MRR and the static etch rate SER with increasing concentration of the compound (B); and (C) a dissolved organic non-polymeric compound interacting and forming slightly soluble or insoluble complexes with the metal, which complexes are capable of being adsorbed by the metal surfaces, and causing a lower increase of the MRR than the compound (B) and a lower increase of the SER than the compound (B) or no increase of the SER with increasing concentration of the compound (C); a CMP process comprising selecting the components (A) to (C) and the use of the CMP agent and process for polishing wafers with ICs.

Abstract: A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol, a controlled amount of chloride ion source and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.

Abstract: Mirror-polishing a front surface of a silicon wafer using polishing liquid composed of an abrasive grain-free alkaline solution including water-soluble polymers simplifies a polishing process, thus leading to an increase in productivity and a reduction in cost, and reduces the density of LPDs attributable to processing and occurring in the front surface of a mirror-polished wafer, thus improving the surface roughness of the wafer front surface.

Abstract: A method of forming trench isolation with different depths of a semiconductor device is disclosed. A semiconductor substrate having a first mask layer formed thereon is first provided. A first etching process is performed with the first mask layer as an etching mask to form a shallow trench structure, followed by forming a first dielectric layer on the semiconductor substrate to fill the shallow trench structure. The first dielectric layer is then patterned to form a second mask layer which is used in a second etching process to form a deep trench structure. After that, a dielectric material is applied to fill the deep trench structure.

Abstract: A composite hard mask is disclosed that prevents build up of metal etch residue in a MRAM device during etch processes that define an MTJ shape. As a result, MTJ shape integrity is substantially improved. The hard mask has a lower non-magnetic spacer, a middle conductive layer, and an upper sacrificial dielectric layer. The non-magnetic spacer serves as an etch stop during a pattern transfer with fluorocarbon plasma through the conductive layer. A photoresist pattern is transferred through the dielectric layer with a first fluorocarbon etch. Then the photoresist is removed and a second fluorocarbon etch transfers the pattern through the conductive layer. The dielectric layer protects the top surface of the conductive layer during the second fluorocarbon etch and during a substantial portion of a third RIE step with a gas comprised of C, H, and O that transfers the pattern through the underlying MTJ layers.

Abstract: The invention provides a polishing liquid for polishing a barrier layer of a semiconductor integrated circuit, the polishing liquid comprising: a diquaternary ammonium cation; a corrosion inhibiting agent; and a colloidal silica, wherein the pH of the polishing liquid is in the range of 2.5 to 5.0. According to the invention, a polishing liquid capable of achieving a superior barrier layer polishing rate, as well as suppressing the occurrence of scratching due to the agglomeration of solid abrasive grains can be provided.

Abstract: There is provided a substrate processing method capable of etching a layer containing, at least, platinum without using a halogen gas. When etching the platinum-manganese layer on a wafer W by using a tantalum (Ta) layer 38 having a certain pattern shape, a processing gas containing, at least, a carbon monoxide gas, a hydrogen gas, and a rare gas is used, and a ratio of a gas flow rate of the hydrogen gas to a total gas flow rate of the carbon monoxide gas and the hydrogen gas is in a range of from about 50% to about 75%.

Abstract: According to one embodiment, a method is disclosed for chemical planarization. The method can include forming a surface layer on a to-be-processed film having irregularity. The surface layer binds to or adsorbs onto the to-be-processed film along the irregularity to suppress dissolution of the to-be-processed film. The method can include planarizing the to-be-processed film in a processing solution dissolving the to-be-processed film, by rotating the to-be-processed film and a processing body while the to-be-processed film contacting the processing body via the surface layer, removing the surface layer on convex portions of the irregularity while leaving the surface layer on concave portions of the irregularity and making dissolution degree of the convex portions larger than dissolution degree of the concave portions.

Abstract: A composition and associated method for chemical mechanical planarization of a metal-containing substrate (e.g., a copper substrate) are described herein which afford high and tunable rates of metal removal as well as low dishing and erosion levels during CMP processing.

Abstract: A method for producing a semiconductor wafer sliced from a single crystal includes rounding an edge using a grinding disk containing abrasives with an average grain size of 20.0-60.0 ?m. A first simultaneous double-side material-removing process is performed wherein the semiconductor wafers are processed between two rotating ring-shaped working disks, each working disk having a working layer containing abrasives having an average grain size of 5.0-20.0 ?m, wherein the semiconductor wafer is placed in a cutout in one of a plurality of carriers rotatable by a rolling apparatus such that the semiconductor wafer lies in a freely movable manner in the carrier and the wafer is movable on a cycloidal trajectory. A second simultaneous double-side material-removing process is performed including processing the semiconductor wafers between two rotating ring-shaped working disks, each working disk having a working layer containing abrasives having an average grain size of 0.5-15.0 ?m.

Abstract: (A) solid polymer particles being finely dispersed in the aqueous phase and containing pendant functional groups (a1) capable of strongly interacting and forming strong complexes with the metal of the surfaces to be polished, and pendant functional groups (a2) capable of interacting less strongly with the metal of the surfaces to be polished than the functional groups (a1); and (B) an organic non-polymeric compound dissolved in the aqueous phase and capable of interacting and forming strong, water-soluble complexes with the metal of the surfaces to be polished and causing an increase of the material removal rate MRR and the static etch rate SER of the metal surfaces to be polished with increasing concentration of the compound (B); a CMP process comprising selecting (A) and (B) and the use of the CMP agent and process for polishing wafers with ICs.

Abstract: A method of manufacturing an electronic device that comprises a microelectromechanical (MEMS) element, the method comprising the steps of: providing a material layer (34) on a first side of a substrate (32); providing a trench (40) in the material later (34); etching material from the trench (40) such as to also etch the substrate (32) from the first side of the substrate (32); grinding the substrate (32) from a second side of the substrate to expose the trench (40); and using the exposed trench (40) as an etch hole. The exposed trench (40) is used as an etch hole for releasing a portion of the material layer (34), for example a beam resonator (12), from the substrate (32). An input electrode (6), an output electrode (8), and a top electrode (10) are provided.

Abstract: According to the insulated gate transistor, a gate electrode (11A) is provided on a main surface of a glass substrate (2); a first part of an insulating layer (gate insulating layer (30) and transparent inorganic insulating layer (60)) is thicker than a second part of the insulating layer (gate insulating layer (30)), the first part being between (i) the gate electrode (11A) and (ii) a source electrode (12) and a drain electrode (21) of the insulated gate transistor, and the second part being between (i) the gate electrode (11A) and (ii) a channel section (31A) of the insulated gate transistor. This makes it possible to reduce parasitic capacitor without deteriorating characteristics of the transistor.

Abstract: The method for producing a silicon epitaxial wafer according to the present invention has: a growth step F at which an epitaxial layer is grown on a silicon single crystal substrate; a first polishing step D at which, before the growth step, at least a front surface of the silicon single crystal substrate is polished without using abrasive grains; and a second polishing step G at which at least the front surface of the silicon single crystal substrate is subjected to finish polishing after the growth step.

Abstract: The present invention relates to a plasma etching method with which a wide-gap semiconductor substrate can be etched with high accuracy. An inert gas is supplied into a processing chamber and plasma is generated from the inert gas, a bias potential is applied to a platen on which a wide-gap semiconductor substrate is placed, thereby making ions generated by the generation of plasma from the inert gas incident on the semiconductor substrate on the platen to thereby heat the semiconductor substrate. After the temperature of the semiconductor substrate reaches an etching temperature between 200° C. and 400° C., an etching gas is supplied into the processing chamber and plasma is generated from the etching gas and a bias potential is applied to the platen, thereby etching the semiconductor substrate while maintaining the temperature of the semiconductor substrate at the etching temperature.

Abstract: The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.

Abstract: Provided is a method of producing a liquid ejection head substrate, the method including, in sequence; grinding a second surface of a silicon substrate, which is an opposite surface of a first surface on which a function element is formed, polishing the ground second surface, etching the polished second surface by reactive ion etching using ion incident energy, forming an etching mask on the second surface after the reactive ion etching, and forming a liquid supply port by subjecting the silicon substrate to wet etching using the etching mask.

Abstract: Described is a method for improving the flatness of a layer deposited on a doped polycrystalline layer, which includes reducing the grain size of the polycrystalline layer to decrease the out-diffusion amount of the dopant from the polycrystalline layer, and/or reducing the amount of the out-diffusing dopant on the surface of the polycrystalline layer.

Abstract: Disclosed is an adjuvant for use in simultaneous polishing of a cationically charged material and an anionically charged material, wherein the adjuvant comprises a polyelectrolyte salt containing: (a) a mixture of a linear polyelectrolyte having a weight average molecular weight of 2,000˜50,000 with a graft type polyelectrolyte that has a weight average molecular weight of 1,000˜20,000 and comprises a backbone and a side chain; and (b) a basic material. CMP (chemical mechanical polishing) slurry comprising the above adjuvant and abrasive particles is also disclosed. The adjuvant comprising a mixture of a linear polyelectrolyte with a graft type polyelectrolyte makes it possible to increase polishing selectivity as compared to CMP slurry using the linear polyelectrolyte alone, and to obtain a desired range of polishing selectivity by controlling the ratio of the linear polyelectrolyte to the graft type polyelectrolyte.

Abstract: Semiconductor material substrates are polished by a method including at least one polishing step A by means of which the substrate is polished on a polishing pad containing an abrasive material bonded in the polishing pad and a polishing agent solution is introduced between the substrate and the polishing pad during the polishing step; and at least one polishing step B by means of which the substrate is polished on a polishing pad containing an abrasive material-containing polishing pad and wherein a polishing agent slurry containing unbonded abrasive material is introduced between the substrate and the polishing pad during the polishing step.

Abstract: A polishing composition of the present invention at least comprises about 750 ppm to less than 5000 ppm by weight of abrasive particles, hydrogen peroxide, an accelerator, a dual-corrosion inhibitor and water, wherein the dual-corrosion inhibitor contains a first and a second corrosion inhibitor. The dual-corrosion inhibitor is applied to the planarization of metal layers so as to maintain a high removal rate of metal layers as well as suppress etching of the metal, thus capable of reducing polishing defects such as dishing, erosion and the like.

Abstract: Embodiments of mechanisms for flattening a packaged structure are provided. The mechanisms involve a flattening apparatus and the utilization of protection layer(s) between the packaged structure and the surface(s) of the flattening apparatus. The protection layer(s) is made of a soft and non-sticking material to allow protecting exposed fragile elements of the packaged structure and easy separation after processing. The embodiments of flattening process involve flattening the warped packaged structure by pressure under elevated processing temperature. Processing under elevated temperature allows the package structure to be flattened within a reasonable processing time.

Abstract: A method for manufacturing a silicon carbide substrate includes the steps of: preparing an ingot made of silicon carbide; obtaining a silicon carbide substrate by cutting the ingot prepared; etching a silicon surface of the silicon carbide substrate; and polishing the etching surface of the silicon carbide substrate after etching the silicon carbide substrate. The step of etching a silicon surface of the silicon carbide substrate includes the step of removing silicon atoms, which form the silicon carbide, from an etching region using chlorine gas, the etching region including the etching main surface of the silicon carbide substrate.

Abstract: A method includes forming a cavity in a substrate, depositing a layer of conductive material in the cavity and over exposed portions of the substrate, removing portions of the conductive material to expose portions of the substrate using a planarizing process, and removing residual portions of the conductive material disposed on the substrate using a reactive ion etch (RIE) process.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. Self-aligned assist pattern (SAP) is derived from original design layout in an automated manner using geometric Boolean operations based on some predefined design rules, and are included in the mask layout for efficient self-alignment of various sub-layouts of the target pattern during a multiple patterning lithography process. SAP can be of any shape and size, and can have continuous features (e.g., a ring), or discontinuous (e.g., bars not connected to each other) features. An end-to-end multiple patterning lithography using spacer and SAP may use positive tone lithography, and/or negative tone lithography for line and/or space printing.

Abstract: A polishing liquid composition includes composite oxide particles containing cerium and zirconium, a dispersing agent, and an aqueous medium. A powder X-ray diffraction spectrum of the composite oxide particles obtained by CuK?1 ray (?=0.154050 nm) irradiation includes a peak (first peak) having a peak top in a diffraction angle 2? (? is a Bragg angle) range of 28.61 to 29.67°, a peak (second peak) having a peak top in a diffraction angle 2? range of 33.14 to 34.53°, a peak (third peak) having a peak top in a diffraction angle 2? range of 47.57 to 49.63°, and a peak (fourth peak) having a peak top in a diffraction angle 2? range of 56.45 to 58.91°. A half-width of the first peak is 0.8° or less.

Abstract: One illustrative method disclosed herein includes performing at least one etching process on a semiconducting substrate to form a plurality of trenches and a plurality of fins for the FinFET device in the substrate, forming a first layer of insulating material in the trenches, wherein an upper surface of the first layer of insulating material is below an upper surface of the substrate, forming an isolation layer within the trenches above the first layer of insulating material, wherein the isolation layer has an upper surface that is below the upper surface of the substrate, forming a second layer of insulating material above the isolation layer, wherein the second layer of insulating material has an upper surface that is below the upper surface of the substrate, and forming a gate electrode structure above the second layer of insulating material.

Abstract: The generation of surface patterns or the replication of surface patterns is achieved in the present disclosure without the need to employ an etching process. Instead, a unique fracture mode referred to as spalling is used in the present disclosure to generate or replicate surface patterns. In the case of surface pattern generation, a surface pattern is provided in a stressor layer and then spalling is performed. In the case of surface pattern replication, a surface pattern is formed within or on a surface of a base substrate, and then a stressor layer is applied. After applying the stressor layer, spalling is performed. Generation or replication of surface patterns utilizing spalling provides a low cost means for generation or replication of surface patterns.

Abstract: A polishing method that carries out a multi-step polishing process with improved polishing conditions (polishing recipe) while omitting measurement of the surface conditions of a substrate, as carried out between polishing steps thereby increasing the throughput.

Abstract: The problem addressed by the present invention is providing a technique for fabricating, by a method simpler than conventional methods, a silicon substrate that is effective for light trapping, one surface of which has a textured structure and the other surface of which has higher reflectivity than the surface having the textured structure. The fabrication method for this semiconductor substrate comprises: a sandblasting step in which a first surface of a silicon substrate in an as-sliced state, fabricated by slicing a silicon ingot, is surface treated by sandblasting and, after the sandblasting step, a step for carrying out surface treatment using an etching solution that contains either or both of hydrofluoric acid and nitric acid on the silicon substrate.

Abstract: Embodiments described herein relate to removing material from a substrate. More particularly, the embodiments described herein relate to polishing or planarizing a substrate by a chemical mechanical polishing process. In one embodiment, a method of chemical mechanical polishing (CMP) of a substrate is provided. The method comprises exposing a substrate having a conductive material layer formed thereon to a polishing solution comprising phosphoric acid, one or more chelating agents, one or more corrosion inhibitors, and one or more oxidizers, forming a passivation layer on the conductive material layer, providing relative motion between the substrate and a polishing pad and removing at least a portion of the passivation layer to expose a portion of the underlying conductive material layer, and removing a portion of the exposed conductive material layer.

Abstract: The present invention provided is the temporary adhesive for wafer processing which temporarily bonds a wafer having a circuit face on the front surface and a processing face on the back surface to a support, and includes a first temporary adhesive layer which is a layer (A) of a thermoplastic resin modified organopolysiloxane obtained by partial dehydration condensation of an organopolysiloxane resin containing a R21R22R23SiO1/2, and a SiO4/2 unit in a molar ratio of R21R22R23SiO1/2 unit/SiO4/2 unit of 0.6 to 1.7 and an organopolysiloxane represented by the following general formula (1), and a second temporary adhesive layer which is a thermosetting modified siloxane polymer layer (B) which is laminated on the first temporary adhesive layer and is releasably bonded to the support.

Abstract: A method for chemical mechanical polishing of a semiconductor wafer containing a nonferrous metal is provided, comprising: providing a chemical mechanical polishing composition comprising 1 to 25 wt % of an oxidizer; 0.01 to 15 wt % of an inhibitor for the nonferrous metal; 0.005 to 5 wt % of a copolymer of poly(ethylene glycol) methyl ether(meth)acrylate and 1-vinylimidazole; and water; wherein the chemical mechanical polishing composition has an acidic pH; providing a chemical mechanical polishing pad; providing a semiconductor wafer containing the nonferrous metal; creating dynamic contact between the chemical mechanical polishing pad and the semiconductor wafer; and, dispensing the polishing solution at or near the interface between the chemical mechanical polishing pad and the semiconductor wafer.

Abstract: A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.

Abstract: Semiconductor wafers are CMP polished by polishing the rear side of the semiconductor wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is higher at the center than at the edge of the rear side; and polishing the front side of the wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is lower in the center of the front side than in an edge region of the front side.