Coating Of Sidewall Patents (Class 438/696)
  • Patent number: 8568598
    Abstract: A manufacturing method of a tip type probe includes the steps of: forming on a substrate an etching mask of a shape similar to a shape of a top surface of a truncated pyramid; forming the truncated pyramid by subjecting the substrate to isotropic etching using the etching mask as a mask member; stopping the isotropic etching when an area of the top surface reaches an area capable of generating near-field light; and forming a metal film on at least some of the side surfaces of the truncated pyramid by allowing film forming particles to enter into a space between the etching mask and the side surfaces and adhere onto the truncated pyramid. The directivity of the film forming particles is controlled so that the metal film has a thickness that is reduced gradually from a bottom of the truncated pyramid toward the top surface.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: October 29, 2013
    Assignee: Seiko Instruments Inc.
    Inventors: Majung Park, Manabu Oumi
  • Publication number: 20130277723
    Abstract: Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000° C., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. Silicon dioxide is formed along multiple crystallographic planes along an interior of the trench utilizing a first treatment temperature of no greater than about 1000° C., and an interface between the silicon dioxide and the monocrystalline silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. A transistor gate is formed within the trench, and a pair of source/drain regions is formed within the monocrystalline silicon adjacent the transistor gate. Some embodiments include DRAM cells.
    Type: Application
    Filed: April 19, 2012
    Publication date: October 24, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shivani Srivastava, Kunal Shrotri, Fawad Ahmed
  • Patent number: 8557706
    Abstract: A substrate processing method that forms an opening, which has a size that fills the need for downsizing a semiconductor device and is to be transferred to an amorphous carbon film, in a photoresist film of a substrate to be processed. Deposit is accumulated on a side wall surface of the opening in the photoresist film using plasma produced from a deposition gas having a gas attachment coefficient S of 0.1 to 1.0 so as to reduce the opening width of the opening.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: October 15, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Masanobu Honda, Hironobu Ichikawa
  • Patent number: 8557662
    Abstract: A method for fabricating a semiconductor device is provided, the method includes forming a double trench including a first trench and a second trench formed below the first trench and having surfaces covered with insulation layers, and removing portions of the insulation layers to form a side contact exposing one sidewall of the second trench.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: October 15, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Oh Lee
  • Patent number: 8557128
    Abstract: Methods for fabricating sub-lithographic, nanoscale microchannels utilizing an aqueous emulsion of an amphiphilic agent and a water-soluble, hydrogel-forming polymer, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: October 15, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Publication number: 20130260561
    Abstract: Techniques disclosed herein include systems and methods for an aspect ratio dependent deposition process that improves gate spacer profile, reduces fin loss, and also reduces hardmask loss in a FinFET or other transistor scheme. Techniques include depositing an aspect ratio dependent protective layer to help tune profile of a structure during fabrication. Plasma and process gas parameters are tuned such that more polymer can collect on surfaces of a structure that are visible to the plasma. For example, upper portions of structures can collect more polymer as compared to lower portions of structures. The variable thickness of the protection layer enables selective portions of spacer material to be removed while other portions are protected.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 3, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Alok Ranjan, Angelique Denise Raley
  • Patent number: 8546265
    Abstract: A method for manufacturing a silicon structure according to the present invention includes, in a so-called dry-etching process wherein gas-switching is employed, the steps of: etching a portion in the silicon region at a highest etching rate under a high-rate etching condition such that the portion does not reach the etch stop layer; subsequently etching under a transition etching condition in which an etching rate is decreased with time from the highest etching rate in the high-rate etching condition; and thereafter, etching the silicon region under a low-rate etching condition of a lowest etching rate in the transition etching condition.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: October 1, 2013
    Assignee: SPP Technologies Co., Ltd.
    Inventors: Yoshiyuki Nozawa, Takashi Yamamoto
  • Patent number: 8546218
    Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a plurality of bodies isolated by a first trench, forming a buried bit line gap-filling a portion of the first trench, etching the top portions of the bodies to form a plurality of pillars isolated by a plurality of second trenches extending across the first trench, forming a passivation layer gap-filling a portion of the second trenches, forming an isolation layer that divides each of the second trenches into isolation trenches over the passivation layer, and filling a portion of the isolation trenches to form a buried word line extending in a direction crossing over the buried bit line.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: October 1, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Uk Kim, Kyung-Bo Ko
  • Patent number: 8546258
    Abstract: Metal contacts are formed within a string overhead area using a double patterning technology (DPT) process thereby allowing for the reduction of a string overhead area and a concomitant reduction in the chip size of a semiconductor device. A first mask pattern is formed by etching a first mask layer, the first mask pattern including a first opening formed in a cell region and a first hole formed in a peripheral region. A first sacrificial pattern is formed on the first mask pattern and the exposed first insulating layer of the cell region using a double patterning technology process. Contact holes are formed by exposing the target layer by etching the first insulating layer using the first mask pattern and the first sacrificial pattern as an etch mask. Metal contacts are then formed in the contact holes.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-cheol Kim, Dae-youp Lee
  • Publication number: 20130252429
    Abstract: A photo mask for exposing according to an embodiment includes a mark pattern arranged in a mark region that is different from an effective region to form a semiconductor device; and a regular pattern arranged in the mark region and around the mark pattern and smaller than the mark pattern in size and pitch.
    Type: Application
    Filed: August 8, 2012
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yosuke OKAMOTO, Kazutaka ISHIGO, Taketo KURIYAMA
  • Publication number: 20130249062
    Abstract: A method of forming an embedded film comprises depositing a first layer on a second layer that is disposed on a substrate and includes a material different from materials included in the first layer, forming an aperture through the first layer and into the second layer, the aperture having a side surface that includes an exposed portion of the first layer and an exposed portion of the second layer, bringing a material that includes organic molecules into contact with the exposed portion of the first layer and the exposed portion of the second layer to form a monomolecular film that covers the side surface, and forming the embedded film in the aperture with a material having a high enough affinity to the monomolecular film to substantially fill the aperture.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasuhito YOSHIMIZU, Hisashi OKUCHI, Hiroshi TOMITA
  • Publication number: 20130252430
    Abstract: A method for performing a spacer etch process is described. The method includes providing a gate structure on a substrate having a low-k spacer material conformally applied over the gate structure, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a spacer protection layer on an exposed surface of said spacer material, and performing one or more etching processes to selectively and anisotropically remove the spacer protection layer and the spacer material to leave behind the sidewall spacer on the sidewall of the gate structure, wherein, while being partly or fully consumed by the one or more etching processes, the spacer protection layer exhibits a reduced variation in composition and/or dielectric constant.
    Type: Application
    Filed: August 18, 2012
    Publication date: September 26, 2013
    Applicant: Tokyo Electron Limited
    Inventors: Alok Ranjan, Angelique D. Raley
  • Publication number: 20130244392
    Abstract: Provided are methods of forming field effect transistors. The method includes preparing a substrate with a first region and a second region, forming fin portions on the first and second regions, each of the fin portions protruding from the substrate and having a first width, forming a first mask pattern to expose the fin portions on the first region and cover the fin portions on the second region, and changing widths of the fin portions provided on the first region.
    Type: Application
    Filed: February 28, 2013
    Publication date: September 19, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chang Woo OH, Shincheol Min, Jongwook Lee, Choongho Lee
  • Publication number: 20130237059
    Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a SiOCl-containing layer on an exposed surface of the spacer material to form a spacer protection layer.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 12, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Alok RANJAN, Kaushik Arun KUMAR
  • Patent number: 8530264
    Abstract: Methods of fabricating complementary metal-oxide-semiconductor (CMOS) imagers for backside illumination are disclosed. In one embodiment, the method may include forming at a front side of a substrate a plurality of high aspect ratio trenches having a predetermined trench depth, and forming at the front side of the substrate a plurality of photodiodes, where each photodiode is adjacent at least one trench. The method may further include forming an oxide layer on inner walls of each trench, removing the oxide layer, filling each trench with a highly doped material, and thinning the substrate from a back side opposite the front side to a predetermined final substrate thickness. In some embodiments, the substrate may have a predetermined doping profile, such as a graded doping profile, that provides a built-in electric field suitable to guide the flow of photogenerated minority carriers towards the front side.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: September 10, 2013
    Assignee: IMEC
    Inventors: Koen De Munck, Kiki Minoglou, Joeri De Vos
  • Patent number: 8525168
    Abstract: A test probe head for probing integrated circuit (IC) chips and method of making test heads. The test head includes an array of vias (e.g., annular vias or grouped rectangular vias) through, and exiting one surface of, a semiconductor layer, e.g., a silicon layer. The vias, individual test probe tips, may be on a pitch at or less than fifty microns (50 ?m). The probe tips may be stiffened with SiO2 (and optionally silicon) extending along the sidewalls. A redistribution layer connects individual test probe tips externally. The probe tips may be capped with a hardening cap that also caps stiffening SiO2 and silicon along the tip sidewall.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: September 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, John U. Knickerbocker, Yang Liu
  • Patent number: 8524604
    Abstract: A method for forming fine pattern includes sequentially forming a first thin film and a second thin film over a target layer for patterning, forming a partition over the second thin film, removing the partition after forming spacers on sidewalls of the partition, forming first pattern of the second thin film by etching the second thin film of a first region and the second thin film of a second region while exposing the spacers, forming second pattern of the second thin film by using the spacers as masks and etching the first pattern of the second thin film in the first region, forming first thin film pattern by using the first and second patterns of the second thin film as masks in the first and second regions and etching the first thin film, and etching the pattern target layer.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: September 3, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young-Kyun Jung
  • Patent number: 8524605
    Abstract: Self-aligned sextuple patterning (SASP) processes and mask design methods for the semiconductor manufacturing are invented. The inventions pertain to methods of forming one and/or two dimensional features on a substrate having the feature density increased to six times of what is possible using the standard optical lithographic technique; and methods to release the overlay requirement when patterning the critical layers of semiconductor devices. Our inventions provide production-worthy methods for the semiconductor industry to continue device scaling beyond 15 nm (half pitch).
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: September 3, 2013
    Assignee: Vigma Nanoelectronics
    Inventor: Yijian Chen
  • Patent number: 8518828
    Abstract: According to a disclosed semiconductor device fabrication method according to one embodiment of the present invention, a layer having a line-and-space pattern extending in one direction is etched using another layer having a line-and-space pattern extending in another direction intersecting the one direction, thereby obtaining a mask having two-dimensionally arranged dots. An underlying layer is etched using the mask, thereby providing two-dimensionally arranged pillars.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: August 27, 2013
    Assignees: Tokyo Electron Limited, Tohoku University
    Inventors: Tetsuo Endoh, Eiichi Nishimura
  • Patent number: 8513132
    Abstract: A method for fabricating a metal pattern in a semiconductor device includes forming a metal layer over a substrate, forming a hard mask layer over the metal layer, forming a sacrifice pattern over the hard mask layer, forming a spacer pattern on sidewalks of the sacrifice pattern, removing the sacrifice pattern, forming a hard mask pattern by etching the hard mask layer using the spacer pattern as an etch barrier, forming an etching protection layer over the hard mask pattern and on sidewalks of the hard mask pattern, and forming the metal pattern by performing primary and secondary etching processes on the metal layer using the etching protection layer as an etch barrier.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: August 20, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Mi-Na Ku
  • Patent number: 8513131
    Abstract: A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ming Cai, Dechao Guo, Chung-hsun Lin, Chun-chen Yeh
  • Patent number: 8513125
    Abstract: A method for manufacturing a device comprising a structure with nanowires based on a semiconducting material such as Si and another structure with nanowires based on another semiconducting material such as SiGe, and is notably applied to the manufacturing of transistors.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: August 20, 2013
    Assignee: Commissariat a l'energie atomique et aux alternatives
    Inventors: Emeline Saracco, Jean-Francois Damlencourt, Michel Heitzmann
  • Patent number: 8507384
    Abstract: Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and curved outer sidewalls. An augmentation material is formed on the plurality of spacers such that the inner or the outer sidewalls of the spacers are selectively expanded. The augmentation material can bridge the upper portions of pairs of neighboring inner sidewalls to limit deposition between the inner sidewalls. The augmentation material is selectively etched to form a pattern of augmented spacers having a desired augmentation of the inner or outer sidewalls. The pattern of augmented spacers can then be transferred to the substrate through a series of selective etches such that features formed in the substrate achieve a desired pitch.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: August 13, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Hongbin Zhu
  • Patent number: 8501626
    Abstract: Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: August 6, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Wei Liu, Eiichi Matsusue, Meihua Shen, Shashank Deshmukh, Anh-Kiet Quang Phan, David Palagashvili, Michael D. Willwerth, Jong I. Shin, Barrett Finch, Yohei Kawase
  • Patent number: 8501611
    Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: August 6, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Do Ryu, Si-Young Choi, Yu-Gyun Shin, Tai-Su Park, Dong-Chan Kim, Jong-Ryeol Yoo, Seong-Hoon Jeong, Jong-Hoon Kang
  • Patent number: 8501607
    Abstract: A method is provided for forming FinFETS with improved alignment features. Embodiments include forming on a Si substrate pillars of TEOS on poly-Si; conformally depositing a first TEOS liner over the entire substrate; etching the first TEOS liner and substrate through the pillars, forming first trenches; filling the first trenches and spaces between the pillars with an oxide; removing the TEOS from the pillars and the oxide therebetween; removing the poly-Si; conformally depositing a second TEOS liner over the entire Si substrate; etching the second TEOS liner and Si between the oxide, forming second trenches having a larger depth than the first trenches; filling the second trenches with oxide; removing the oxide and the first and second TEOS liners down to an upper surface of the Si substrate; and recessing the oxide below the upper surface of the Si substrate.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: August 6, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Werner Juengling
  • Publication number: 20130196508
    Abstract: In one example, the method includes forming a hard mask layer above a semiconducting substrate, forming a patterned spacer mask layer above the hard mask layer, wherein the patterned spacer mask layer is comprised of a plurality of first spacers, second spacers and third spacers, and performing a first etching process on the hard mask layer through the patterned spacer mask layer to define a patterned hard mask layer. The method also includes performing a second etching process through the patterned hard mask layer to define a plurality of first fins, second fins and third fins in the substrate, wherein the first fins have a width that corresponds approximately to a width of the first spacers, the second fins have a width that corresponds approximately to a width of the second spacers, and the third fins have a width that corresponds approximately to a width of the third spacers.
    Type: Application
    Filed: January 26, 2012
    Publication date: August 1, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: Nicholas V. LiCausi
  • Publication number: 20130189845
    Abstract: A method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber is provided. The method generally includes depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a nitrogen-doped amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the nitrogen-doped amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the nitrogen-doped amorphous carbon layer, and removing the patterned features from the substrate.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 25, 2013
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Sungjin Kim, Deenesh Padhi, Song Hyun Hong, Bok Hoen Kim, Derek R. Witty
  • Patent number: 8492227
    Abstract: An etching stopper film is formed over a first insulating film. Then, a second insulating film is formed with a thickness that allows concave and convex portions formed due to a first gate electrode to remain. Then, anisotropic etching is performed using the etching stopper film as a stopper to remove the second insulating film over a second gate electrode and form a first side wall spacer of the first gate electrode. Then, the etching stopper film is removed. Then, anisotropic etching is performed on the first insulating film to form a second side wall spacer over the second gate electrode and form a third side wall spacer which is disposed inside the first side wall spacer over the first gate electrode.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: July 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Akira Mitsuiki, Atsuro Inada
  • Patent number: 8492282
    Abstract: In some embodiments, methods for forming a masking pattern for an integrated circuit are disclosed. In one embodiment, mandrels defining a first pattern are formed in a first masking layer over a target layer. A second masking layer is deposited to at least partially fill spaces of the first pattern. Sacrificial structures are formed between the mandrels and the second masking layer. After depositing the second masking layer and forming the sacrificial structures, the sacrificial structures are removed to define gaps between the mandrels and the second masking layer, thereby defining a second pattern. The second pattern includes at least parts of the mandrels and intervening mask features alternating with the mandrels. The second pattern may be transferred into the target layer. In some embodiments, the method allows the formation of features having a high density and a small pitch while also allowing the formation of features having various shapes and sizes.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: July 23, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Anton DeVilliers
  • Patent number: 8491804
    Abstract: A method of processing a substrate having a processing target layer and an organic film serving as a mask layer includes a mineralizing process of mineralizing the organic film. The mineralizing process includes an adsorption process for allowing a silicon-containing gas to be adsorbed onto a surface of the organic film; and an oxidation process for oxidizing the adsorbed silicon-containing gas to be converted into a silicon oxide film. A monovalent aminosilane is employed as the silicon-containing gas.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: July 23, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Masato Kushibiki, Eiichi Nishimura
  • Patent number: 8486838
    Abstract: A method for forming a fine pattern using isotropic etching, includes the steps of forming an etching layer on a semiconductor substrate, and coating a photoresist layer on the etching layer, performing a lithography process with respect to the etching layer coated with the photoresist layer, and performing a first isotropic etching process with respect to the etching layer including a photoresist pattern formed through the lithography process, depositing a passivation layer on the etching layer including the photoresist pattern, and performing a second isotropic etching process with respect to the passivation layer. The second isotropic etching process is directly performed without removing the predetermined portion of the passivation layer.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: July 16, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventors: Sang-Yu Lee, Jee-Heum Paik, Soo-Hong Kim, Chang-Woo Yoo, Sung-Woon Yoon
  • Patent number: 8486752
    Abstract: A phase change memory device includes a semiconductor substrate having an impurity region and an interlayer dielectric applying a tensile stress formed on the semiconductor substrate and having contact holes exposing the impurity region. Switching elements are formed in the contact holes; and sidewall spacers interposed between the switching elements and the interlayer dielectric and formed as a dielectric layer applying a compressive stress.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: July 16, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Heon Yong Chang
  • Patent number: 8486288
    Abstract: A pattern forming method including: (a) forming a porous layer above an etching target layer; (b) forming an organic material with a transferred pattern on the porous layer; (c) forming, by use of the transferred pattern, a processed pattern in a transfer oxide film that is more resistant to etching than the porous layer; and (d) transferring the processed pattern to the etching target layer by use of the transfer oxide film as a mask.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: July 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Ohashi
  • Patent number: 8481431
    Abstract: A method for opening a one-side contact region of a vertical transistor is provided. The one-side contact region of the vertical transistor is opened using a polysilicon layer, a certain portion of which can be selectively removed by a selective ion implantation process. In order to selectively remove the polysilicon layer formed on one of both sides of an active region, at which the one-side contact is to be formed, impurity ion implantation is performed in a direction vertical to the polysilicon layer by a plasma doping process, and a tilt ion implantation using an existing ion implantation process is performed. In this manner, the polysilicon layer is selectively doped, and the undoped portion of the polysilicon layer is selectively removed.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: July 9, 2013
    Assignee: SK Hynix Inc.
    Inventors: Kyong Bong Rouh, Yong Seok Eun, Eun Shil Park
  • Publication number: 20130164940
    Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Angélique Denise RALEY, Takuya MORI, Hiroto OHTAKE
  • Publication number: 20130161841
    Abstract: An alignment mark includes a plurality of mark units. Each mark unit includes a first element and a plurality of second elements. Each second element includes opposite first and second end portions. The plurality of second elements are arranged along a direction. The first element extends adjacent to the first end portions of the plurality of second elements and parallel to the direction of the plurality of second elements.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 27, 2013
    Applicant: Nan Ya Technology Corporation
    Inventors: Chen Ku CHIANG, Yuan Hsun Wu
  • Publication number: 20130157462
    Abstract: The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")
    Inventors: Chia Ying Lee, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai, Syun-Ming Jang
  • Patent number: 8466066
    Abstract: A method for forming a micro-pattern in a semiconductor device includes forming a hard mask layer and a sacrificial layer over an etch target layer, forming a plurality of openings having a hole shape in the sacrificial layer, forming spacers over inner sidewalls of the openings to form first hole patterns inside the openings, etching the sacrificial layer outside of the sidewalls of the openings using the spacers in a manner that the sacrificial layer in a first area remains partially and the sacrificial layer in a second area is removed to form second hole patterns, wherein the first area is smaller than the second area, and etching the hard mask layer using the remaining sacrificial layer and the spacers including the first and second hole patterns.
    Type: Grant
    Filed: June 27, 2009
    Date of Patent: June 18, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Won-Kyu Kim
  • Patent number: 8461048
    Abstract: A fabrication method of a minute pattern at least includes following steps. A first crystallizable material layer is formed on a base material. The first crystallizable material layer is patterned to form a plurality of first patterns on the base material. A distance between every two adjacent first patterns is greater than a width of each of the first patterns. A first treatment process is performed to crystallize the first patterns. A second crystallizable material layer is formed on the base material and covers the first patterns. The second crystallizable material layer is patterned to form a plurality of second patterns on the base material. Each of the second patterns is located between the first patterns adjacent thereto, respectively.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: June 11, 2013
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventor: Hsi-Ming Chang
  • Patent number: 8461049
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a first cap layer on a surface of the substrate and sidewall of the gate structure; forming a second cap layer on the first cap layer; forming a third cap layer on the second cap layer; performing an etching process to partially remove the third cap layer, the second cap layer, and the first cap layer to form a first spacer and a second spacer on the sidewall of the gate structure; and forming a contact etch stop layer (CESL) on the substrate to cover the second spacer, wherein the third cap layer and the CESL comprise same deposition condition.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: June 11, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chu-Chun Chang, Chun-Mao Chiou, Chiu-Te Lee
  • Publication number: 20130143409
    Abstract: Methods for forming semiconductor structures using selectively-formed sidewall spacers are provided. One method comprises forming a first structure and a second structure. The second structure has a height that is greater than the first structure's height. A first sidewall spacer-forming material is deposited overlying the first structure and the second structure. A second sidewall spacer-forming material is deposited overlying the first sidewall spacer-forming material. A composite spacer is formed about the second structure, the composite spacer comprising the first sidewall spacer-forming material and the second sidewall spacer-forming material. The second sidewall spacer-forming material is removed from the first structure and the first sidewall spacer-forming material is removed from the first structure.
    Type: Application
    Filed: January 31, 2013
    Publication date: June 6, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: Frank Scott JOHNSON
  • Patent number: 8455364
    Abstract: In one non-limiting exemplary embodiment, a method includes: providing a structure having at least one lithographic layer on a substrate, where the at least one lithographic layer includes a planarization layer (PL); forming a sacrificial mandrel by patterning at least a portion of the at least one lithographic layer using a photolithographic process, where the sacrificial mandrel includes at least a portion of the PL; and producing at least one microstructure by using the sacrificial mandrel in a sidewall image transfer process.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventor: Sivananda K. Kanakasabapathy
  • Patent number: 8455268
    Abstract: Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: June 4, 2013
    Assignee: Spansion LLC
    Inventors: Chungho Lee, Hiroyuki Kinoshita, Kuo-Tung Chang, Rinji Sugino, Chi Chang, Huaqiang Wu
  • Patent number: 8450212
    Abstract: A method including forming an organic polymer layer (OPL) on a substrate; forming a patterned photoresist layer having a first opening and a second opening over the OPL, the second opening wider than the first opening; performing a first reactive ion etch (RIE) to form a first trench and a second trench in the organic layer, the second trench wider than the first trench, the first trench extending into but not through the organic polymer layer, the second trench extending through the OPL to the substrate, the first RIE forming a first polymer layer on sidewalls of the first trench and a second polymer layer on sidewalls of the second trench, the second polymer layer thicker than the first polymer layer; and performing a second RIE to extend the first trench through the OPL to the substrate, the second RIE removing the second polymer layer from sidewalls of the second trench.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Matthew S. Angyal, Oluwafemi O. Ogunsola, Hakeem B. Akinmade-Yusuff
  • Patent number: 8450175
    Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: May 28, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
  • Publication number: 20130126959
    Abstract: According to one embodiment, there are provided a first shaped pattern in which a plurality of first holes are arranged and of which a width is periodically changed along an arrangement direction of the first holes, a second shaped pattern in which a plurality of second holes are arranged and of which a width is periodically changed along an arrangement direction of the second holes, and slits which are formed along the arrangement direction of the first holes and separate the first shaped pattern and the second shaped pattern.
    Type: Application
    Filed: September 13, 2012
    Publication date: May 23, 2013
    Inventors: Ryota Aburada, Takashi Obara, Toshiya Kotani
  • Patent number: 8445381
    Abstract: A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: May 21, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Sundar Narayanan
  • Patent number: 8435900
    Abstract: The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 7, 2013
    Assignee: Semiconductor Manufacturing International Corp.
    Inventors: Qun Shao, Zhongshan Hong
  • Patent number: 8431492
    Abstract: In a first embodiment, a method of forming a memory cell is provided that includes (a) forming one or more layers of steering element material above a substrate; (b) etching a portion of the steering element material to form a pillar of steering element material having an exposed sidewall; (c) forming a sidewall collar along the exposed sidewall of the pillar; and (d) forming a memory cell using the pillar. Numerous other aspects are provided.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: April 30, 2013
    Assignee: SanDisk 3D LLC
    Inventor: S. Brad Herner