Abstract: Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and curved outer sidewalls. An augmentation material is formed on the plurality of spacers such that the inner or the outer sidewalls of the spacers are selectively expanded. The augmentation material can bridge the upper portions of pairs of neighboring inner sidewalls to limit deposition between the inner sidewalls. The augmentation material is selectively etched to form a pattern of augmented spacers having a desired augmentation of the inner or outer sidewalls. The pattern of augmented spacers can then be transferred to the substrate through a series of selective etches such that features formed in the substrate achieve a desired pitch.

Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

Abstract: A method is provided for forming FinFETS with improved alignment features. Embodiments include forming on a Si substrate pillars of TEOS on poly-Si; conformally depositing a first TEOS liner over the entire substrate; etching the first TEOS liner and substrate through the pillars, forming first trenches; filling the first trenches and spaces between the pillars with an oxide; removing the TEOS from the pillars and the oxide therebetween; removing the poly-Si; conformally depositing a second TEOS liner over the entire Si substrate; etching the second TEOS liner and Si between the oxide, forming second trenches having a larger depth than the first trenches; filling the second trenches with oxide; removing the oxide and the first and second TEOS liners down to an upper surface of the Si substrate; and recessing the oxide below the upper surface of the Si substrate.

Abstract: Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.

Abstract: In one example, the method includes forming a hard mask layer above a semiconducting substrate, forming a patterned spacer mask layer above the hard mask layer, wherein the patterned spacer mask layer is comprised of a plurality of first spacers, second spacers and third spacers, and performing a first etching process on the hard mask layer through the patterned spacer mask layer to define a patterned hard mask layer. The method also includes performing a second etching process through the patterned hard mask layer to define a plurality of first fins, second fins and third fins in the substrate, wherein the first fins have a width that corresponds approximately to a width of the first spacers, the second fins have a width that corresponds approximately to a width of the second spacers, and the third fins have a width that corresponds approximately to a width of the third spacers.

Abstract: A method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber is provided. The method generally includes depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a nitrogen-doped amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the nitrogen-doped amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the nitrogen-doped amorphous carbon layer, and removing the patterned features from the substrate.

Abstract: An etching stopper film is formed over a first insulating film. Then, a second insulating film is formed with a thickness that allows concave and convex portions formed due to a first gate electrode to remain. Then, anisotropic etching is performed using the etching stopper film as a stopper to remove the second insulating film over a second gate electrode and form a first side wall spacer of the first gate electrode. Then, the etching stopper film is removed. Then, anisotropic etching is performed on the first insulating film to form a second side wall spacer over the second gate electrode and form a third side wall spacer which is disposed inside the first side wall spacer over the first gate electrode.

Abstract: In some embodiments, methods for forming a masking pattern for an integrated circuit are disclosed. In one embodiment, mandrels defining a first pattern are formed in a first masking layer over a target layer. A second masking layer is deposited to at least partially fill spaces of the first pattern. Sacrificial structures are formed between the mandrels and the second masking layer. After depositing the second masking layer and forming the sacrificial structures, the sacrificial structures are removed to define gaps between the mandrels and the second masking layer, thereby defining a second pattern. The second pattern includes at least parts of the mandrels and intervening mask features alternating with the mandrels. The second pattern may be transferred into the target layer. In some embodiments, the method allows the formation of features having a high density and a small pitch while also allowing the formation of features having various shapes and sizes.

Abstract: A method of processing a substrate having a processing target layer and an organic film serving as a mask layer includes a mineralizing process of mineralizing the organic film. The mineralizing process includes an adsorption process for allowing a silicon-containing gas to be adsorbed onto a surface of the organic film; and an oxidation process for oxidizing the adsorbed silicon-containing gas to be converted into a silicon oxide film. A monovalent aminosilane is employed as the silicon-containing gas.

Abstract: A method for forming a fine pattern using isotropic etching, includes the steps of forming an etching layer on a semiconductor substrate, and coating a photoresist layer on the etching layer, performing a lithography process with respect to the etching layer coated with the photoresist layer, and performing a first isotropic etching process with respect to the etching layer including a photoresist pattern formed through the lithography process, depositing a passivation layer on the etching layer including the photoresist pattern, and performing a second isotropic etching process with respect to the passivation layer. The second isotropic etching process is directly performed without removing the predetermined portion of the passivation layer.

Abstract: A phase change memory device includes a semiconductor substrate having an impurity region and an interlayer dielectric applying a tensile stress formed on the semiconductor substrate and having contact holes exposing the impurity region. Switching elements are formed in the contact holes; and sidewall spacers interposed between the switching elements and the interlayer dielectric and formed as a dielectric layer applying a compressive stress.

Abstract: A pattern forming method including: (a) forming a porous layer above an etching target layer; (b) forming an organic material with a transferred pattern on the porous layer; (c) forming, by use of the transferred pattern, a processed pattern in a transfer oxide film that is more resistant to etching than the porous layer; and (d) transferring the processed pattern to the etching target layer by use of the transfer oxide film as a mask.

Abstract: A method for opening a one-side contact region of a vertical transistor is provided. The one-side contact region of the vertical transistor is opened using a polysilicon layer, a certain portion of which can be selectively removed by a selective ion implantation process. In order to selectively remove the polysilicon layer formed on one of both sides of an active region, at which the one-side contact is to be formed, impurity ion implantation is performed in a direction vertical to the polysilicon layer by a plasma doping process, and a tilt ion implantation using an existing ion implantation process is performed. In this manner, the polysilicon layer is selectively doped, and the undoped portion of the polysilicon layer is selectively removed.

Abstract: An alignment mark includes a plurality of mark units. Each mark unit includes a first element and a plurality of second elements. Each second element includes opposite first and second end portions. The plurality of second elements are arranged along a direction. The first element extends adjacent to the first end portions of the plurality of second elements and parallel to the direction of the plurality of second elements.

Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure.

Abstract: The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.

Abstract: A method for forming a micro-pattern in a semiconductor device includes forming a hard mask layer and a sacrificial layer over an etch target layer, forming a plurality of openings having a hole shape in the sacrificial layer, forming spacers over inner sidewalls of the openings to form first hole patterns inside the openings, etching the sacrificial layer outside of the sidewalls of the openings using the spacers in a manner that the sacrificial layer in a first area remains partially and the sacrificial layer in a second area is removed to form second hole patterns, wherein the first area is smaller than the second area, and etching the hard mask layer using the remaining sacrificial layer and the spacers including the first and second hole patterns.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a first cap layer on a surface of the substrate and sidewall of the gate structure; forming a second cap layer on the first cap layer; forming a third cap layer on the second cap layer; performing an etching process to partially remove the third cap layer, the second cap layer, and the first cap layer to form a first spacer and a second spacer on the sidewall of the gate structure; and forming a contact etch stop layer (CESL) on the substrate to cover the second spacer, wherein the third cap layer and the CESL comprise same deposition condition.

Abstract: A fabrication method of a minute pattern at least includes following steps. A first crystallizable material layer is formed on a base material. The first crystallizable material layer is patterned to form a plurality of first patterns on the base material. A distance between every two adjacent first patterns is greater than a width of each of the first patterns. A first treatment process is performed to crystallize the first patterns. A second crystallizable material layer is formed on the base material and covers the first patterns. The second crystallizable material layer is patterned to form a plurality of second patterns on the base material. Each of the second patterns is located between the first patterns adjacent thereto, respectively.

Abstract: Methods for forming semiconductor structures using selectively-formed sidewall spacers are provided. One method comprises forming a first structure and a second structure. The second structure has a height that is greater than the first structure's height. A first sidewall spacer-forming material is deposited overlying the first structure and the second structure. A second sidewall spacer-forming material is deposited overlying the first sidewall spacer-forming material. A composite spacer is formed about the second structure, the composite spacer comprising the first sidewall spacer-forming material and the second sidewall spacer-forming material. The second sidewall spacer-forming material is removed from the first structure and the first sidewall spacer-forming material is removed from the first structure.

Abstract: In one non-limiting exemplary embodiment, a method includes: providing a structure having at least one lithographic layer on a substrate, where the at least one lithographic layer includes a planarization layer (PL); forming a sacrificial mandrel by patterning at least a portion of the at least one lithographic layer using a photolithographic process, where the sacrificial mandrel includes at least a portion of the PL; and producing at least one microstructure by using the sacrificial mandrel in a sidewall image transfer process.

Abstract: Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

Abstract: A method including forming an organic polymer layer (OPL) on a substrate; forming a patterned photoresist layer having a first opening and a second opening over the OPL, the second opening wider than the first opening; performing a first reactive ion etch (RIE) to form a first trench and a second trench in the organic layer, the second trench wider than the first trench, the first trench extending into but not through the organic polymer layer, the second trench extending through the OPL to the substrate, the first RIE forming a first polymer layer on sidewalls of the first trench and a second polymer layer on sidewalls of the second trench, the second polymer layer thicker than the first polymer layer; and performing a second RIE to extend the first trench through the OPL to the substrate, the second RIE removing the second polymer layer from sidewalls of the second trench.

Abstract: According to one embodiment, there are provided a first shaped pattern in which a plurality of first holes are arranged and of which a width is periodically changed along an arrangement direction of the first holes, a second shaped pattern in which a plurality of second holes are arranged and of which a width is periodically changed along an arrangement direction of the second holes, and slits which are formed along the arrangement direction of the first holes and separate the first shaped pattern and the second shaped pattern.

Abstract: A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.

Abstract: The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer.

Abstract: In a first embodiment, a method of forming a memory cell is provided that includes (a) forming one or more layers of steering element material above a substrate; (b) etching a portion of the steering element material to form a pillar of steering element material having an exposed sidewall; (c) forming a sidewall collar along the exposed sidewall of the pillar; and (d) forming a memory cell using the pillar. Numerous other aspects are provided.

Abstract: In anisotropic etching of the substrates, ultra-thin and conformable layers of materials can be used to passivate sidewalls of the etched features. Such a sidewall passivation layer may be a Self-assembled monolayer (SAM) material deposited in-situ etching process from a vapor phase. Alternatively, the sidewall passivation layer may be an inorganic-based material deposited using Atomic Layer Deposition (ALD) method. SAM or ALD s layer deposition can be carried out in a pulsing regime alternating with sputtering and/or etching processes using process gasses with or without plasma. Alternatively, SAM deposition is carried out continuously, while etch or sputtering turns on in a pulsing regime. Alternatively, SAM deposition and etch or sputtering may be carried out continuously.

Abstract: In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.

Abstract: A method of forming a semiconductor memory device includes forming an etch target layer on a substrate, forming a sacrificial layer having preliminary openings on the etch target layer, forming assistance spacers in the preliminary openings, respectively, removing the sacrificial layer, such that the assistance spacers remain on the etch target layer, forming first mask spacers covering inner sidewalls of the assistance spacers, respectively, the first mask spacers respectively defining first openings, forming a second mask spacer covering outer sidewalls of the assistance spacers, the second mask spacer defining second openings between the first openings, the first and second openings being adjacent to each other along a first direction, and etching the etch target layer exposed by the first openings and the second openings to form holes in the etch target layer.

Abstract: Embodiment of the present invention provides a method of forming a semiconductor device in a sidewall image transfer process with multiple critical dimensions. The method includes forming a multi-level dielectric layer over a plurality of mandrels, the multi-level dielectric layer having a plurality of regions covering the plurality of mandrels, the plurality of regions of the multi-level dielectric layer having different thicknesses; etching the plurality of regions of the multi-level dielectric layer into spacers by applying a directional etching process, the spacers being formed next to sidewalls of the plurality of mandrels and having different widths corresponding to the different thicknesses of the plurality of regions of the multi-level dielectric layer; removing the plurality of mandrels in-between the spacers; and transferring bottom images of the spacers into one or more layers underneath the spacers.

Abstract: Methods for fabrication of microfluidic systems on printed circuit boards (PCB) are described. The PCB contains layers of insulating material and a layer or layers of metal buried within layers of insulating material. The metal layers are etched away, leaving fully enclosed microfluidic channels buried within the layers of insulating material.

Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed.

Abstract: A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.

Abstract: A method for producing a deep trench in a substrate includes a series of elementary etch cycles each etching a portion of the trench. Each elementary cycle includes deposition of a passivation layer on the sidewalls and the bottom of the trench portion etched during previous cycles; followed by pulsed plasma anisotropic ion etching of the trench portion etched during previous cycles, the etching; being implemented in an atmosphere comprising a passivating species; and including a first etch sequence followed by a second etch sequence of less power than the power of the first etch sequence. The first etch sequence etches the passivation layer deposited in the bottom of the portion so as to access the substrate and etches the free substrate at the bottom of the portion while leaving a passivation layer on sidewalls of the portion.

Abstract: A method of fabricating a semiconductor device for improving the performance of “?” shaped embedded source/drain regions is disclosed. A “U” shaped recess is formed in a Si substrate. The recess is treated with a surfactant, the amount of surfactant adsorbed on the recess sidewalls being greater than that on the recess bottom. An oxide is formed on the bottom. The presence of surfactant on the sidewalls, prevents oxide from forming thereon. The surfactant on the sidewalls is then removed and an orientation selective wet etching process is performed on the sidewalls. The oxide protects the Si at the bottom is from being etched.

Abstract: A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. The liner is removed from a bottom surface of the at least one trench to expose the underlying silicon. A portion of the underlying exposed silicon is removed to form a cavity in the silicon. At least one removal cycle is conducted to remove exposed silicon in the cavity to form a bulb-shaped cross-sectional profile, with each removal cycle comprising subjecting the silicon in the cavity to ozonated water to oxidize the silicon and subjecting the oxidized silicon to a hydrogen fluoride solution to remove the oxidized silicon. A semiconductor device structure comprising the at least one trench comprising a cavity with a bulb-shaped cross-sectional profile is also disclosed.

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning.

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

Abstract: The invention discloses a method for reducing a minimum line width in a spacer-defined double patterning process of the present invention. In the method, the silicon nitride spacers can be converted into trenches in the interlayer dielectric layer by using a silicon dioxide film as a mask and by means of a chemically mechanical polishing process and an etching process, so that the minimum line width of the trenches can be determined by the width of the silicon nitride spacers, and thus a smaller line width can be achieved and the process can be simple and easy to control.

Abstract: A method for etching features into a silicon based etch layer through a patterned hard mask in a plasma processing chamber is provided. A silicon sputtering is provided to sputter silicon from the silicon based etch layer onto sidewalls of the patterned hard mask to form sidewalls on the patterned hard mask. The etch layer is etched through the patterned hard mask.

Abstract: Provided are methods of forming patterns of semiconductor devices, whereby patterns having various widths may be simultaneously formed, and a pattern density may be doubled by a double patterning process in a portion of the semiconductor device. A dual mask layer is formed on a substrate. A variable mask layer is formed on the dual mask layer. A first photoresist pattern having a first thickness and a first width in the first region, and a second photoresist pattern having a second thickness greater than the first thickness and a second width wider than the first width in the second region are formed on the variable mask layer. A first mask pattern and a first variable mask pattern are formed in the first region, and a second mask pattern and a second variable mask pattern are formed in the second region, by sequentially etching the variable mask layer and the dual mask layer by using, as etch masks, the first photoresist pattern and the second photoresist pattern.

Abstract: A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such structures.

Abstract: A method for realizing a nanometric circuit architecture includes: realizing plural active areas on a semiconductor substrate; realizing on the substrate a seed layer of a first material; realizing a mask-spacer of a second material on the seed layer in a region comprised between the active areas; realizing a mask overlapping the mask-spacer and extending in a substantially perpendicular direction thereto; selectively removing the seed layer exposed on the substrate; selectively removing the mask and the mask-spacer obtaining a seed-spacer comprising a linear portion extending in that region and a portion substantially orthogonal thereto; realizing by MSPT from the seed-spacer an insulating spacer reproducing at least part of the profile of the seed-spacer; realizing by MSPT a nano-wire of conductive material from the seed-spacer or insulating spacer, the nano-wire comprising a first portion at least partially extending in the region and a second portion contacting a respective active area.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of active regions, each having a first sidewall and a second sidewall, by etching a semiconductor substrate, forming an insulation layer on the first sidewall and the second sidewall, forming an etch stop layer filling a portion of each gap between the active regions, forming a recess exposing the insulation layer formed on any one sidewall from among the first sidewall and the second sidewall, and forming a side contact exposing a portion of any one sidewall from among the first sidewall and the second sidewall by selectively removing a portion of the insulation layer.

Abstract: A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having a plurality of different widths on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.

Abstract: A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to form the features on the target layer. Integrated circuit devices are also disclosed.

Abstract: A fin Field Effect Transistor (finFET), an array of finFETs, and methods of production thereof. The finFETs are provided on an insulating region, which may optionally contain dopants. Further, the finFETs are optionally capped with a pad. The finFETs provided in an array are of uniform height.

Abstract: A method for manufacturing an image sensor includes forming circuitry including a metal line over a semiconductor substrate, forming a photodiode over the metal line, and forming a contact plug in the photodiode such that the contact plug is connected to the metal line. The forming of the contact plug includes performing a first etch process to etch a portion of the photodiode, and performing a second etch process to expose a portion of the metal line by using a byproduct generated in etching, to form a via hole for the contact plug in the photodiode.