Formation Of Groove Or Trench Patents (Class 438/700)
  • Patent number: 8749070
    Abstract: The present disclosure relates to a dielectric solder barrier for a semiconductor die. In one embodiment, a semiconductor die includes a substrate, a semiconductor body on a first surface of the substrate, one or more first metallization layers on the semiconductor body opposite the substrate, a via that extends from a second surface of the substrate through the substrate and the semiconductor body to the one or more first metallization layers, and a second metallization layer on the second surface of the substrate and within the via. A portion of the second metallization layer within the via provides an electrical connection between the second metallization layer and the one or more first metallization layers. The semiconductor die further includes a dielectric solder barrier on the second metallization layer. Preferably, the dielectric solder barrier is on a surface of the portion of the second metallization layer within the via.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 10, 2014
    Assignee: Cree, Inc.
    Inventors: Helmut Hagleitner, Fabian Radulescu
  • Publication number: 20140154886
    Abstract: A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features.
    Type: Application
    Filed: February 4, 2014
    Publication date: June 5, 2014
    Applicant: Micron Technology, Inc.
    Inventors: William R. Brown, David Kewley, Adam Olson
  • Patent number: 8742442
    Abstract: A method for patterning an epitaxial substrate includes: (a) forming an etch mask layer over an epitaxial substrate, and patterning the etch mask layer using a patterned cover mask layer to form the etch mask layer into a plurality of spaced apart mask patterns; and (b) etching the epitaxial substrate that is exposed from the mask patterns, and removing the mask patterns such that the epitaxial substrate is formed with a plurality of spaced apart substrate patterns.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: June 3, 2014
    Assignee: Sino-American Silicon Products Inc.
    Inventors: Cheng-Hung Wei, Bo-Wen Lin, Ching-Yen Peng, Hao-Chung Kuo, Wen-Ching Hsu
  • Publication number: 20140148012
    Abstract: A stack of an organic planarization layer (OPL) and a template layer is provided over a substrate. The template layer is patterned to induce self-assembly of a copolymer layer to be subsequently deposited. A copolymer layer is deposited and annealed to form phase-separated copolymer blocks. An original self-assembly pattern is formed by removal of a second phase separated polymer relative to a first phase separated polymer. The original pattern is transferred into the OPL by an anisotropic etch, and the first phase separated polymer and the template layer are removed. A spin-on dielectric (SOD) material layer is deposited over the patterned OPL that includes the original pattern to form SOD portions that fill trenches within the patterned OPL. The patterned OPL is removed selective to the SOD portions, which include a complementary pattern. The complementary pattern of the SOD portions is transferred into underlying layers by an anisotropic etch.
    Type: Application
    Filed: August 16, 2012
    Publication date: May 29, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Steven J. Holmes, Chi-Chun Liu, Hiroyuki Miyazoe, Hsinyu Tsai
  • Publication number: 20140145391
    Abstract: A component carrier assembly (1) is provided which has a plurality of component carrier regions (10), which are intended for mounting semiconductor components. The component carrier assembly comprises a carrier body (2) with a first major face (21). On the first major face a trench pattern (3) is formed in the carrier body, with first trenches (31) extending parallel to one another in a first direction, the first trenches delimiting the component carrier regions in a second direction extending transversely of the trenches. A coating (4) is formed on the carrier body, such that the component carrier regions each have a first major face of the carrier body which is coated at least in places and a side face (5) of the trench pattern which is coated at least in places.
    Type: Application
    Filed: May 6, 2011
    Publication date: May 29, 2014
    Applicant: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Jürgen Dachs
  • Patent number: 8735294
    Abstract: A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device includes a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one implementation, a method for fabricating a vertically arranged LDMOS device includes forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: May 27, 2014
    Assignee: International Rectifier Corporation
    Inventor: Igor Bol
  • Patent number: 8735295
    Abstract: A method for fabricating a dual damascene structure includes the following steps. At first, a dielectric layer, a dielectric mask layer and a metal mask layer are sequentially formed on a substrate. A plurality of trench openings is formed in the metal mask layer, and a part of the metal mask layer is exposed in the bottom of each of the trench openings. Subsequently, a plurality of via openings are formed in the dielectric mask layer, and a part of the dielectric mask layer is exposed in a bottom of each of the via openings. Furthermore, the trench openings and the via openings are transferred to the dielectric layer to form a plurality of dual damascene openings.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: May 27, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Hsiao Lee, Hsin-Yu Chen, Yu-Tsung Lai, Jiunn-Hsiung Liao, Shih-Chun Tsai
  • Publication number: 20140141602
    Abstract: A method for producing a semiconductor device is provided. The method includes: forming in a semiconductor substrate a plurality of semiconductor mesas extending to an upper side so that adjacent semiconductor mesas are spaced apart from each other by one of a substantially empty trench and a trench substantially filled with a sacrificial layer selectively etchable with respect to the semiconductor mesas; forming a support structure mechanically connecting the semiconductor mesas spaced apart from each other by one of the substantially empty trench and the trench substantially filled with the sacrificial layer; and processing the semiconductor substrate from the upper side while the semiconductor mesas are mechanically connected via the support structure.
    Type: Application
    Filed: October 25, 2013
    Publication date: May 22, 2014
    Inventors: Kurt Sorschag, Daniel Sarlette, Felix Braun, Marcel Heller, Dieter Kaiser, Ingo Meusel, Marko Lemke, Anton Mauder, Helmut Strack
  • Patent number: 8728332
    Abstract: Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: May 20, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yi Lin, Jiing-Feng Yang, Tzu-Hao Huang, Chih-Hao Hsieh, Dian-Hau Chen, Hsiang-Lin Chen, Ko-Bin Kao, Yung-Shih Cheng
  • Patent number: 8728933
    Abstract: A method of kerf formation and treatment for solar cells and semiconductor films and a system therefor are described. A semiconductor film is backed by a first metal layer and topped by a second metal layer. A reference feature is defined on the film. An ultraviolet laser beam is aligned to the reference feature. A kerf is cut along the reference feature, using the ultraviolet laser beam. The beam cuts through the second metal layer, through the film and through the first metal layer. Cutting leaves debris deposited on walls of the kerf. The debris is cleaned off of the walls, using an acid-based solvent. In the case of solar cells, respective first terminals of the solar cells are electrically isolated by the cleaned kerf, and respective negative terminals of the solar cells are electrically isolated by the cleaned kerf.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: May 20, 2014
    Assignee: Alta Devices, Inc.
    Inventors: Michael Andres, Laila Mattos, Daniel G. Patterson, Gang He
  • Patent number: 8728943
    Abstract: A pattern forming method includes forming a spin on dielectric film on a substrate, washing the spin on dielectric film by using a washing liquid, drying a surface of the spin on dielectric film after the washing, forming a photosensitive film on the dried coating type insulation film, emitting energy rays to a predetermined position of the photosensitive film in order to form a latent image on the photosensitive film, developing the photosensitive film in order to form a photosensitive film pattern which corresponds to the latent image, and processing the spin on dielectric film with the photosensitive film pattern serving as a mask.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoyuki Takeishi, Hirokazu Kato, Shinichi Ito
  • Patent number: 8728906
    Abstract: A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: May 20, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Tai Chang, Yi-Shan Chen, Hsin-Chih Chen, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8722542
    Abstract: A method for patterning a layer at a bottom of a high aspect ratio feature of a substrate is described. The method includes providing the substrate having a first layer with a feature pattern overlying a second layer. The feature pattern is characterized with an initial critical dimension (CD), an initial corner profile, and an aspect ratio of 5:1 or greater. The method further includes etching through at least a portion of the second layer at the bottom of the feature pattern to extend the feature pattern at least partially into the second layer while retaining a final CD within a threshold of the initial CD and a final corner profile within a threshold of the initial corner profile using a gas cluster ion beam (GCIB) etching process.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 13, 2014
    Assignee: TEL Epion Inc.
    Inventors: Christopher K. Olsen, Luis Fernandez
  • Patent number: 8722518
    Abstract: A method is provided for forming a monolithic three dimensional memory array. The method includes forming a first memory level above a substrate, and monolithically forming a second memory level above the first memory level. The first memory level is formed by forming first substantially parallel conductors extending in a first direction, forming first pillars above the first conductors, each first pillar including a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, depositing a first dielectric layer above the first pillars, etching first trenches in the first dielectric layer, the first trenches extending in a second direction. After etching, a lowest point in the trenches is above a lowest point of the first conductive layer or layerstack, and the first conductive layer or layerstack does not include a resistivity-switching metal oxide or nitride. Numerous other aspects are provided.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: May 13, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Steven J. Radigan, Usha Raghuram, Samuel V. Dunton, Michael W. Konevecki
  • Patent number: 8721910
    Abstract: A process for manufacturing a membrane of nozzles of a spray device, comprising the steps of laying a substrate, forming a membrane layer on the substrate, forming a plurality of nozzles in the membrane layer, forming a plurality of supply channels in the substrate, each supply channel being substantially aligned in a vertical direction to a respective nozzle of the plurality of nozzles and in direct communication with the respective nozzle.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: May 13, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Angelo Antonio Merassi, Angelo Pesci, Benedetto Vigna, Ernestino Galeazzi, Marco Mantovani
  • Patent number: 8722507
    Abstract: A method for forming an identification mark on a silicon carbide single crystal substrate according to the present invention includes: (a) scanning a principal surface of a silicon carbide single crystal substrate with a laser beam at a first energy density such that a groove is formed in the principal surface of the silicon carbide single crystal substrate, thereby forming an identification mark which is constituted of one or more grooves in the principal surface of the silicon carbide single crystal substrate; and (b) scanning an inside of the groove formed in the principal surface of the silicon carbide single crystal substrate with a laser beam at a second energy density that is lower than the first energy density.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: May 13, 2014
    Assignee: Hitachi Metals, Ltd.
    Inventor: Sadahiko Kondo
  • Patent number: 8716126
    Abstract: Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: May 6, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas Werner, Peter Baars, Frank Feustel
  • Patent number: 8716137
    Abstract: According to an embodiment, a method for etching polycrystalline silicon includes a step of holding the polycrystalline silicon at a temperature higher than or equal to TE (K) given in a following equation; and a step of etching the polycrystalline silicon by dry etching with an etching gas containing CF4 and O2, T E = - 0.114 ? x + 0.0556 k × ln ? { ( 1 - r / d ) × - 6.27 ? x + 5.38 - 2.01 ? x + 3.11 } where d (nm) is etching amount of the polycrystalline silicon, r (nm) is surface roughness of the polycrystalline silicon after the etching, x is ratio of flow rate of CF4 gas to sum of flow rate of the CF4 gas and flow rate of O2 gas, and k (eV/K) is Boltzmann constant.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: May 6, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takayuki Sakai
  • Patent number: 8716138
    Abstract: Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 6, 2014
    Assignee: FlashSilicon Incorporation
    Inventor: Lee Wang
  • Patent number: 8709898
    Abstract: A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: April 29, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masahiro Fukuda, Eiji Yoshida, Yosuke Shimamune
  • Publication number: 20140110855
    Abstract: A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CDL). CDL is larger than a desired CD (CDD). A third layer is formed to fill the opening, leaving a top surface of the second layer exposed. The second layer is removed to produce a mesa formed by the third layer. The CD of the mesa is equal to about the first CD. The mesa is trimmed to produce a mesa with a second CD equal to about CDD. A fourth layer is formed to cover the first layer, leaving a top of the mesa exposed. The substrate is etched to remove the mesa and a portion of the first layer below the mesa to form an opening in the first layer with CDD.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zheng ZOU, Alex SEE, Huang LIU, Hai CONG
  • Patent number: 8703509
    Abstract: A method for manufacturing a substrate for liquid-ejecting heads includes etching a surface of a silicon substrate using a first etchant, with a silicon oxide layer as a mask, to form a depression as a part of a liquid supply port, and subsequently etching at least the silicon oxide layer and the thickness sandwiched between the depression and the etched surface of the silicon substrate with a second etchant to form the liquid supply port.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: April 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroyuki Abo, Keiji Watanabe, Keiji Matsumoto
  • Patent number: 8703570
    Abstract: A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced relative one another. Width of the spaced second features is laterally trimmed to a greater degree than any lateral trimming of width of the spaced first features while laterally trimming width of the spaced second features. After laterally trimming of the second features, spacers are formed on sidewalls of the spaced first features and on sidewalls of the spaced second features. The spacers are of some different composition from that of the spaced first features and from that of the spaced second features. After forming the spacers, the spaced first features and the spaced second features are removed from the substrate. The substrate is processed through a mask pattern comprising the spacers. Other embodiments are disclosed.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Scott Sills, Gurtej S. Sandhu, Anton deVilliers
  • Patent number: 8697580
    Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Ho Lee, Jae-Hwang Sim, Sang-Yong Park, Kyung-Lyul Moon
  • Patent number: 8697581
    Abstract: A III-nitride trench device has a vertical conduction region with an interrupted conduction channel when the device is not on, providing an enhancement mode device. The trench structure may be used in a vertical conduction or horizontal conduction device. A gate dielectric provides improved performance for the device by being capable of withstanding higher electric field or manipulating the charge in the conduction channel. A passivation of the III-nitride material decouples the dielectric from the device to permit lower dielectric constant materials to be used in high power applications.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: April 15, 2014
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Paul Bridger
  • Patent number: 8697579
    Abstract: A method of forming an isolation structure includes forming a trench at an upper portion of a substrate, forming a first oxide layer on an inner wall of the trench, oxidizing a portion of the substrate adjacent to the trench to form a second oxide layer such that the portion of the substrate adjacent to the trench has the first oxide layer thereon, forming a nitride layer on the first oxide layer, and forming an insulation layer pattern on the nitride layer such that the insulation layer pattern fills a remaining portion of the trench.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Sung Park, Se-Myeong Jang, Gil-Sub Kim
  • Patent number: 8697538
    Abstract: A method of forming a pattern in a substrate is provided, in which the substrate having a pattern region is provided first. A plurality of stripe-shaped mask layers is formed on the substrate in the pattern region. Each of at least two adjacent stripe-shaped mask layers among the stripe-shaped mask layers has a protrusion portion and the protrusion portions face to each other. A spacer is formed on sidewalls of the stripe-shaped mask layers, wherein a thickness of the spacer is greater than a half of a distance between two of the protrusion portions. Subsequently, the stripe-shaped mask layers are removed. An etching process is performed by using the spacer as a mask to form trenches in the substrate. Thereafter, the trenches are filled with a material.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: April 15, 2014
    Assignee: Winbond Electronics Corp.
    Inventor: Lu-Ping Chiang
  • Publication number: 20140099793
    Abstract: A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 10, 2014
    Applicants: Seoul National University R&DB Foundation, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Chul SUN, Byung-Gook PARK
  • Patent number: 8691701
    Abstract: A method for forming etched features in a low-k dielectric layer disposed below the photoresist mask in a plasma processing chamber is provided. Features are etched into the low-k dielectric layer through the photoresist mask. The photoresist mask is stripped, wherein the stripping comprising at least one cycle, wherein each cycle comprises a fluorocarbon stripping phase, comprising flowing a fluorocarbon stripping gas into the plasma processing chamber, forming a plasma from the fluorocarbon stripping gas, and stopping the flow of the fluorocarbon stripping gas into the plasma processing chamber and a reduced fluorocarbon stripping phase, comprising flowing a reduced fluorocarbon stripping gas that has a lower fluorocarbon flow rate than the fluorocarbon stripping gas into the plasma processing chamber, forming the plasma from the reduced fluorocarbon stripping gas, and stopping the flow of the reduced fluorocarbon stripping gas.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: April 8, 2014
    Assignee: Lam Research Corporation
    Inventors: Bing Ji, Andrew D. Bailey, III, Maryam Moravej, Stephen M. Sirard
  • Patent number: 8691691
    Abstract: The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Troy L. Graves-Abe, William F. Landers, Kevin S. Petrarca, Richard P. Volant
  • Patent number: 8691698
    Abstract: A method for etching features in a silicon layer disposed below a mask in a plasma processing chamber a plurality of cycles is provided. A deposition phase forming a deposition on the silicon layer in the plasma processing chamber is provided comprising providing a deposition gas into the plasma processing chamber wherein the deposition gas comprises a halogen containing etchant component and a fluorocarbon deposition component, forming the deposition gas into a plasma, which provides a net deposition on the silicon layer, and stopping the flow of the deposition gas. A silicon etch phase is provided, comprising providing a silicon etch gas into the plasma processing chamber that is different than the deposition gas, forming the silicon etch gas into a plasma to etch the silicon layer, and stopping the flow of the silicon etch gas.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: April 8, 2014
    Assignee: Lam Research Corporation
    Inventors: Qing Xu, William Thie, Camelia Rusu
  • Publication number: 20140094020
    Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.
    Type: Application
    Filed: December 4, 2013
    Publication date: April 3, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroki WAKIMOTO, Kenichi Iguchi, Koh Yoshikawa, Tsunehiro Nakajima, Shunsuke Tanaka, Masaaki Ogino
  • Patent number: 8685853
    Abstract: A method for creating a dual damascene structure while using only one lithography and masking step. Conventional dual damascene structures utilize two lithography steps: one to mask and expose the via, and a second step to mask and expose the trench interconnection. The novel method for creating a dual damascene structure allows for a smaller number of processing steps, thus reducing the processing time needed to complete the dual damascene structure. In addition, a lower number of masks may be needed. The exemplary mask or reticle used within the process incorporates different regions possessing different transmission rates. During the exposing step, light from an exposing source passes through the mask to expose a portion of the photoresist layer on top of the wafer.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Fan Chung Tseng, Chi Hsi Wu, Wei Ting Chien
  • Patent number: 8685860
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. Firstly, a semiconductor substrate having an active surface and a back surface is provided. The active surface is opposite to the back surface, and the semiconductor substrate includes at least one grounding pad disposed on the active surface. Secondly, at least one through silicon via is formed through the semiconductor substrate from the back surface to the active surface thus exposing the grounding pad. Then, a conductive layer is formed on the back surface of the semiconductor substrate and filled into the through silicon via to electrically connect to the grounding pad and the semiconductor substrate.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: April 1, 2014
    Assignee: Ineffable Cellular Limited Liability Company
    Inventor: Wen-Hsiung Chang
  • Patent number: 8679922
    Abstract: The method includes a step of forming a mask having an opening, for forming an opening in multiple insulating films, above a semiconductor substrate on which a member becoming a first insulating film, a member becoming a second insulating film being different from the member becoming the first insulating film, a member becoming a third insulating film, and a member becoming a fourth insulating film being different from the member becoming the third insulating film are stacked in this order; a first step of continuously removing the member becoming the fourth insulating film and the member becoming the third insulating film at a portion corresponding to the opening of the mask; and a second step of removing the member becoming the second insulating film, after the first step, at a portion corresponding to the opening of the mask.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: March 25, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takaharu Kondo, Takashi Usui
  • Patent number: 8673782
    Abstract: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-ho Park, Jae-kwan Park, Dong-hwa Kwak, So-wi Jin, Byung-jun Hwang, Nam-su Lim
  • Patent number: 8673785
    Abstract: A gas distribution system for supplying different gas compositions to a chamber, such as a plasma processing chamber of a plasma processing apparatus is provided. The gas distribution system can include a gas supply section, a flow control section and a switching section. The gas supply section provides first and second gases, typically gas mixtures, to the flow control section, which controls the flows of the first and second gases to the chamber. The chamber can include multiple zones, and the flow control section can supply the first and second gases to the multiple zones at desired flow ratios of the gases. The gas distribution system can continuously supply the first and second gases to the switching section and the switching section is operable to switch the flows of the first and second gases, such that one of the first and second process gases is supplied to the chamber while the other of the first and second gases is supplied to a by-pass line, and then to switch the gas flows.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: March 18, 2014
    Assignee: Lam Research Corporation
    Inventors: Zhisong Huang, Jose Tong Sam, Eric H. Lenz, Rajinder Dhindsa, Reza Sadjadi
  • Patent number: 8673673
    Abstract: A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. An interrupted trench structure separates the P-type doped region from the N-type doped region in some locations but allows the P-type doped region and the N-type doped region to touch in other locations. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. Among other advantages, the resulting solar cell structure allows for increased efficiency while having a relatively low reverse breakdown voltage.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: March 18, 2014
    Assignee: SunPower Corporation
    Inventors: Denis De Ceuster, Peter John Cousins, David D. Smith
  • Publication number: 20140070401
    Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Patent number: 8668833
    Abstract: A method of forming a discrete nanostructured element at one or more predetermined locations on a substrate is presented. The method includes forming a mask member over the substrate. A window is formed in the mask member at each of one or more locations at which it is required to form the nanostructured element thereby to expose a portion of a surface of the substrate. A portion of the substrate exposed by the window at the one or more locations is removed to form one or more recesses in the substrate. The method further includes forming a layer of a nanostructure medium over a surface of the recess and annealing the structure thereby to form the nanostructured element in each of the one or more recesses. The nanostructured element includes a portion of the nanostructure medium and has an external dimension along at least two substantially orthogonal directions of less than substantially 100 nm.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: March 11, 2014
    Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., National University of Singapore
    Inventors: Han Guan Chew, Fei Zheng, Wee Kiong Choi, Tze Haw Liew
  • Patent number: 8668835
    Abstract: A multi-step etch process wherein elliptical via openings and trench openings are formed in a dielectric layer includes supporting a multi-layer film stack on a temperature controlled electrostatic chuck in a plasma etch reactor. The multi-layer film stack has a dielectric layer and a patterned metal hard mask layer above the dielectric layer. An etchant gas is supplied to the plasma etch reactor. The etchant gas is energized into a plasma state, and via openings in a photo resist are transferred into a planarization layer and then into elliptical portions of the trench openings in a patterned hard mask layer while maintaining the chuck at a temperature of about 30 to 50° C. The elliptical openings are extended into a lower layer of the hard mask and into an underlying dielectric layer while maintaining the chuck at a temperature of 20° C. or below.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: March 11, 2014
    Assignee: Lam Research Corporation
    Inventors: Ananth Indrakanti, Bhaskar Nagabhirava
  • Patent number: 8664117
    Abstract: Provided is a semiconductor device manufacturing method enabling miniaturization by forming a hole in a vertical shape, capable of reducing the number of processes as compared to conventional methods, and capable of increasing productivity. The semiconductor device manufacturing method includes: forming a hole in a substrate; forming a polyimide film within the hole; anisotropically etching the substrate without using a mask covering a sidewall portion of the polyimide film within the hole and removing at least a part of a bottom portion of the polyimide film within the hole while the sidewall portion of the polyimide film remains within the hole; and filling the hole with a conductive metal.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: March 4, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Katsuyuki Ono, Yusuke Hirayama, Hideyuki Hatoh
  • Patent number: 8658537
    Abstract: According to one embodiment, a mask manufacturing method includes acquiring positional deviation information between an actual position of a pattern formed on a mask substrate and a design position decided at the time of designing the pattern; calculating an irradiating amount and an irradiating position of radiation to be irradiated to a predetermined area of a square on the mask substrate according to the calculated positional deviation information; and irradiating the radiation based on the calculated irradiating amount and the calculated irradiating position to form in a part of the mask substrate a heterogeneous layer of which volume is expanded more greatly than that of the surrounding mask substrate region.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: February 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masamitsu Itoh
  • Patent number: 8658538
    Abstract: A method of fabricating a memory device includes forming a plurality of first insulative blocks and a plurality of second insulative blocks arranged in an alternating manner in a substrate, forming a plurality of wide trenches in the substrate to form a plurality of protruding blocks, forming a word line on each sidewall of the protruding blocks, isolating the word line on each sidewall of the protruding block, and forming an trench filler in the protruding block to form two mesa structures, wherein the first insulative block and the second insulative block have different depths, and the wide trenches are transverse to the first insulative blocks.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: February 25, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
  • Patent number: 8653483
    Abstract: According to one embodiment, a mask manufacturing device includes a positional-deviation calculating unit that acquires positional deviation information between an actual position of a pattern formed on a mask substrate and a design position decided at the time of designing the pattern to a predetermined area of a square on the mask substrate; an irradiating-condition calculating unit that calculates an irradiating condition including an irradiating amount and an irradiating position of radiation to correct the positional deviation calculated to the predetermined area of a square on the mask substrate by using positional-deviation correction information, which indicates a relationship between the irradiating amount and the irradiating position of the radiation to the mask substrate and a pattern position change after irradiation of the radiation; and an irradiating unit that irradiates the mask substrate with the radiation under the irradiating condition calculated by the irradiating-condition calculating uni
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: February 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masamitsu Itoh
  • Patent number: 8652342
    Abstract: A semiconductor fabrication apparatus and a method of fabricating a semiconductor device using the same performs semiconductor etching and deposition processes at an edge of a semiconductor substrate after disposing the semiconductor substrate at a predetermined place in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus has lower, middle and upper electrodes sequentially stacked. The semiconductor substrate is disposed on the middle electrode. Semiconductor etching and deposition processes are performed on the semiconductor substrate in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus forms electrical fields along an edge of the middle electrode during performance of the semiconductor etching and deposition processes.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Kyung-Woo Lee, Jin-Sung Kim, Joo-Byoung Yoon, Yeong-Cheol Lee, Sang-Jun Park, Hee-Kyeong Jeon
  • Patent number: 8653665
    Abstract: There is provided a film forming method for forming a film on a target object having thereon an insulating layer 1 that is made of a low-k film and having a recess 2 whose bottom surface is exposed to a metallic layer 3. The film forming method includes forming a first-metal-containing film containing a first metal such as ruthenium (Ru); and after forming the first-metal-containing film, forming a second-metal-containing film containing a second metal such as a manganese (Mn) having a barrier property against a filling metal to be filled in the recess.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: February 18, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Hidenori Miyoshi
  • Patent number: 8652968
    Abstract: A method of fabricating a semiconductor device may include forming spacer line patterns on sidewalls of photoresist. A planarization etching process may be performed on a subsequently added planarization layer, after forming a mesh-shaped mask pattern from the spacer line patterns.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han Geun Yu, Eunsung Kim, Chulho Shin
  • Patent number: 8652337
    Abstract: A mechanism is provided for fabricating nanochannels for a nanodevice. Insulating film is deposited on a substrate. A nanowire is patterned on the film. Insulating material is deposited on the nanowire and film. A first circular hole is formed in the insulating material as an inlet, over a first tip of the nanowire to expose the first tip. A second circular hole is formed as an outlet, over a second tip of the nanowire opposite the first tip to expose the second tip. A nanochannel connects the first and second holes by etching away the nanowire via an etchant in the first and the second holes. A first reservoir is attached over the first hole in connection with the nanochannel at a previous location of the first tip. A second reservoir is attached over the second hole in connection with the nanochannel at a previous location of the second tip.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Binquan Luan, Gustavo A. Stolovitzky, Chao Wang, Deqiang Wang
  • Publication number: 20140045335
    Abstract: A photolithographic rinse solution includes deionized water, and a surfactant, the surfactant including a cyclic amine group and at least one non-amine cyclic group joined to or fused with the cyclic amine group, wherein the cyclic amine group includes a ring having a carbon number of 4 to 6, and the non-amine cyclic group includes a ring having a carbon number of 5 to 8.
    Type: Application
    Filed: August 8, 2013
    Publication date: February 13, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chawon KOH, Su Min KIM, Hyunwoo KIM, Hyojin YUN