Formation Of Groove Or Trench Patents (Class 438/700)
  • Publication number: 20150024601
    Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.
    Type: Application
    Filed: March 21, 2014
    Publication date: January 22, 2015
    Applicant: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Xuliang Zhou, Hongyan Yu, Shiyan Li, Jiaoqing Pan, Wei Wang
  • Patent number: 8937007
    Abstract: A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: January 20, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kenichi Watanabe, Nobuhiro Misawa, Satoshi Otsuka
  • Patent number: 8937017
    Abstract: Embodiments of the invention relate to a substrate etching method and apparatus. In one embodiment, a method for etching a substrate in a plasma etch reactor is provided that include flowing a backside process gas between a substrate and a substrate support assembly, and cyclically etching a layer on the substrate.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: January 20, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Alan Cheshire, Stanley Detmar
  • Patent number: 8932956
    Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Robert L. Bruce, Swetha Kamlapurkar
  • Patent number: 8932904
    Abstract: A semiconductor device including a graphene layer and a method of manufacturing the same are disclosed. A method in which graphene is grown on a catalyst metal by a chemical vapor deposition or the like is known. However, the graphene cannot be used as a channel, since the graphene is in contact with the catalyst metal, which is conductive. There is disclosed a method in which a catalyst film (2) is formed over a substrate (1), a graphene layer (3) is grown originating from the catalyst film (2), an electrode (4) in contact with the graphene layer (3) is formed, and the catalyst film (2) is removed.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: January 13, 2015
    Assignee: Fujitsu Limited
    Inventors: Daiyu Kondo, Shintaro Sato
  • Patent number: 8932947
    Abstract: Embodiments of the present invention provide methods to etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a Cl2 gas into the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, supplying a pulsed RF bias power in the etching gas mixture, and etching the portion of the silicon substrate exposed through the patterned photoresist layer in the presence of the plasma.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: January 13, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Joo Won Han, Kee Young Cho, Han Soo Cho, Sang Wook Kim, Anisul H. Khan
  • Patent number: 8932955
    Abstract: A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: January 13, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Jongsun Sel, Yuji Takahashi
  • Patent number: 8932957
    Abstract: A method includes receiving a substrate having an etch stop layer deposited over the substrate and a dummy mandrel layer deposited over the etch stop layer, forming a plurality of hard mask patterns using a hard mask layer deposited over the dummy mandrel layer, wherein the hard mask patterns includes a first dimension adjusted by a predetermined value, depositing a first spacer layer over the hard mask patterns, wherein a thickness of the first spacer layer is adjusted by the predetermined value, forming a plurality of spacer fins in the dummy mandrel layer, wherein the spacer fins include a second dimension, a first space, and a second space, performing a first fin cut process to remove at least one spacer fin, adjusting the second dimension to a target dimension, performing a second fin cut process, and forming a plurality of fin structures in the substrate by etching the spacer fins.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Chen-Yu Chen
  • Patent number: 8927433
    Abstract: Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: January 6, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Jin-Yeong Kang
  • Patent number: 8927436
    Abstract: The present invention relates to a method for forming a trench that can remove residual particles in a trench using a metal mask, a method for forming a metal wire, and a method for manufacturing a thin film transistor array panel. The method for forming a trench includes: forming a first insulating layer on a substrate; forming a first metal layer on the first insulating layer; forming an opening by patterning the first metal layer; forming a trench by dry-etching the first insulating layer using the patterned first metal layer as a mask; and wet-etching the substrate. The dry-etching is performed using a main etching gas and a first auxiliary etching gas, and the first auxiliary etching gas includes argon.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dae Ho Kim, Bong-Kyun Kim, Yong-Hwan Ryu, Hong Sick Park, Wang Woo Lee, Shin Il Choi
  • Patent number: 8927427
    Abstract: A method including introducing a dopant into a region of a substrate, etching a deep trench in the substrate through the region, gettering impurities introduced during etching of the deep trench using a pentavalent ion formed from a reaction between an element of the substrate and the dopant, wherein the charge of the pentavalent ion attracts the impurities, and filling the deep trench with a conductive material.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Troy L. Graves-Abe, Brian J. Greene, Chandrasekharan Kothandaraman
  • Publication number: 20150001687
    Abstract: Various embodiments provide double patterning methods and structures. In an exemplary method, a to-be-etched layer can be provided. A stress layer can be formed on the to-be-etched layer. The stress layer can have a tensile stress. A plurality of discrete sacrificial layers can be formed on the stress layer. A sidewall-spacer material layer covering the plurality of sacrificial layers and the stress layer can be formed. The sidewall-spacer material layer can be etched to form a sidewall spacer on a sidewall of each sacrificial layer of the plurality of sacrificial layers. The stress layer at each side of the each sacrificial layer can be etched to form a groove passing through a thickness of the stress layer. The plurality of sacrificial layers can be removed.
    Type: Application
    Filed: February 12, 2014
    Publication date: January 1, 2015
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: PETER ZHANG, JEFFERY HE, STEVEN ZHANG
  • Patent number: 8921954
    Abstract: A method for providing a semiconductor structure includes forming a sacrificial structure by etching a plurality of trenches from a first main surface of a substrate. The method further includes covering the plurality of trenches at the first main surface with a cover material to define cavities within the substrate, removing a part of the substrate from a second main surface opposite to the first main surface to a depth at which the plurality of trenches are present, and etching away the sacrificial structure from the second main surface of the substrate.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: December 30, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thoralf Kautzsch, Stefan Kolb, Boris Binder, Bernd Foeste, Marco Mueller
  • Patent number: 8921199
    Abstract: A method for fabricating a resistor in a dielectric layer of an integrated circuit (IC) is disclosed. The method may include creating a trench with a first side, a second side opposing the first side, and a bottom, in the dielectric layer, and depositing a conformal film onto the first side, the second side and the bottom of the trench. The method may also include removing the conformal film from the bottom and the second side of the trench, and filling the trench with an insulator. The method may also include removing the conformal film from the first side of the trench to form a receptacle adjacent to the insulator, and depositing electrically resistive material into the receptacle to form a resistor.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Patent number: 8921188
    Abstract: One illustrative method disclosed herein includes forming a trench within an isolated region of a bulk semiconductor substrate, forming a region of an insulating material in the trench and forming a semiconductor material within the trench and above the upper surface of the region of insulating material. A substrate disclosed herein includes an isolated substrate region in a bulk semiconductor substrate, a region of an insulating material that is positioned within a trench defined in the isolated substrate region and a semiconductor material positioned within the trench and above the upper surface of the region of insulating material.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: December 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ram Asra
  • Patent number: 8916474
    Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor package having a first semiconductor die, which is disposed in a first encapsulant. An opening is disposed in the first encapsulant. A second semiconductor package including a second semiconductor die is disposed in a second encapsulant. The second semiconductor package is disposed at least partially within the opening in the first encapsulant.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: December 23, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef H•glauer
  • Patent number: 8916943
    Abstract: An integrated circuit device includes a first layer comprising at least two partial cavities, an intermediate layer bonded to the first layer, the intermediate layer formed to support at least two Micro-electromechanical System (MEMS) devices, and a second layer bonded to the intermediate layer, the second layer comprising at least two partial cavities to complete the at least two partial cavities of the first layer through the intermediate layer to form at least two sealed full cavities. The at least two full cavities have different pressures within.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shyh-Wei Cheng, Jui-Chun Weng, Hsi-Cheng Hsu, Chih-Yu Wang, Jung-Kuo Tu, Che-Jung Chu, Yu-Ting Hsu
  • Patent number: 8916475
    Abstract: A patterning method is provided. A mask composite layer and a first tri-layer photoresist are sequentially formed on a target layer. A first etching is performed to the mask composite layer, using the first tri-layer photoresist as a mask, to form at least one first opening in an upper portion of the mask composite layer. The first tri-layer photoresist is removed. A second tri-layer photoresist is formed on the mask composite layer. A second etching is performed to the mask composite layer, using the second tri-layer photoresist as a mask, to form at least one second opening in the upper portion of the mask composite layer. The second tri-layer photoresist is removed. A lower portion of the mask composite layer is patterned by using the upper portion of the mask composite layer as a mask. The target layer is patterned by using the patterned mask composite layer as a mask.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: December 23, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Hsuan-Hsu Chen, Cheng-Hsing Chuang
  • Patent number: 8910380
    Abstract: Described is a process for producing an inkjet printhead comprising an aperture face having an oleophobic surface. The process includes forming an aperture plate by disposing a silicon layer on an aperture plate; using photolithography to create a textured pattern on an outer surface of the silicon layer; and chemically modifying the textured surface by disposing a conformal, oleophobic coating on the textured surface. The oleophobic aperture plate may be used as a front face surface for an inkjet printhead.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: December 16, 2014
    Assignee: Xerox Corporation
    Inventors: Kock-Yee Law, Hong Zhao
  • Patent number: 8907491
    Abstract: A silicon structure is fabricated determining a pattern for wire trenches and air gaps. The wire trenches are created, and certain trenches are used as air gaps. The remaining wire trenches are used for metallization of inter connecting wires.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 9, 2014
    Assignee: Intel Corporation
    Inventor: Marc Van Veenhuizen
  • Patent number: 8900990
    Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: December 2, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Walter Kleemeier, Cindy Goldberg
  • Patent number: 8901004
    Abstract: A method of producing plurality of etched features in an electronic device is disclosed that avoids micro-loading problems thus maintaining more uniform sidewall profiles and more uniform critical dimensions. The method comprises performing a first time-divisional plasma etch process step within a plasma chamber to a first depth of the plurality of etched features, and performing a flash process step to remove any polymers from exposed surfaces of the plurality of etched features without requiring an oxidation step. The flash process step is performed independently of the time-divisional plasma etch step. A second time-divisional plasma etch process step is performed within the plasma chamber to a second depth of the plurality of etched features. The method may be repeated until a desired etch depth is reached.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: December 2, 2014
    Assignee: Lam Research Corporation
    Inventors: Tom Kamp, Qian Fu, I. C. Jang, Linda Braly, Shenjian Liu
  • Patent number: 8901005
    Abstract: Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Habib Hichri, Xi Li, Richard Wise
  • Publication number: 20140349486
    Abstract: Some embodiments include methods of forming patterns utilizing copolymer. A main body of copolymer may be formed across a substrate, and self-assembly of the copolymer may be induced to form a pattern of structures across the substrate. A uniform thickness throughout the main body of the copolymer may be maintained during the inducement of the self-assembly. In some embodiments, the uniform thickness may be maintained through utilization of a wall surrounding the main body of copolymer to impede dispersal of the copolymer from the main body. In some embodiments, the uniform thickness may be maintained through utilization of a volume of copolymer in fluid communication with the main body of copolymer.
    Type: Application
    Filed: August 8, 2014
    Publication date: November 27, 2014
    Inventors: Scott E. Sills, Dan Millward
  • Patent number: 8895445
    Abstract: A method for forming vias and trenches for an interconnect structure on a substrate includes exposing via pitch reduction patterns in a photoresist layer, developing the patterns to remove the via pitch reduction patterns, etching the photoresist layer partially using a polymer gas to reshape the pattern into small via shapes, and etching the remaining photoresist layer to extend the reshaped pattern. The reshaped small via shape patterns have a smaller pitch than the via pitch reduction patterns in a long direction. For via pitch reduction patterns having two vias each, the pattern has a peanut-shape. During the reshaping etch operation, the polymer gas deposits more in a pinched-in middle section while allowing downward etch in unpinched sections.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Kuo Hsieh, Marowen Ng, Ming-Chung Liang, Hsin-Yi Tsai
  • Patent number: 8894868
    Abstract: A method of forming an aperture (e.g., a through via, a blind via, a trench, an alignment feature, etc.) within a substrate includes irradiating a substrate with a laser beam to form a laser-machined feature having a sidewall. The laser-machined feature is then processed to change at least one characteristic (e.g., the sidewall surface roughness, diameter, taper, aspect ratio, cross-sectional profile, etc.) of the laser-machined feature. The laser-machined feature can be processed to form the aperture by performing an isotropic wet-etch process employing an etchant solution containing HNO3, HF and, optionally acetic acid.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: November 25, 2014
    Assignee: Electro Scientific Industries, Inc.
    Inventors: Andy Hooper, Daragh Finn, Tim Webb, Lynn Sheehan, Kenneth Pettigrew, Yu Chong Tai
  • Patent number: 8895446
    Abstract: A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Hao-Ming Lien
  • Patent number: 8895400
    Abstract: A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: November 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Yun-Gi Kim, Young-Woong Son, Bong-Soo Kim
  • Publication number: 20140332932
    Abstract: Various embodiments provide shallow trenches and fabrication methods. In an exemplary method, a semiconductor substrate can be provided. A mask layer can be provided on the semiconductor substrate. An etch-cleaning process can be performed. The etch-cleaning process can include etching the semiconductor substrate to form a shallow trench by one or more etching steps using the mask layer as an etch mask. The etch-cleaning process can further include performing a plasma cleaning process after each of the one or more etching steps. The plasma cleaning process can use a plasma that is electronegative.
    Type: Application
    Filed: October 17, 2013
    Publication date: November 13, 2014
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: HAIYANG ZHANG, DONGJIANG WANG
  • Patent number: 8883647
    Abstract: Disclosed herein are a trench substrate and a method of manufacturing the same. The trench substrate includes a base substrate, an insulating layer formed on one side or both sides of the base substrate and including trenches formed in a circuit region and a dummy region positioned at a peripheral edge of the trench substrate, and a circuit layer formed in the trenches of the circuit region through a plating process and including a circuit pattern and vias. Thanks to formation of the trenches in the dummy region and the cutting region, deviation in thickness of a plating layer formed on the insulating layer in a plating process is improved upon.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: November 11, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Gwan Ko, Ryoichi Watanabe, Sang Soo Lee
  • Patent number: 8883571
    Abstract: A method of manufacturing a transistor includes: forming an oxide semiconductor film and a gate electrode on a substrate, the oxide semiconductor film having a channel region, and the gate electrode facing the channel region; and forming an insulating film covering the gate electrode and the oxide semiconductor film. Infiltration of moisture from the insulating film into the oxide semiconductor film is suppressed by the substrate.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: November 11, 2014
    Assignee: Sony Corporation
    Inventors: Narihiro Morosawa, Motohiro Toyota
  • Patent number: 8883630
    Abstract: A method of forming contact holes includes: forming a first conductive layer and a second conductive layer; forming an insulating layer on the first conductive layer and the second conductive layer; forming a photoresist pattern which exposes first and second etch surfaces of a top surface of the insulating layer; performing a first etching process on the insulating layer at a first etching rate; and performing a second etching process on the insulating layer at a second etching rate which is higher than the first etching rate, after a top surface of the first conductive layer is exposed through the insulating layer. The first etch surface is on the first conductive layer, the second etch surface is on the second conductive layer, and a distance between the second etch surface and the second conductive layer is greater than a distance between the first etch surface and the first conductive layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Yong Jae Jang
  • Patent number: 8877634
    Abstract: The inventive concept provides methods of manufacturing semiconductor devices having a fine pattern. In some embodiments, the methods comprise forming an etch-target film on a substrate, forming a first mask pattern on the etch-target film, forming a second mask pattern by performing an ion implantation process in the first mask pattern, and etching the etch-target film using the second mask pattern.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Woon Shin, Bong-Hyun Kim, Su-Min Kim, Hyo-Jung Kim, Chang-Min Park, Soo-Jin Hong
  • Patent number: 8877610
    Abstract: In various embodiments, a method of patterning a substrate may include: forming an auxiliary layer on or above a substrate and forming a plasma etch mask layer on or above the auxiliary layer, wherein the auxiliary layer is configured such that it may be removed from the substrate more easily than the plasma etch mask layer; patterning the plasma etch mask layer and the auxiliary layer such that at least a portion of the substrate is exposed; patterning the substrate by means of a plasma etch process using the patterned plasma etch mask layer as a plasma etch mask.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: November 4, 2014
    Assignee: Infineon Technologies AG
    Inventor: Manfred Engelhardt
  • Patent number: 8877648
    Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. A step is performed to selectively etch through the semiconductor active layer and the sacrificial layer in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. A step can be performed to selectively etch through the capping layer and the first portion of the semiconductor active layer to thereby expose the sacrificial layer.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: November 4, 2014
    Assignee: Semprius, Inc.
    Inventors: Christopher Bower, Etienne Menard, Matthew Meitl
  • Publication number: 20140322871
    Abstract: Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.
    Type: Application
    Filed: July 14, 2014
    Publication date: October 30, 2014
    Inventors: Long-Shih Lin, Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Paul Chu
  • Patent number: 8871105
    Abstract: A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: October 28, 2014
    Assignee: Lam Research Corporation
    Inventors: Jaroslaw W. Winniczek, Frank Y. Lin, Alan J. Miller, Qing Xu, Seongjun Heo, Jin Hwan Ham, Sang Joon Yoon, Camelia Rusu
  • Patent number: 8871649
    Abstract: One illustrative method disclosed herein involves forming a layer of insulating material, forming a patterned layer of photoresist above the layer of insulating material, wherein the patterned layer of photoresist has an opening defined therein, forming an internal spacer within the opening in the patterned layer of photoresist, wherein the spacer defines a reduced-size opening, performing an etching process through the reduced-size opening on the layer of insulating material to define a trench/hole type feature in the layer of insulating material, and forming a conductive structure in the trench/hole type feature in the layer of insulating material.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 28, 2014
    Assignees: GLOBALFOUNDRIES Inc., Renesas Electronics Corporation, International Business Machines Corporation
    Inventors: Linus Jang, Yoshinori Matsui, Chiahsun Tseng
  • Patent number: 8871615
    Abstract: According to one embodiment, a method includes forming a first SiGe layer having a first profile of a concentration of Ge on a semiconductor substrate, forming a second SiGe layer having a second profile of a concentration of Ge on the first SiGe layer, the second profile lower than a first peak of the first profile, forming a mask layer on the second SiGe layer, etching the first and second SiGe layers by anisotropic etching using the mask layer as a mask to form trenches, selectively removing the first SiGe layer exposed into the trenches to form a cavity under the second SiGe layer, and oxidizing side and lower surfaces of the second SiGe layer exposed in the trenches and the cavity to increase the concentration of Ge in the second SiGe layer.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinji Mori
  • Patent number: 8871648
    Abstract: In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in an integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Gurtej S. Sandhu, Ardavan Niroomand
  • Patent number: 8872301
    Abstract: The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Yang Hung, Po-Zen Chen, Szu-Hung Yang, Chih-Cherng Jeng, Chih-Kang Chao, I-I Cheng
  • Patent number: 8859430
    Abstract: A method for protecting an exposed low-k surface is described. The method includes providing a substrate having a low-k insulation layer formed thereon and one or more mask layers overlying the low-k insulation layer with a pattern formed therein. Additionally, the method includes transferring the pattern in the one or more mask layers to the low-k insulation layer using one or more etching processes to form a trench and/or via structure in the low-k insulation layer. The method further includes forming an insulation protection layer on exposed surfaces of the trench and/or via structure during and/or following the one or more etching processes by exposing the substrate to a film forming compound containing C, H, and N. Thereafter, the method includes removing at least a portion of the one or more mask layers using a mask removal process.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: October 14, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Yuki Chiba
  • Patent number: 8859396
    Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gordon M. Grivna, John M. Parsey, Jr.
  • Publication number: 20140302678
    Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.
    Type: Application
    Filed: February 19, 2014
    Publication date: October 9, 2014
    Inventors: Alex Paterson, Do Young Kim, Gowri Kamarthy, Helene Del Puppo, Jen-Kan Yu, Monica Titus, Radhika Mani, Noel Yui Sun, Nicolas Gani, Yoshie Kimura, Ting-Ying Chung
  • Patent number: 8853089
    Abstract: A manufacturing method of a semiconductor substrate includes: forming a trench in a semiconductor board by a dry etching method; etching a surface portion of an inner wall of the trench by a chemical etching method so that a first damage layer is removed, wherein the surface portion has a thickness equal to or larger than 50 nanometers; and performing a heat treatment at temperature equal to or higher than 1050° C. in non-oxidizing and non-azotizing gas so that crystallinity of a second damage layer is recovered, wherein the second damage layer is disposed under the first damage layer. The crystallinity around the trench is sufficiently recovered.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: October 7, 2014
    Assignee: DENSO CORPORATION
    Inventors: Hiroshi Ohtsuki, Takumi Shibata
  • Patent number: 8852448
    Abstract: A method for fabricating a 3D (three-dimensional) structure is disclosed to provide hydrophobicity to a surface of a 3D structure by using a dipping method in which a predetermined-shaped structure is immersed in a molten metal solution. The method includes: immersing a predetermined-shaped structure in a molten metal solution to coat a molten metal material on the surface of the predetermined-shaped structure; anodizing a metal base coated with the molten metal material; coating a polymer material on an outer surface of the metal-coated base to form a negative replica structure; covering an outer surface of the negative replica structure with an outer formation material; and removing the metal-coated base from the negative replica structure and the outer formation material.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: October 7, 2014
    Assignee: Postech Academy-Industry Foundation
    Inventors: Dong-Seob Kim, Kun-Hong Lee, Woon-Bong Hwang, Geun-Bae Lim, Hyun-Chul Park, Byeong-Joo Lee, Sang-Min Lee, Joon-Won Kim
  • Patent number: 8853090
    Abstract: A method for fabricating a through-silicon via comprises the following steps. Provide a substrate. Form a through silicon hole in the substrate having a diameter of at least 1 ?m and a depth of at least 5 ?m. Perform a first chemical vapor deposition process with a first etching/deposition ratio to form a dielectric layer lining the bottom and sidewall of the through silicon hole and the top surface of the substrate. Perform a shape redressing treatment with a second etching/deposition ratio to change the profile of the dielectric layer. Repeat the first chemical vapor deposition process and the shape redressing treatment at least once until the thickness of the dielectric layer reaches to a predetermined value.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 7, 2014
    Assignee: IPEnval Consultant Inc.
    Inventors: Chao-Yuan Huang, Yueh-Feng Ho, Ming-Sheng Yang, Hwi-Huang Chen
  • Patent number: 8853862
    Abstract: Embodiments of the present invention provide a contact structure for transistor. The contact structure includes a first epitaxial-grown region between a first and a second gate of, respectively, a first and a second transistor; a second epitaxial-grown region directly on top of the first epitaxial-grown region with the second epitaxial-grown region having a width that is wider than that of the first epitaxial-grown region; and a silicide region formed on a top portion of the second epitaxial-grown region with the silicide region having an interface, with rest of the second epitaxial-grown region, that is wider than that of the first epitaxial-grown region. In one embodiment, the second epitaxial-grown region is at a level above a top surface of the first and second gates of the first and second transistors.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Reinaldo Vega
  • Patent number: 8846538
    Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: September 30, 2014
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Bomy Chen, Long Ching Wang, Sychi Fang
  • Patent number: RE45180
    Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yun Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang