Abstract: A thermosetting silicon-containing film-forming composition for forming a silicon-containing film to be formed in a multi-layer resist process used in lithography, the composition including at least: (A) a silicon-containing compound obtained by hydrolysis-condensation of a hydrolyzable silicon compound and compound(s) selected from the group consisting of a hydrolyzable silicon compound and a reactive compound; (B) a thermal crosslinking accelerator; (C) an organic acid with one, or two or more valency having 1 to 30 carbon atoms; and (D) an organic solvent.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes preparing an underlying structure; forming a protective film above the underlying structure; forming a trench into the protective film and the underlying structure; filling the trench with a fill material; planarizing the fill material such that the protective film is exposed; forming a sacrificial film above the fill material and the protective film; and reactive ion etching the sacrificial film and the fill material. The fill material is selectively etched back within the trench.

Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.

Abstract: A cleaning solution is provided. The cleaning solution includes a fluorine containing compound, an inorganic acid, a chelating agent containing a carboxylic group and water for balance. The content of the fluorine containing compound is 0.01-0.5 wt % of. The content of the inorganic acid is 1-5 wt %.

Abstract: The invention includes methods in which one or more components of a carboxylic acid having an aqueous acidic dissociation constant of at least 1×10?6 are utilized during the etch of oxide (such as silicon dioxide or doped silicon dioxide). Two or more carboxylic acids can be utilized. Exemplary carboxylic acids include trichloroacetic acid, maleic acid, and citric acid.

Abstract: A method of forming a trench is provided that includes providing a stack having a semiconductor layer or dielectric layer, a metal nitride layer, a leveling layer, and a first mask layer. First trenches are etched through the first mask layer and the leveling layer. The first mask layer is removed. A second mask layer is formed on the leveling layer. Second trenches are formed through the second mask layer, wherein the base of the second trenches do not extend through the metal nitride layer. The second mask layer is removed. Exposed portions of the metal nitride layer are etched selectively to the semiconductor layer and remaining portions of the leveling layer to extend the first trenches and the second trenches into contact with an upper surface of the semiconductor layer.

Abstract: A lower layer of a microelectronic device may be patterned by forming a first sacrificial layer on the lower layer; patterning a plurality of spaced apart trenches in the first sacrificial layer; forming a second sacrificial layer in the plurality of spaced apart trenches; patterning the second sacrificial layer in the plurality of spaced apart trenches to define upper openings in the plurality of spaced apart trenches; and patterning the lower layer using the first and second sacrificial layers as a mask to form lower openings in the lower layer.

Abstract: An electronic component has at least one contact surface situated in a contact plane, at least one insulating layer disposed above the contact plane, at least one stabilizing layer disposed on the insulating layer for increasing a mechanical stability of the component, and at least one of a bonding contact and a soldering contact. The insulating layer and the stabilizing layer have at least one opening which opens in an upper side of the stabilizing layer. The upper side of the stabilizing layer is oriented away from the contact surface. The opening extends through the stabilizing layer and the insulating layer as far as the contact surface. The at least one of a bonding contact and a soldering contact extends over the stabilizing layer and touches the contact surface through the opening.

Abstract: Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns; and a pre-plating layer formed on both upper and lower surfaces of the die pad and the lead patterns.

Abstract: A diode assembly comprising first and second diodes each having a different breakdown voltage, each of the first and second diodes comprising a semiconductor substrate; an electrically conducting channel layer on the semiconductor substrate; an upper semiconductor layer on the channel layer, the upper semiconductor layer comprising a recess; first and second ohmic contacts on the upper semiconductor layer on opposite sides of the recess, the ohmic contacts being connected together to form a first diode contact; a gate electrode within the recess, the gate electrode forming a second diode contact; wherein the area of the recess of the first diode covered by the first gate electrode is different to the area of the recess of the second diode covered by the second gate electrode.

Abstract: A substrate processing method that forms an opening, which has a size that fills the need for downsizing a semiconductor device and is to be transferred to an amorphous carbon film, in a photoresist film of a substrate to be processed. Deposit is accumulated on a side wall surface of the opening in the photoresist film using plasma produced from a deposition gas having a gas attachment coefficient S of 0.1 to 1.0 so as to reduce the opening width of the opening.

Abstract: In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core.

Abstract: During the patterning of sophisticated metallization systems, a damaged surface portion of a sensitive low-k dielectric material may be efficiently replaced by a well-controlled dielectric material, thereby enabling an adaptation of the material characteristics and/or the layer thickness of the replacement material. Thus, established lithography and etch techniques may be used in combination with reduced critical dimensions and dielectric materials of even further reduced permittivity.

Abstract: In a semiconductor device producing method according to one embodiment, an insulating film containing silicon is formed on a semiconductor substrate, a resist is deposited on the insulating film, the resist is patterned into a predetermined pattern, and the insulating film is processed by a dry etching treatment in which gas containing C, F, Br, H, and O is used with the resist having the predetermined pattern as a mask. A deposited film in which C and Br are coupled is produced on the resist.

Abstract: A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern.

Abstract: Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

Abstract: A method of manufacturing a nano structure by etching, using a substrate containing Si. A focused Ga ion or In ion beam is irradiated on the surface of the substrate containing Si. The Ga ions or the In ions are injected while sputtering away the surface of the substrate so that a layer containing Ga or In is formed on the surface of the substrate. Dry etching by a gas containing fluorine (F) is performed with the layer containing the Ga or the In formed on the surface of the substrate taken as an etching mask, and the nano structure is formed having a pattern of at least 2 ?m tin in depth according to a predetermined line width.

Abstract: According to one embodiment, a method of producing a mask includes: a step of forming a pattern on a substrate; a step of forming a first film that covers the top surface and side surface of the pattern and contains a first material; a step of forming a second film containing a second material on the first film; a step of performing anisotropic etching of the first and second films in a way that forms a sidewall layer including the first and second films on the side surface of the pattern and removes the first and second films on any location other than the sidewall layer; a step of performing isotropic etching of the first film of the sidewall layer; and a step of removing the pattern.

Abstract: Transistors are formed using pitch multiplication. Each transistor includes a source region and a drain region connected by strips of active area material separated by shallow trench isolaton structures. The shallow trench isolaton structures are formed by dielectric material filling trenches that are formed by pitch multiplication. During pitch multiplication, rows of spaced-apart mandrels are formed and spacer material is blanket deposited over the mandrels. The spacer material is etched to define spacers on sidewalls of the mandrels and the mandrels are subsequently removed, thereby leaving free-standing spacers. The spacers constitute a mask, through which an underlying substrate is etched to form the trenches and strips of active area material. The trenches are filled to form the shallow trench isolaton structures. The substrate is doped to form source, drain and channel regions and a gate is formed over the channel region.

Abstract: A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.

Abstract: The present invention provides a method for manufacturing a structure over a semiconductor substrate. To form a trench, a patterned layer is formed on a portion of a substrate such that the patterned layer forms a target area located adjacent an edge of the patterned layer. A self-assembled monolayer (SAM) is coupled to the substrate up to the patterned layer, but excluded from the patterned layer. The substrate is then removed within the target area. A wire is formed in a similar fashion except that the first SAM is exchanged with a second SAM in the target area. Then either the substrate outside of the target area is removed, or conductive metal crystals are grown within the target area. Such structures may be advantageously used in the manufacture of a number of active or passive electronic devices, such as a field effect transistor.

Abstract: Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

Abstract: An object of one embodiment of the present invention is to provide a polishing slurry which can reduce dishing and erosion of a to-be-polished semiconductor wafer. The polishing slurry contains an oxidizing agent and two or more kinds of abrasive grains for polishing, i.e., fumed silica and colloidal silica. A ratio (selectivity ratio) between a polishing rate of a metal film such as a tungsten film and a polishing rate of an insulating film (oxide film) such as a SiO2 film can be adjusted by changing a mixing ratio between fumed silica and colloidal silica, and dishing and erosion of the semiconductor wafer can be thus reduced.

Abstract: This invention comprises methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a semiconductor substrate is provided. An antireflective coating is formed over the semiconductor substrate. The antireflective coating has an outer surface. The outer surface is treated with a basic fluid. A positive photoresist is applied onto the outer surface which has been treated with the basic treating fluid. The positive photoresist is patterned and developed effective to form a patterned photoresist layer having increased footing at a base region of said layer than would otherwise occur in the absence of said treating the outer surface. Other aspects and implementations are contemplated.

Abstract: A method of manufacturing a semiconductor device having shallow trench isolation includes steps of forming a hard mask layer on the substrate surface, etching a trench through the hard mask, filling the trench with an isolation material, forming a recessed trench, and forming a serpentine gate structure to connect electronic sources and drains.

Abstract: Winged via structures to increase overlay margin are generally described. In one example, a method comprises depositing a sacrificial layer to an interlayer dielectric, the interlayer dielectric being coupled with a semiconductor substrate, forming at least one trench structure in the sacrificial layer wherein the trench structure comprises a first direction along a length of the trench structure and a second direction along a width of the trench structure wherein the second direction is substantially perpendicular to the first direction, depositing a light sensitive material to the trench structure and the sacrificial layer, and patterning at least one winged via structure in the light sensitive material to overlay the trench structure wherein the winged via structure extends in the second direction beyond the width of the trench structure onto the sacrificial layer.

Abstract: A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask.

Abstract: A method of fabricating a semiconductor device including at least one of the following steps: forming an oxide layer on and/or over a silicon substrate. Forming a first photoresist pattern on and/or over the oxide layer. Forming a trench by etching the oxide layer and the substrate using the first photoresist pattern as a mask. Removing the first photoresist pattern. Filling the trench with a trench oxide layer. Planarizing the trench oxide layer. Forming an etch stop layer on and/or over the trench oxide layer. Forming a second photoresist pattern on and/or over the etch stop layer. Etching the etch stop layer and the trench oxide layer using the second photoresist pattern as an etch mask. Removing the second photoresist pattern and the etch stop layer.

Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film.

Abstract: A method of manufacturing a semiconductor device includes forming a first mask pattern on a substrate by using a material including a polymer having a protection group de-protectable by an acid, the first mask pattern having a plurality of holes; forming a capping layer on an exposed surface of the first mask pattern, the capping layer including an acid source; diffusing the acid source into the first mask pattern so that the protection group becomes de-protectable from the polymer in the first mask pattern; forming a second mask layer on the capping layer, the second mask layer separate from the first mask pattern and filling the plurality of holes in the first mask pattern; and forming a plurality of second mask patterns in the plurality of holes by removing the capping layer and the first mask pattern.

Abstract: According to one embodiment, a method of producing a mask includes: a step of forming a pattern on a substrate; a step of forming a first film that covers the top surface and side surface of the pattern and contains a first material; a step of forming a second film containing a second material on the first film; a step of performing anisotropic etching of the first and second films in a way that forms a sidewall layer including the first and second films on the side surface of the pattern and removes the first and second films on any location other than the sidewall layer; a step of performing isotropic etching of the first film of the sidewall layer; and a step of removing the pattern.

Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.

Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.

Abstract: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

Abstract: In sophisticated semiconductor devices, the initial strain component of a globally strained semiconductor layer may be substantially preserved during the formation of shallow trench isolations by using a rigid mask material, which may efficiently avoid or reduce a deformation of the semiconductor islands upon patterning the isolation trenches. Consequently, selected regions with high internal stress levels may be provided, irrespective of the height-to-length aspect ratio, which may limit the application of globally strained semiconductor layers in conventional approaches. Furthermore, in some illustrative embodiments, active regions of substantially relaxed strain state or of inverse strain type may be provided in addition to the highly strained active regions, thereby enabling an efficient process strategy for forming complementary transistors.

Abstract: A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask.

Abstract: A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed.

Abstract: A method of lithography patterning includes forming a mask layer on a material layer and forming a capping layer on the mask layer. The capping layer is a boron-containing layer with a higher resistance to an etching reaction of patterning process of the material layer. By adapting the boron-containing layer as the capping layer, the thickness of the mask layer can be thus reduced. Hence, a better gap filling for forming an interconnect metallization in the material layer could be achieved as well.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.

Abstract: Methods are provided for fabricating devices. A first layer is formed. A hardmask on the first layer is formed. Features on the hardmask are patterned. The sizes of features on the hardmask are reduced by applying a plasma treatment process to form reduced size features. Also, the size of features on the hardmask can be enlarged to form enlarged size features by applying the plasma treatment process and/or removing the oxidized part of the feature during plasma treatment process. Another method may include a first layer formed on a substrate and a second layer formed on the first layer. First features are patterned on the first layer, and second features are patterned on the second layer. A size of second features on the second layer is closed due to the different oxidation rate of the two layers during the plasma treatment process, to form a self-sealed channel and/or self-buried trench.

Abstract: Methods of forming deep trenches in substrates are described. A method includes providing a substrate with a patterned film disposed thereon, the patterned film including a trench having a first width and a pair of sidewalls, the trench exposing the top surface of the substrate. The method also includes forming a material layer over the patterned film and conformal with the trench. The method also includes etching the material layer to form sidewall spacers along the pair of sidewalls of the trench, the sidewall spacers reducing the first width of the trench to a second width. The method also includes etching the substrate to form a deep trench in the substrate, the deep trench undercutting at least a portion of the sidewall spacers.

Abstract: A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer.

Abstract: Barrier layers and methods for forming barrier layers on a porous layer are provided. The methods can include chemically adsorbing a plurality of first molecules on a surface of the porous layer in a chamber and forming a first layer of the first molecules on the surface of the porous layer. A plasma can then be used to react a plurality of second molecules with the first layer of first molecules to form a first layer of a barrier layer. The barrier layers can seal the pores of the porous material, function as a diffusion barrier, be conformal, and/or have a negligible impact on the overall ILD k value of the porous material.

Abstract: A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurality of nanotubes may be substantially surrounded with a supporting material. Additionally, at least some of the plurality of nanotubes may be selectively shortened and at least a portion of the at least some of the plurality of nanotubes may be functionalized. Methods for forming semiconductor structures intermediate structures, and semiconductor devices are disclosed. An intermediate structure, intermediate semiconductor structure, and a system including nanotube structures are also disclosed.

Abstract: A method for manufacturing a semiconductor device is provided, the method includes forming a coated film by coating a solution containing a solvent and an organic component above an insulating film located above a semiconductor substrate and having a recess, baking the coated film at a first temperature which does not accomplish cross-linking of the organic component to obtain an organic film precursor, polishing the organic film precursor using a slurry containing resin particles to leave the organic film precursor in the recess, baking the left organic film precursor at a second temperature which is higher than the first temperature to remove the solvent to obtain a first organic film embedded in the recess, forming a second organic film on the insulating film, thereby obtaining an underlying film, forming an intermediate layer and a resist film successively above the underlying film, and subjecting the resist film to patterning exposure.

Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.

Abstract: Disclosed are one-port and two-port microelectromechanical structures including variable capacitors, switches, and filter devices. High aspect-ratio micromachining is used to implement low-voltage, large value tunable and fixed capacitors, and the like. Tunable capacitors can move in the plane of the substrate by the application of DC voltages and achieve greater than 240 percent of tuning. Exemplary microelectromechanical apparatus comprises a single crystalline silicon substrate, and a conductive structure laterally separated from the single crystalline silicon substrate by first and second high aspect ratio gaps of different size, wherein at least one of the high aspect ratio gaps has an aspect ratio of at least 30:1, and is vertically anchored to the single crystalline silicon substrate by way of silicon nitride.

Abstract: A method for forming a fine pattern having a variable width by simultaneously using an optimal focused electron beam and a defocused electron beam in a light exposure process Includes, after forming a first film on a substrate, forming a first film pattern including a first level area and a second level area having different distances from the substrate by changing a profile of an upper surface of the first film. A photoresist film having a first area covering the first level area and a second area covering the second level area is formed. To simultaneously light-expose the first area and the second area with the same width, a light exposure condition, in which an optimal focused electron beam is eradiated on the first area and a defocused electron beam is eradiated on the second area, is applied.

Abstract: As a step in performing a process on a structure, a hole pattern is provided in a thin layer of organic resin masking material formed over the structure to provide a process mask. A processing step is then performed through the openings in the mask, and after a processing step is completed the mask is adjusted by a re-flow process in which the structure is placed into an atmosphere of solvent vapor of a solvent of the mask material. By way of the re-flow process, the mask material softens and re-flows to reduce the size of the openings in the mask causing edges of the surface areas on which the processing step was performed to be covered by the mask for subsequent processing steps.