Abstract: In a semiconductor device fabricating process, a copper-based metal film is formed on an insulating layer, and an insulating film is formed on the copper-based metal film. A patterned resist film is formed on the insulating film, and the insulating film is dry-etched using the patterned resist film as a mask to form a hole penetrating through the insulating film. Thereafter, a plasma treatment using an non-oxidizing gas is carried out, and furthermore, a wet treatment using a resist remover liquid is carried out, for removing the resist film and a resist surface hardened layer which was generated in the dry-etching.

Abstract: The present invention relates to a method for forming a gate of a semiconductor device that uses a cobalt silicide. The method for forming the gate of the semiconductor device can include preparing a semiconductor substrate, form a first insulation layer on the semiconductor substrate, form a doped polycrystalline silicon layer simultaneously with a deposition or after the deposition and forming a cobalt silicide layer by another deposition or by reacting a cobalt layer with the polycrystalline silicon layer. The cobalt silicide layer is selectively removed by using at least one etchant gas selected from a group of a gas including a chlorine atom group, a gas mixture of the gas including the chlorine atom group and oxygen, a gas mixture of the gas including the chlorine atom group and an inert gas, and a gas including the above-enumerated gases and a gas having a fluorine atom group. Then, the polycrystalline silicon layer is patterned.

Abstract: Titanium-containing films exhibiting excellent uniformity and step coverage are deposited on semiconductor wafers in a cold wall reactor which has been modified to discharge plasma into the reaction chamber. Titanium tetrabromide, titanium tetraiodide, or titanium tetrachloride, along with hydrogen, enter the reaction chamber and come in contact with a heated semiconductor wafer, thereby depositing a thin titanium-containing film on the wafer's surface. Step coverage and deposition rate are enhanced by the presence of the plasma. The use of titanium tetrabromide or titanium tetraiodide instead of titanium tetrachloride also increases the deposition rate and allows for a lower reaction temperature. Titanium silicide and titanium nitride can also be deposited by this method by varying the gas incorporated with the titanium precursors.

Abstract: An interconnection is formed on a semiconductor substrate having a semiconductor element formed thereon. Next, a passivation film is formed on the semiconductor substrate including the interconnection. Further, a polyimide film, which is served as a buffer coating film, is formed on the passivation film. Further, the polyimide film is patterned. Next, the passivation film is subject to etching while the patterned polyimide film is taken as a mask. Next, a hardened layer, which is formed on the surface of the polyimide film as a result of etching, is removed through ashing process. Next, the semiconductor substrate after ashing process is cured so as to transform the polyimide film into imide.

Abstract: The present invention provides a method for hermetically sealing a semiconductor laser element, by which the cleanness of a package can be maintained extremely satisfactorily in a stabilized state, in order to prevent organic substances from being adhered to the end faces of high output semiconductor laser elements due to photochemical actions. The method comprises the first step of introducing oxygen into a chamber of a hermetical-sealing apparatus and irradiating ultraviolet rays onto an unsealed package having a semiconductor laser element mounted, in the chamber, and the second step of purging the chamber with an inert gas and hermetically sealing an unsealed package in the inert gas atmosphere without being exposed to the outer atmosphere.

Abstract: A method of manufacturing a semiconductor substrate includes the steps of laminating a first substrate having a single-crystal semiconductor region with a second substrate having an insulator region, and selectively removing the portion of the first substrate of the laminated substrates where lamination strength is weak.

Abstract: A semiconductor substrate is provided. A number of rows of layer stacks are formed on the semiconductor substrate with a shallow trench positioned between two adjacent layer stacks. Each layer stack is a polysilicon layer and a sacrificial layer and has two side walls. Each side wall of the layer stack intersects the bottom of the shallow trench at an angle of approximately 90 degrees. A HDPCVD silicon oxide layer is deposited to cover the layer stacks and the shallow trenches followed by a planarization process to remove portions of the HDPCVD silicon oxide layer to expose in the sacrificial layer. Then, the sacrificial layer is removed. An insulating layer, a word line layer, and a photoresist layer are formed on the polysilicon layer, respectively. The photoresist layer is patterned so as to define a position for forming a word line.

Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device on a first surface of a silicon carbide substrate and with at least one metal contact for the device on the first surface of the substrate. The opposite, second surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished second surface of the silicon carbide substrate to define a predetermined location for a via that is opposite the device metal contact on the first surface; etching the desired via through the desired masked location until the etch reaches the metal contact on the first surface; and metallizing the via to provide an electrical contact from the second surface of the substrate to the metal contact and to the device on the first surface of the substrate.

Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Å can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2C12) as the main reactive agent.

Abstract: A method of manufacturing a capacitor in semiconductor devices, the method comprising forming a silicon oxide film on a surface of a silicon substrate; forming a nitride film on said silicon oxide film; forming a contact hole; depositing a doped polysilicon layer; performing an etch-back process to remove a portion of said doped polysilicon layer; forming an ohmic contact layer over said doped polysilicon layer in said contact hole; forming an anti-diffusion film on said ohmic contact layer; forming a silicate glass film; forming a concave hole by etching a portion of said silicate glass film; forming a Ruthenium lower electrode on said internal wall of said concave hole; forming a BST dielectric film on said first Ruthenium electrode; crystallizing said BST dielectric film; forming an upper electrode on said BST dielectric film, thereby forming a capacitor; and performing a thermal treatment to stabilize said capacitor.

Abstract: A plasma processing method that controls an interior of a vacuum chamber to a specified pressure by introducing gas into the vacuum chamber and evacuating the interior of the vacuum chamber. A high-frequency power having a frequency of 50 MHz to 3 GHz is supplied to a site of an antenna other than its center and periphery with the antenna provided opposite to a substrate in the vacuum chamber, in a state where a general center of the antenna and the vacuum chamber are short-circuited to each other. Meanwhile, the interior of the vacuum chamber is controlled to the specified pressure, and plasma is generated within the vacuum chamber and the substrate placed on a substrate electrode is processed within the vacuum chamber.

Abstract: The present invention provides a semiconductor manufacturing method, a plasma processing method and a plasma processing apparatus for generating a plasma in a processing chamber and carrying out processing on material to be processed by using the plasma, comprising a floating-foreign-particle measuring apparatus including: a light radiating optical system for radiating a light having a desired wavelength and completing intensity modulation at a desired frequency to the processing chamber; a scattered-light detecting optical system for separating a component with the desired wavelength from scattered lights obtained from the processing chamber as a result of radiation of the light by the light radiating optical system, for optically receiving the component and for converting the component into a first signal; and a foreign-particle-signal extracting unit which separates a second signal representing foreign particle floating in the plasma or in an area in proximity to the plasma from a third signal obtained by

Abstract: A method and apparatus for accelerating a laser stripping process carried out in a reactive gas mixture, comprising carrying out the stripping process in the presence of an accelerating effective amount of NxOy gas.

Abstract: A silicon nitride deposition method includes providing a substrate surface. Silicon is predeposited on at least a portion of the surface. After predeposition of the silicon, silicon nitride is deposited. The substrate surface may include one or more component surfaces and when at least a monolayer of silicon is predeposited thereon silicon nitride nucleation at the substrate surface is performed at a substantially equivalent rate independent of the different component surfaces.

Abstract: An improved vacuum plasma etching device for plasma etching semiconductor wafers that have a photo-resist pattern. The improved plasma etching device has a reaction chamber in which the plasma etching is performed during a process cycle, an entrance vacuum loadlock for holding the next semiconductor wafer to be plasma etched, an exit vacuum loadlock for transporting the semiconductor wafers out of the reaction chamber after the plasma etching process, and a source of ultraviolet light. Exposing the semiconductor wafer to the ultraviolet light cures the photo-resist patterns, thereby improving CD dispersion, enhancing pattern transfer, and preventing photo-resist reticulation. Curing the photo-resist patterns while the semiconductor wafer is being held during the process cycle in the entrance vacuum loadlock, increases efficiency and productivity.

Abstract: A method of manufacturing a semiconductor substrate includes the steps of laminating a first substrate having a single-crystal semiconductor region with a second substrate having an insulator region, and selectively removing the portion of the first substrate of the laminated substrates where lamination strength is weak.

Abstract: A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.

Abstract: It is an object of the present invention to provide a cleaning method of and a cleaning apparatus for removing organic matters such as phthalates that have deposited on the surface of a semiconductor substrate while restraining the growth of a natural oxide film. The present invention provides a method of cleaning a semiconductor substrate, which comprises irradiating a semiconductor substrate contaminated by organic matters such as phthalic acid, phthalate and derivatives thereof with vacuum ultraviolet light having a wavelength within a range from 165 to 179 nm in an atmosphere of oxygen or air that is introduced from an O2 or air intake port, thereby decomposing and removing the contaminant.

Abstract: An improved method of forming a via on a semiconductor substrate forms a conductive line thereon and then forms an inter-metal dielectric layer over the conductive line. A patterned photoresist layer is formed on the inter-metal dielectric layer. A portion of the inter-metal dielectric layer is removed to expose the conductive line using the photoresist layer as a mask to form a via hole, wherein the via hole is subsequently used to form a via. A high density plasma process is performed to remove the photoresist layer. The photoresist layer remaining on the substrate is removed with a solvent.

Abstract: A method for simultaneously stripping a photoresist mask employed for etching, in a low pressure, high density plasma processing chamber, a contact hole through an oxide layer to a silicon layer of a substrate and soft etching a surface of the silicon layer at a bottom of the contact hole. The technique of simultaneously stripping and soft etching is configured to substantially remove the photoresist mask and reducing a contact resistance at the bottom of the contact hole simultaneously. The method includes flowing an etchant source gas comprising a fluorocarbon and O2into the plasma processing chamber after the contact hole is formed but prior to filling the contact hole with a substantially conductive material. There is also included forming a plasma from the etchant source gas.

Abstract: A method of etching a metal layer on a semiconductor device using an in-situ plasma cleaning step following the metal etch. The process begins by forming a metal layer over a semiconductor substrate. A photoresist mask is formed over the metal layer. The metal layer is patterned by dry etching unmasked areas of the metal layer in a plasma etching chamber. Polymer formations are formed during etching on the metal sidewalls and the walls of the plasma etching chamber. A novel plasma cleaning step is performed in-situ to partially remove the photoresist and to soften and partially remove the polymer formations formed on the metal sidewalls during etching. The plasma cleaning also partially removes polymer from the walls of the plasma etching chamber. The substrate is removed from the plasma etching chamber, and placed in an ashing chamber, and the remaining photoresist is removed. The substrate is removed from the ashing chamber and the remaining polymer formations are removed in a wet etch process.

Abstract: In one aspect, the invention includes a method of patterning a substrate. A film is formed over a substrate and comprises a plurality of individual molecules. The individual molecules comprise two ends with one of the two ends being directed toward the substrate and the other of the two ends being directed away from the substrate. Particle-adhering groups are bound to said other of the two ends of at least some of the individual molecules and a plurality of particles are adhered to the particle-adhering groups to form a mask over the substrate. The substrate is etched while the mask protects portions of the substrate. In another aspect, the invention encompasses a method of forming a field emission display. A material having a surface of exposed nitrogen-containing groups is formed over the substrate. At least one portion of the material is exposed to radiation while at least one other portion of the material is not exposed.

Abstract: A silicon nitride deposition method includes providing a substrate surface including one or more component surfaces. At least a monolayer of silicon is predeposited on the one or more component surfaces resulting in a substantially native oxide free uniform predeposited silicon substrate surface. A silicon nitride layer is then deposited on the predeposited silicon substrate surface after the silicon predeposition.

Abstract: Stepped photoresist profiles provide various methods of forming profiles in an underlying substrate. The stepped photoresist profiles are formed in two layers of photoresist that are disposed over the substrate. The substrate is then etched twice using a respective opening in each photoresist layer to create a stepped profile in the substrate.

Abstract: There is provided a method of dry etching a nickel film formed on a substrate by means of plasma of an etching gas, wherein the etching gas includes at least one of CO and CO.sub.2 gases, and the substrate is kept at a temperature in the range of -25.degree. C. to 40.degree. C. both inclusive, while the substrate is being etched. For instance, the etching gas is a mixture gas including CO and CO.sub.2 gases, a mixture gas including CO, CO.sub.2 and H.sub.2 gases, or a mixture gas including CO and H.sub.2 gases. The above-mentioned method provides higher etching accuracy, higher etching rate, and less etching damage in a substrate.

Abstract: The present invention provides a plasma processing system comprising a remote plasma activation region for formation of active gas species, a transparent transfer tube coupled between the remote activation region and a semiconductor processing chamber, and a source of photo energy for maintaining activation of the active species during transfer from the remote plasma activation region to the processing chamber. The source of photo energy preferably includes an array of UV lamps. Additional UV lamps may also be used to further sustain active species and assist plasma processes by providing additional in-situ energy through a transparent window of the processing chamber.

Abstract: An integrated circuit fabrication process in which residual fluorine contamination on metal surfaces after ashing is removed by exposure to an NH.sub.3 /O.sub.2 plasma.

Abstract: A method and apparatus for depositing an etch stop layer. The method begins by introducing process gases into a processing chamber in which a substrate is disposed. An etch stop layer is then deposited over the substrate. An overlying layer is then deposited over the etch stop layer. The etch stop layer substantially protects underlying materials from the etchants used in patterning the overlying layer. Moreover, the etch stop layer also possesses advantageous optical characteristics, making it suitable for use as an antireflective coating in the patterning of layers underlying the etch stop layer.

Abstract: A method of producing etched structures in substrates by anisotropic plasma etching, wherein an essentially isotropic etching operation and side wall passivation are performed separately and in alternation, with the substrate being a polymer, a metal or a multicomponent system, and portions of the side wall passivation layer applied during passivation of the side wall are transferred to the exposed side surfaces of the side wall during the subsequent etching operations, so the entire method is anisotropic as a whole.

Abstract: A method for forming a patterned polysilicon layer within a microelectronics fabrication. There is first provided a substrate layer employed within a microelectronics fabrication. There is then formed upon the substrate layer a blanket polysilicon layer. There is then formed upon the blanket polysilicon layer a blanket organic polymer layer. There is then formed upon the blanket organic polymer layer a patterned photoresist layer, where the patterned photoresist layer has a high areal density region and a low areal density region. There is then etched through a first plasma etch method while employing the patterned photoresist layer as an etch mask layer the blanket organic polymer layer to form a patterned organic polymer layer while reaching the blanket polysilicon layer.

Abstract: A method for removing native oxides and other contaminants from a wafer surface while minimizing the loss of a desired film on the wafer surface. The method is carried out in a hermetically sealed reactor. A fluorine-containing gas or gas mixture is passed over the wafer during simultaneous exposure to ultraviolet radiation in the absence of added water, hydrogen, hydrogen fluoride or hydrogen containing organics, thereby avoiding the production of water as a reaction product. The addition of ultraviolet radiation and the elimination of water, hydrogen, hydrogen fluoride and hydrogen containing organics provides for the nearly equivalent (non-selective) removal of various forms of oxide and also provides for improved process control.

Abstract: A method for etching through a low capacitance dielectric layer in a plasma processing chamber. The low capacitance dielectric layer is disposed below a hard mask layer on a substrate. The method includes flowing an etch chemistry that includes N.sub.2 and H.sub.2 into the plasma processing chamber. There is included creating a plasma out of the etch chemistry. The method also includes etching, using the plasma, through the low capacitance dielectric layer through openings in the hard mask layer in the plasma processing chamber.

Abstract: An interconnect layer is fabricated using a tungsten hard mask by forming a tungsten based layer over an aluminum based layer. A photoresist layer is deposited over the tungsten based layer and patterned. The tungsten based layer is patterned by applying a fluorine-based etchant using the photoresist layer as an etch mask. Then the aluminum based layer is patterned by applying a chlorine based etchant using the tungsten based layer as an etch mask.

Abstract: A method of fabricating a DRAM device having nitride/oxide or tantalum pentoxide dielectric layers. The method includes: forming field oxide regions on a substrate to define active regions; forming at each active region a MOSFET comprising a top dielectric layer; forming a contact window in the MOSFET top dielectric layer; generating a doped poly-Si bottom electrode of a capacitor in electrical connection with the MOSFET through the contact window; removing surface oxide of the bottom electrode using both chemical and inductive coupled plasma (ICP) treatments; depositing nitride/oxide dielectric layers or a tantalum pentoxide dielectric layer on the ICP-treated bottom electrode; generating a doped poly-Si top electrode of the capacitor.

Abstract: A method for forming a gate dielectric (14b) begins by providing a substrate (12). A high K dielectric layer (14a) is deposited overlying the substrate (12). The dielectric layer (14a) contains bulk traps (16) and interface traps (18). A polysilicon gate electrode (20) is then patterned and etched overlying the gate dielectric (14a) whereby the plasma etching of the gate electrode (20) results in substrate plasma damage (22). A post gate wet oxidation process is performed between 750.degree. C. and 850.degree. C. to reduce plasma etch damage and trap sites (16, 18) in order to provide an improved gate dielectric (14b). Source and drain electrodes (30) are then formed within the substrate and laterally adjacent the gate electrode (20) to form a transistor device having more consistent threshold voltages, improved subthreshold slope operation, reduced gate to channel leakage, and improved speed of operation.

Abstract: A method for producing a semiconductor device capable of stably removing a sidewall mask layer without removal of an etching stopper film, wherein a conductive layer 30 and a first diffusion layer 11 are formed in a semiconductor substrate 10, an etching stopper film 21 is formed covering the conductive layer 30, a sidewall mask layer 31b containing silicon is formed at an upper layer of the etching stopper film 21 facing a sidewall surface of the conductive layer 30, and a second diffusion layer 12 is formed. Here, a conductive impurity is introduced into at least the sidewall mask layer 31b at either of the time of formation of the sidewall mask layer 31b or the time of formation of the second diffusion layer 12, and heat treatment for activating the conductive impurity in the sidewall mask layer 31b is applied.

Abstract: A process is described for etching contact holes though a dielectric layer down to a silicon surface. Initial etching, until the silicon is exposed, is performed in a suitable plasma environment under high RF power. This results in damage to the newly exposed silicon surface. Said damage is repaired by exposing the silicon and the photoresist to an atmosphere that includes carbon tetrafluoride and atomic oxygen. The latter oxidizes the damaged layer, allowing it to be removed by the former. Much of the photoresist is also removed by the atomic oxygen, any that still remains being then removed using a wet etch. At the user's option, the silicon may be allowed to overetch during the high RF power application and/or a low power RF step may be introduced to partially remove silicon surface damage prior to the atomic oxygen treatment.

Abstract: A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed upon the substrate a pair of microelectronic structures. There is then formed sequentially upon the substrate including the pair of microelectronic structures a first conformal dielectric layer followed by a second conformal dielectric layer followed by a third dielectric layer, where the second conformal dielectric layer serves as an etch stop layer with respect to the third dielectric layer in a first plasma etch method employed in forming in part a via through the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer at a location between the pair of microelectronic structures.

Abstract: A plasma etch method for patterning for use within an integrated circuit a blanket conductor layer such that an integrated circuit layer adjoining the blanket conductor layer is not damaged when the blanket conductor layer is patterned to form a patterned conductor layer through the plasma etch method. There is first provided a semiconductor substrate. There is then formed over the semiconductor substrate a blanket conductor layer, where the blanket conductor layer communicates electrically with the semiconductor substrate in a fashion such that an electrical charge is shunted from the blanket conductor layer into the semiconductor substrate when the blanket conductor layer is patterned to form the patterned conductor layer through the plasma etch method. There is then patterned through the plasma etch method the blanket conductor layer to form the patterned conductor layer.